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-rw-r--r--src/mainboard/google/sarien/variants/arcada/gpio.c4
-rw-r--r--src/mainboard/google/sarien/variants/sarien/gpio.c4
2 files changed, 6 insertions, 2 deletions
diff --git a/src/mainboard/google/sarien/variants/arcada/gpio.c b/src/mainboard/google/sarien/variants/arcada/gpio.c
index 2a0ead82a9..a88e0b1190 100644
--- a/src/mainboard/google/sarien/variants/arcada/gpio.c
+++ b/src/mainboard/google/sarien/variants/arcada/gpio.c
@@ -211,7 +211,6 @@ static const struct pad_config gpio_table[] = {
/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */
/* I2C5_SDA */ PAD_NC(GPP_H10, NONE), /* ISH_I2C2_SDA */
/* I2C5_SCL */ PAD_NC(GPP_H11, NONE), /* ISH_I2C2_SCL */
-/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 1, DEEP), /* D3 cold RST */
/* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */
/* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE),
/* M2_SKT2_CFG3 */ PAD_CFG_GPO(GPP_H15, 1, DEEP), /* BT_RADIO_DIS# */
@@ -240,6 +239,8 @@ static const struct pad_config gpio_table[] = {
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
+/* SSD RESET pin will stay low first */
+/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 0, DEEP), /* D3 cold RST */
/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */
/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */
/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */
@@ -251,6 +252,7 @@ static const struct pad_config early_gpio_table[] = {
/* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */
/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */
/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */
+/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 1, DEEP), /* D3 cold RST */
};
const struct pad_config *variant_gpio_table(size_t *num)
diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c
index 19fd45cdea..53a937ff39 100644
--- a/src/mainboard/google/sarien/variants/sarien/gpio.c
+++ b/src/mainboard/google/sarien/variants/sarien/gpio.c
@@ -197,7 +197,6 @@ static const struct pad_config gpio_table[] = {
/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */
/* I2C5_SDA */ PAD_NC(GPP_H10, NONE),
/* I2C5_SCL */ PAD_NC(GPP_H11, NONE),
-/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 1, DEEP), /* /D3 cold RST */
/* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */
/* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE),
/* M2_SKT2_CFG3 */ PAD_CFG_GPO(GPP_H15, 1, DEEP), /* BT_RADIO_DIS# */
@@ -225,6 +224,7 @@ static const struct pad_config gpio_table[] = {
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
+/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 0, DEEP), /* D3 cold RST */
/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */
/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */
/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */
@@ -236,6 +236,8 @@ static const struct pad_config early_gpio_table[] = {
/* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */
/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */
/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */
+/* SSD RESET need to stay low first */
+/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 1, DEEP), /* D3 cold RST */
/* PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* SIO_PWRBTN# */
};