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-rw-r--r--src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c13
-rw-r--r--src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb4
2 files changed, 16 insertions, 1 deletions
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c
index 6897658ad5..d13a97bee9 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <bootblock_common.h>
+#include <device/pnp_ops.h>
#include <northbridge/intel/sandybridge/raminit.h>
#include <northbridge/intel/sandybridge/pei_data.h>
#include <southbridge/intel/bd82x6x/pch.h>
@@ -11,11 +12,23 @@
#include <option.h>
#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1)
+#define GPIO0_DEV PNP_DEV(0x2e, NCT6779D_WDT1_GPIO01_V)
void bootblock_mainboard_early_init(void)
{
nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ nuvoton_pnp_enter_conf_state(GPIO0_DEV);
+
+ /* Turn on DRAM_LED. If raminit dies, this would remain on and we know
+ * we have a problem. We turn it off in ramstage. */
+ pnp_set_logical_device(GPIO0_DEV);
+ pnp_write_config(GPIO0_DEV, 0x30, 0x02);
+ pnp_write_config(GPIO0_DEV, 0xe0, 0x7f);
+ pnp_write_config(GPIO0_DEV, 0xe1, 0x00);
+
+ nuvoton_pnp_exit_conf_state(GPIO0_DEV);
+
/*
* TODO: Put PCIe root port 7 (00:1c.6) into subtractive decode and have it accept I/O
* cycles. This should allow a POST card in the PCI slot, connected via an ASM1083
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
index 6232c9be83..41351b5bdd 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
@@ -59,6 +59,9 @@ chip northbridge/intel/sandybridge
end
device pnp 2e.6 off end # CIR
device pnp 2e.8 off end # WDT1
+ device pnp 2e.108 on # GPIO 0
+ drq 0xe1 = 0x80 # GP07 high turns DRAM_LED off
+ end
device pnp 2e.a on # ACPI
drq 0xe4 = 0x10 # Enable 3VSBSW#, needed for S3 suspend
drq 0xe7 = 0x11 # HWM reset by LRESET#, 0.5s S3 delay for compatibility
@@ -78,7 +81,6 @@ chip northbridge/intel/sandybridge
end
device pnp 2e.9 off end # GPIO 8
device pnp 2e.308 on end # GPIO by I/O
- device pnp 2e.108 on end # GPIO 0
device pnp 2e.109 on end # GPIO 1
device pnp 2e.209 on # GPIO 2
drq 0xe0 = 0xbf # GP26 output