summaryrefslogtreecommitdiff
path: root/src/mainboard
diff options
context:
space:
mode:
Diffstat (limited to 'src/mainboard')
-rwxr-xr-xsrc/mainboard/google/cyan/devicetree.cb3
-rwxr-xr-xsrc/mainboard/intel/strago/devicetree.cb3
2 files changed, 2 insertions, 4 deletions
diff --git a/src/mainboard/google/cyan/devicetree.cb b/src/mainboard/google/cyan/devicetree.cb
index c36ae3d235..8932cf4391 100755
--- a/src/mainboard/google/cyan/devicetree.cb
+++ b/src/mainboard/google/cyan/devicetree.cb
@@ -72,8 +72,7 @@ chip soc/intel/braswell
register "ISPPciDevConfig" = "3"
# LPE audio codec settings
- register "lpe_codec_clk_freq" = "25" # 25MHz clock
- register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
+ register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock
# Enable devices in ACPI mode
register "lpss_acpi_mode" = "1"
diff --git a/src/mainboard/intel/strago/devicetree.cb b/src/mainboard/intel/strago/devicetree.cb
index c2aa47aa6e..2bca939dfa 100755
--- a/src/mainboard/intel/strago/devicetree.cb
+++ b/src/mainboard/intel/strago/devicetree.cb
@@ -72,8 +72,7 @@ chip soc/intel/braswell
register "ISPPciDevConfig" = "3"
# LPE audio codec settings
- register "lpe_codec_clk_freq" = "25" # 25MHz clock
- register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
+ register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock
# Enable devices in ACPI mode
register "lpss_acpi_mode" = "1"