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-rw-r--r--src/mainboard/emulation/qemu-q35/bootblock.c4
-rw-r--r--src/mainboard/google/beltino/Kconfig1
2 files changed, 2 insertions, 3 deletions
diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c
index 939a4e6320..68df39f27a 100644
--- a/src/mainboard/emulation/qemu-q35/bootblock.c
+++ b/src/mainboard/emulation/qemu-q35/bootblock.c
@@ -10,12 +10,12 @@ static void bootblock_northbridge_init(void)
/*
* The "io" variant of the config access is explicitly used to
- * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to
+ * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to
* to true. That way all subsequent non-explicit config accesses use
* MCFG. This code also assumes that bootblock_northbridge_init() is
* the first thing called in the non-asm boot block code. The final
* assumption is that no assembly code is using the
- * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses.
+ * CONFIG_MMCONF_SUPPORT option to do PCI config acceses.
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under
* 4GiB.
diff --git a/src/mainboard/google/beltino/Kconfig b/src/mainboard/google/beltino/Kconfig
index 608523ee7e..c43001838a 100644
--- a/src/mainboard/google/beltino/Kconfig
+++ b/src/mainboard/google/beltino/Kconfig
@@ -9,7 +9,6 @@ config BOARD_GOOGLE_BASEBOARD_BELTINO
select HAVE_ACPI_TABLES
select HAVE_OPTION_TABLE
select HAVE_ACPI_RESUME
- select MMCONF_SUPPORT
select HAVE_SMI_HANDLER
select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_HAS_LPC_TPM