diff options
Diffstat (limited to 'src/mainboard')
30 files changed, 41 insertions, 11 deletions
diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index bc5d3126f2..0edc3466c9 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -39,6 +39,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c index 3e37e03f35..3d0eecf5e0 100644 --- a/src/mainboard/amd/inagua/romstage.c +++ b/src/mainboard/amd/inagua/romstage.c @@ -40,6 +40,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c index b1addb3db3..bb1ad30f7f 100644 --- a/src/mainboard/amd/olivehill/romstage.c +++ b/src/mainboard/amd/olivehill/romstage.c @@ -38,6 +38,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + /* Must come first to enable PCI MMCONF. */ + amd_initmmio(); + /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA * even though the register is not documented in the Kabini BKDG. @@ -46,8 +49,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) outb(0xD2, 0xcd6); outb(0x00, 0xcd7); - amd_initmmio(); - /* Set LPC decode enables. */ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5); diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index ae1c246c64..1f251ab379 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -38,6 +38,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); /* Set LPC decode enables. */ diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index 980ff3edbc..c8a8d74e75 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -46,6 +46,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c index 4b725c07ab..95f6dded7d 100644 --- a/src/mainboard/amd/south_station/romstage.c +++ b/src/mainboard/amd/south_station/romstage.c @@ -41,6 +41,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 4c9c8fa1b3..147f31acce 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -43,6 +43,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u8 byte; pci_devfn_t dev; + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); /* Set LPC decode enables. */ diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c index 74402bf124..d28608e16a 100644 --- a/src/mainboard/amd/torpedo/romstage.c +++ b/src/mainboard/amd/torpedo/romstage.c @@ -39,9 +39,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - post_code(0x35); + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); + post_code(0x35); + if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); gpioEarlyInit(); diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c index cdc564082d..7a5d348a2c 100644 --- a/src/mainboard/amd/union_station/romstage.c +++ b/src/mainboard/amd/union_station/romstage.c @@ -39,6 +39,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index 7a849e4739..82fbecfdb0 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -43,6 +43,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c index 7070e69f8e..29d831dc03 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/romstage.c @@ -51,6 +51,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) //outb(0xD2, 0xcd6); //outb(0x00, 0xcd7); + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); /* Set LPC decode enables. */ diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 83f6778f49..b5aff9f46b 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -64,6 +64,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u8 byte; pci_devfn_t dev; + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); #if IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE) diff --git a/src/mainboard/bap/ode_e20XX/romstage.c b/src/mainboard/bap/ode_e20XX/romstage.c index c109265b0d..a43d035fb4 100644 --- a/src/mainboard/bap/ode_e20XX/romstage.c +++ b/src/mainboard/bap/ode_e20XX/romstage.c @@ -43,6 +43,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); /* Set LPC decode enables. */ diff --git a/src/mainboard/biostar/am1ml/romstage.c b/src/mainboard/biostar/am1ml/romstage.c index d7da2bb783..e0afa759d8 100644 --- a/src/mainboard/biostar/am1ml/romstage.c +++ b/src/mainboard/biostar/am1ml/romstage.c @@ -113,6 +113,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) pci_devfn_t dev; u32 *addr32; + /* Must come first to enable PCI MMCONF. */ + amd_initmmio(); + /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA * even though the register is not documented in the Kabini BKDG. @@ -121,7 +124,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) outb(0xD2, 0xcd6); outb(0x00, 0xcd7); - amd_initmmio(); /* Set LPC decode enables. */ pci_devfn_t dev2 = PCI_DEV(0, 0x14, 3); pci_write_config32(dev2, 0x44, 0xff03ffd5); diff --git a/src/mainboard/elmex/pcm205400/romstage.c b/src/mainboard/elmex/pcm205400/romstage.c index 980ff3edbc..c8a8d74e75 100644 --- a/src/mainboard/elmex/pcm205400/romstage.c +++ b/src/mainboard/elmex/pcm205400/romstage.c @@ -46,6 +46,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c index 1335a8fe6a..6d06621584 100644 --- a/src/mainboard/gizmosphere/gizmo/romstage.c +++ b/src/mainboard/gizmosphere/gizmo/romstage.c @@ -41,6 +41,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/gizmosphere/gizmo2/romstage.c b/src/mainboard/gizmosphere/gizmo2/romstage.c index b1addb3db3..bb1ad30f7f 100644 --- a/src/mainboard/gizmosphere/gizmo2/romstage.c +++ b/src/mainboard/gizmosphere/gizmo2/romstage.c @@ -38,6 +38,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + /* Must come first to enable PCI MMCONF. */ + amd_initmmio(); + /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA * even though the register is not documented in the Kabini BKDG. @@ -46,8 +49,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) outb(0xD2, 0xcd6); outb(0x00, 0xcd7); - amd_initmmio(); - /* Set LPC decode enables. */ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5); diff --git a/src/mainboard/hp/abm/romstage.c b/src/mainboard/hp/abm/romstage.c index 6e77c57477..02ebbc96ae 100644 --- a/src/mainboard/hp/abm/romstage.c +++ b/src/mainboard/hp/abm/romstage.c @@ -44,6 +44,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 *addr32; + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); /* Set LPC decode enables. */ diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c index e5f15b5423..714743b924 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c @@ -34,6 +34,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); hudson_lpc_port80(); diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index 5f22aaadbd..85a4343ae7 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -62,6 +62,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/lenovo/g505s/romstage.c b/src/mainboard/lenovo/g505s/romstage.c index e5f15b5423..714743b924 100644 --- a/src/mainboard/lenovo/g505s/romstage.c +++ b/src/mainboard/lenovo/g505s/romstage.c @@ -34,6 +34,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); hudson_lpc_port80(); diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c index ccb6b39bea..37dc37f69f 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/romstage.c @@ -45,6 +45,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index b2590fc216..adc2987e3d 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -46,6 +46,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/msi/ms7721/romstage.c b/src/mainboard/msi/ms7721/romstage.c index f8565adec6..4aeb1ec17b 100644 --- a/src/mainboard/msi/ms7721/romstage.c +++ b/src/mainboard/msi/ms7721/romstage.c @@ -128,6 +128,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u8 byte; pci_devfn_t dev; + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); #if IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE) diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c index f8e6318773..a74d2479a8 100644 --- a/src/mainboard/pcengines/apu1/romstage.c +++ b/src/mainboard/pcengines/apu1/romstage.c @@ -51,6 +51,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/supermicro/h8qgi/Kconfig b/src/mainboard/supermicro/h8qgi/Kconfig index b259e3b45d..5492d47418 100644 --- a/src/mainboard/supermicro/h8qgi/Kconfig +++ b/src/mainboard/supermicro/h8qgi/Kconfig @@ -30,7 +30,6 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_2048 - #select MMCONF_SUPPORT_DEFAULT #TODO enable it to resolve Multicore IO conflict config MAINBOARD_DIR string diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c index bab438e6d4..19ffbdfe4f 100644 --- a/src/mainboard/supermicro/h8qgi/romstage.c +++ b/src/mainboard/supermicro/h8qgi/romstage.c @@ -40,8 +40,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - post_code(0x30); + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); + post_code(0x31); /* Halt if there was a built in self test failure */ diff --git a/src/mainboard/supermicro/h8scm/romstage.c b/src/mainboard/supermicro/h8scm/romstage.c index fecb91a691..918d9ad7e7 100644 --- a/src/mainboard/supermicro/h8scm/romstage.c +++ b/src/mainboard/supermicro/h8scm/romstage.c @@ -39,8 +39,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - post_code(0x30); + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); + post_code(0x31); /* Halt if there was a built in self test failure */ diff --git a/src/mainboard/tyan/s8226/Kconfig b/src/mainboard/tyan/s8226/Kconfig index 733f1c44e3..46107580c2 100644 --- a/src/mainboard/tyan/s8226/Kconfig +++ b/src/mainboard/tyan/s8226/Kconfig @@ -30,7 +30,6 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 - #select MMCONF_SUPPORT_DEFAULT #TODO enable it to resolve Multicore IO conflict config MAINBOARD_DIR string diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c index 7460f208ce..d43c04b4cc 100644 --- a/src/mainboard/tyan/s8226/romstage.c +++ b/src/mainboard/tyan/s8226/romstage.c @@ -38,8 +38,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - post_code(0x30); + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); + post_code(0x31); /* For serial port. */ |