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-rw-r--r--src/mainboard/amd/dbm690t/dsdt.asl13
-rw-r--r--src/mainboard/amd/pistachio/dsdt.asl13
-rw-r--r--src/mainboard/kontron/kt690/dsdt.asl13
-rw-r--r--src/mainboard/siemens/sitemp_g1p1/dsdt.asl10
-rw-r--r--src/mainboard/technexion/tim5690/dsdt.asl13
-rw-r--r--src/mainboard/technexion/tim8690/dsdt.asl13
6 files changed, 34 insertions, 41 deletions
diff --git a/src/mainboard/amd/dbm690t/dsdt.asl b/src/mainboard/amd/dbm690t/dsdt.asl
index 46d3671576..744c687e35 100644
--- a/src/mainboard/amd/dbm690t/dsdt.asl
+++ b/src/mainboard/amd/dbm690t/dsdt.asl
@@ -13,6 +13,8 @@
* GNU General Public License for more details.
*/
+#include <southbridge/amd/sb600/sb600.h>
+
/* DefinitionBlock Statement */
DefinitionBlock (
"DSDT.AML", /* Output filename */
@@ -33,7 +35,6 @@ DefinitionBlock (
Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
- Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
@@ -1361,20 +1362,18 @@ DefinitionBlock (
})
} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
- Device(HPTM) {
+ Device(HPTM) { /* HPET */
Name(_HID,EISAID("PNP0103"))
Name(CRS,ResourceTemplate() {
- Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
+ Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x00000400, HPT) /* 1kb reserved space */
})
Method(_STA, 0) {
- Return(0x0F) /* sata is visible */
+ Return(0x0F) /* HPET is visible */
}
Method(_CRS, 0) {
- CreateDwordField(CRS, ^HPT._BAS, HPBA)
- Store(HPBA, HPBA)
Return(CRS)
}
- } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+ } /* End Device(_SB.PCI0.LpcIsaBr.HPTM) */
} /* end LIBR */
Device(HPBR) {
diff --git a/src/mainboard/amd/pistachio/dsdt.asl b/src/mainboard/amd/pistachio/dsdt.asl
index 6322289c07..0e8bd05789 100644
--- a/src/mainboard/amd/pistachio/dsdt.asl
+++ b/src/mainboard/amd/pistachio/dsdt.asl
@@ -13,6 +13,8 @@
* GNU General Public License for more details.
*/
+#include <southbridge/amd/sb600/sb600.h>
+
/* DefinitionBlock Statement */
DefinitionBlock (
"DSDT.AML", /* Output filename */
@@ -33,7 +35,6 @@ DefinitionBlock (
Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
- Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
@@ -1360,20 +1361,18 @@ DefinitionBlock (
})
} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
- Device(HPTM) {
+ Device(HPTM) { /* HPET */
Name(_HID,EISAID("PNP0103"))
Name(CRS,ResourceTemplate() {
- Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
+ Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x00000400, HPT) /* 1kb reserved space */
})
Method(_STA, 0) {
- Return(0x0F) /* sata is visible */
+ Return(0x0F) /* HPET is visible */
}
Method(_CRS, 0) {
- CreateDwordField(CRS, ^HPT._BAS, HPBA)
- Store(HPBA, HPBA)
Return(CRS)
}
- } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+ } /* End Device(_SB.PCI0.LpcIsaBr.HPTM) */
} /* end LIBR */
Device(HPBR) {
diff --git a/src/mainboard/kontron/kt690/dsdt.asl b/src/mainboard/kontron/kt690/dsdt.asl
index 5884e74a55..05b6855da1 100644
--- a/src/mainboard/kontron/kt690/dsdt.asl
+++ b/src/mainboard/kontron/kt690/dsdt.asl
@@ -13,6 +13,8 @@
* GNU General Public License for more details.
*/
+#include <southbridge/amd/sb600/sb600.h>
+
/* DefinitionBlock Statement */
DefinitionBlock (
"dsdt.aml", /* Output filename */
@@ -33,7 +35,6 @@ DefinitionBlock (
Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
- Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
@@ -1362,20 +1363,18 @@ DefinitionBlock (
})
} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
- Device(HPTM) {
+ Device(HPTM) { /* HPET */
Name(_HID,EISAID("PNP0103"))
Name(CRS,ResourceTemplate() {
- Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
+ Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x00000400, HPT) /* 1kb reserved space */
})
Method(_STA, 0) {
- Return(0x0F) /* sata is visible */
+ Return(0x0F) /* HPET is visible */
}
Method(_CRS, 0) {
- CreateDwordField(CRS, ^HPT._BAS, HPBA)
- Store(HPBA, HPBA)
Return(CRS)
}
- } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+ } /* End Device(_SB.PCI0.LpcIsaBr.HPTM) */
} /* end LIBR */
Device(HPBR) {
diff --git a/src/mainboard/siemens/sitemp_g1p1/dsdt.asl b/src/mainboard/siemens/sitemp_g1p1/dsdt.asl
index 699bb93891..3d85966630 100644
--- a/src/mainboard/siemens/sitemp_g1p1/dsdt.asl
+++ b/src/mainboard/siemens/sitemp_g1p1/dsdt.asl
@@ -16,13 +16,13 @@
*/
#include <arch/ioapic.h>
#include <cpu/x86/lapic_def.h>
+#include <southbridge/amd/sb600/sb600.h>
DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005)
{
/* Data to be patched by the BIOS during POST */
/* Memory related values */
Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
- Name(HPBA, 0xFED00000) /* Base address of HPET table */
/* USB overcurrent mapping pins. */
Name(UOM0, 0)
@@ -1004,17 +1004,15 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005)
})
} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
- Device(HPET) {
+ Device(HPET) { /* HPET */
Name(_HID,EISAID("PNP0103"))
Name(CRS,ResourceTemplate() {
- Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
+ Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x00000400, HPT) /* 1kb reserved space */
})
Method(_STA, 0) {
- Return(0x0F) /* sata is visible */
+ Return(0x0F) /* HPET is visible */
}
Method(_CRS, 0) {
- CreateDwordField(CRS, ^HPT._BAS, HPBA)
- Store(HPBA, HPBA)
Return(CRS)
}
}
diff --git a/src/mainboard/technexion/tim5690/dsdt.asl b/src/mainboard/technexion/tim5690/dsdt.asl
index a763bcfe0e..14d0bfa8a7 100644
--- a/src/mainboard/technexion/tim5690/dsdt.asl
+++ b/src/mainboard/technexion/tim5690/dsdt.asl
@@ -13,6 +13,8 @@
* GNU General Public License for more details.
*/
+#include <southbridge/amd/sb600/sb600.h>
+
/* DefinitionBlock Statement */
DefinitionBlock (
"DSDT.AML", /* Output filename */
@@ -33,7 +35,6 @@ DefinitionBlock (
Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
- Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
@@ -1361,20 +1362,18 @@ DefinitionBlock (
})
} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
- Device(HPTM) {
+ Device(HPTM) { /* HPET */
Name(_HID,EISAID("PNP0103"))
Name(CRS,ResourceTemplate() {
- Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
+ Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x00000400, HPT) /* 1kb reserved space */
})
Method(_STA, 0) {
- Return(0x0F) /* sata is visible */
+ Return(0x0F) /* HPET is visible */
}
Method(_CRS, 0) {
- CreateDwordField(CRS, ^HPT._BAS, HPBA)
- Store(HPBA, HPBA)
Return(CRS)
}
- } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+ } /* End Device(_SB.PCI0.LpcIsaBr.HPTM) */
} /* end LIBR */
Device(HPBR) {
diff --git a/src/mainboard/technexion/tim8690/dsdt.asl b/src/mainboard/technexion/tim8690/dsdt.asl
index 692c02b72d..e831750052 100644
--- a/src/mainboard/technexion/tim8690/dsdt.asl
+++ b/src/mainboard/technexion/tim8690/dsdt.asl
@@ -13,6 +13,8 @@
* GNU General Public License for more details.
*/
+#include <southbridge/amd/sb600/sb600.h>
+
/* DefinitionBlock Statement */
DefinitionBlock (
"DSDT.AML", /* Output filename */
@@ -33,7 +35,6 @@ DefinitionBlock (
Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
- Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
@@ -1361,20 +1362,18 @@ DefinitionBlock (
})
} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
- Device(HPTM) {
+ Device(HPTM) { /* HPET */
Name(_HID,EISAID("PNP0103"))
Name(CRS,ResourceTemplate() {
- Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
+ Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x00000400, HPT) /* 1kb reserved space */
})
Method(_STA, 0) {
- Return(0x0F) /* sata is visible */
+ Return(0x0F) /* HPET is visible */
}
Method(_CRS, 0) {
- CreateDwordField(CRS, ^HPT._BAS, HPBA)
- Store(HPBA, HPBA)
Return(CRS)
}
- } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+ } /* End Device(_SB.PCI0.LpcIsaBr.HPTM) */
} /* end LIBR */
Device(HPBR) {
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-26 05:47:16 +0000