diff options
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/snow/Kconfig | 117 | ||||
| -rw-r--r-- | src/mainboard/google/snow/Makefile.inc | 3 | ||||
| -rw-r--r-- | src/mainboard/google/snow/bootblock.c | 49 | ||||
| -rw-r--r-- | src/mainboard/google/snow/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/google/snow/exynos5250.h | 33 | ||||
| -rw-r--r-- | src/mainboard/google/snow/mainboard.c | 50 | ||||
| -rw-r--r-- | src/mainboard/google/snow/mainboard.h | 33 | ||||
| -rw-r--r-- | src/mainboard/google/snow/memory.c | 38 | ||||
| -rw-r--r-- | src/mainboard/google/snow/romstage.c | 52 | ||||
| -rw-r--r-- | src/mainboard/google/snow/wakeup.c | 31 |
10 files changed, 107 insertions, 301 deletions
diff --git a/src/mainboard/google/snow/Kconfig b/src/mainboard/google/snow/Kconfig index 4072b0fb6f..12b11807c3 100644 --- a/src/mainboard/google/snow/Kconfig +++ b/src/mainboard/google/snow/Kconfig @@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select EC_GOOGLE_CHROMEEC_I2C select BOARD_ROMSIZE_KB_4096 select DRIVER_MAXIM_MAX77686 -# select HAVE_ACPI_TABLES select EXYNOS_DISPLAYPORT select CHROMEOS select DRIVER_TI_TPS65090 @@ -41,132 +40,18 @@ config MAINBOARD_DIR config MAINBOARD_PART_NUMBER string - default "SNOW" - -#config MMCONF_BASE_ADDRESS -# hex -# default 0xf0000000 - -#config IRQ_SLOT_COUNT -# int -# default 18 + default "Snow" config MAX_CPUS int default 2 -config MAINBOARD_VENDOR - string - default "Samsung" - -config BOOTBLOCK_MAINBOARD_INIT - string - default "mainboard/google/snow/bootblock.c" - config DRAM_SIZE_MB int default 2048 -config NR_DRAM_BANKS - int - default 1 - -choice CONSOLE_SERIAL_UART_CHOICES - prompt "Serial Console UART" - default CONSOLE_SERIAL_UART3 - depends on CONSOLE_SERIAL_UART - -config CONSOLE_SERIAL_UART0 - bool "UART0" - help - Serial console on UART0 - -config CONSOLE_SERIAL_UART1 - bool "UART1" - help - Serial console on UART1 - -config CONSOLE_SERIAL_UART2 - bool "UART2" - help - Serial console on UART2 - -config CONSOLE_SERIAL_UART3 - bool "UART3" - help - Serial console on UART3 - -endchoice - -config CONSOLE_SERIAL_UART_ADDRESS - hex - depends on CONSOLE_SERIAL_UART - default 0x12c00000 if CONSOLE_SERIAL_UART0 - default 0x12c10000 if CONSOLE_SERIAL_UART1 - default 0x12c20000 if CONSOLE_SERIAL_UART2 - default 0x12c30000 if CONSOLE_SERIAL_UART3 - help - Map the UART names to the respective MMIO address. - config EC_GOOGLE_CHROMEEC_I2C_BUS hex default 4 -################################################################# -# stuff from smdk5250.h # -# FIXME: can we move some of these to exynos5250's Kconfig? # -################################################################# -config SYS_I2C_SPEED - int - default 100000 - -config SYS_I2C_SLAVE - hex - default 0x0 - -config I2C_MULTI_BUS - bool - default y - -#config HARD_I2C -# bool -# default y -#CMD_I2C -#I2C_EDID -#DRIVER_S3C24X0_I2C - -config VDD_ARM_MV - int - default 1300 #1.3V - -config VDD_INT_UV - int - default 1012500 # 1.0125v - -config VDD_MIF_MV - int - default 1000 # 1.0v - -config VDD_G3D_MV - int - default 1200 # 1.2v - -config VDD_LDO2_MV - int - default 1500 # 1.5v - -config VDD_LDO3_MV - int - default 1800 # 1.8v - -config VDD_LDO5_MV - int - default 1800 # 1.8v - -config VDD_LDO10_MV - int - default 1800 # 1.8v - -######### smdk5250.h ######## - endif # BOARD_GOOGLE_SNOW diff --git a/src/mainboard/google/snow/Makefile.inc b/src/mainboard/google/snow/Makefile.inc index 69bc9ba97b..96496628c9 100644 --- a/src/mainboard/google/snow/Makefile.inc +++ b/src/mainboard/google/snow/Makefile.inc @@ -1,7 +1,7 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. +## Copyright (C) 2012 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -23,6 +23,5 @@ romstage-y += memory.c romstage-y += romstage.c romstage-y += wakeup.c -# ramstage-y += ec.c ramstage-y += mainboard.c ramstage-y += chromeos.c diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c deleted file mode 100644 index 56c2650f7a..0000000000 --- a/src/mainboard/google/snow/bootblock.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <types.h> -#include <arch/io.h> -#include <cbfs.h> -#include <uart.h> -#include <console/console.h> -#include <cpu/samsung/exynos5250/clk.h> -#include <cpu/samsung/exynos5250/periph.h> -#include <cpu/samsung/exynos5250/pinmux.h> -#include "mainboard.h" - -void bootblock_mainboard_init(void); -void bootblock_mainboard_init(void) -{ - /* kick off the multi-core timer. - * We want to do this as early as we can. - */ - mct_start(); - - if (snow_get_wakeup_state() == SNOW_WAKEUP_DIRECT) { - snow_wakeup(); - /* Never returns. */ - } - - /* For most ARM systems, we have to initialize firmware media source - * (ex, SPI, SD/MMC, or eMMC) now; but for Exynos platform, that is - * already handled by iROM so there's no need to setup again. - */ - - console_init(); -} diff --git a/src/mainboard/google/snow/devicetree.cb b/src/mainboard/google/snow/devicetree.cb index 41ed45e4dd..deebbf4cd2 100644 --- a/src/mainboard/google/snow/devicetree.cb +++ b/src/mainboard/google/snow/devicetree.cb @@ -1,7 +1,7 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. +## Copyright (C) 2012 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/snow/exynos5250.h b/src/mainboard/google/snow/exynos5250.h new file mode 100644 index 0000000000..998d9ee32e --- /dev/null +++ b/src/mainboard/google/snow/exynos5250.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* I2C */ +#define I2C_0_SPEED 100000 +#define I2C_SLAVE 0 + +/* Voltages */ +#define VDD_ARM_MV 1300 // 1.3V +#define VDD_INT_UV 1012500 // 1.0125V +#define VDD_MIF_MV 1000 // 1.0V +#define VDD_G3D_MV 1200 // 1.2V +#define VDD_LDO2_MV 1500 // 1.5V +#define VDD_LDO3_MV 1800 // 1.8V +#define VDD_LDO5_MV 1800 // 1.8V +#define VDD_LDO10_MV 1800 // 1.8V + diff --git a/src/mainboard/google/snow/mainboard.c b/src/mainboard/google/snow/mainboard.c index f4c8e6cf13..197735e7d3 100644 --- a/src/mainboard/google/snow/mainboard.c +++ b/src/mainboard/google/snow/mainboard.c @@ -1,10 +1,11 @@ /* - * Copyright (C) 2012 Google Inc. + * This file is part of the coreboot project. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -13,8 +14,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <console/console.h> @@ -38,13 +38,14 @@ #include <cpu/samsung/exynos5-common/i2c.h> #include <cpu/samsung/exynos5-common/s5p-dp-core.h> +#include "exynos5250.h" /* convenient shorthand (in MB) */ #define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20) #define DRAM_SIZE CONFIG_DRAM_SIZE_MB #define DRAM_END (DRAM_START + DRAM_SIZE) /* plus one... */ -static struct edid snow_edid = { +static struct edid edid = { .ha = 1366, .va = 768, .bpp = 16, @@ -114,14 +115,14 @@ static void exynos_dp_reset(void) #define LCD_T5_DELAY_MS 10 #define LCD_T6_DELAY_MS 10 -static void snow_backlight_pwm(void) +static void backlight_pwm(void) { /*Configure backlight PWM as a simple output high (100% brightness) */ gpio_direction_output(GPIO_B20, 1); udelay(LCD_T6_DELAY_MS * 1000); } -static void snow_backlight_en(void) +static void backlight_en(void) { /* * Configure GPIO for LCD_BL_EN */ gpio_direction_output(GPIO_X30, 1); @@ -132,13 +133,13 @@ static void snow_backlight_en(void) #define FET1_CTRL 0x0f #define FET6_CTRL 0x14 -static void snow_lcd_vdd(void) +static void lcd_vdd(void) { /* Enable FET6, lcd panel */ tps65090_fet_enable(TPS69050_BUS, FET6_CTRL); } -static void snow_backlight_vdd(void) +static void backlight_vdd(void) { /* Enable FET1, backlight */ tps65090_fet_enable(TPS69050_BUS, FET1_CTRL); @@ -146,7 +147,7 @@ static void snow_backlight_vdd(void) } //static struct video_info smdk5250_dp_config = { -static struct video_info snow_dp_video_info = { +static struct video_info dp_video_info = { /* FIXME: fix video_info struct to use const for name */ .name = (char *)"eDP-LVDS NXP PTN3460", @@ -165,7 +166,7 @@ static struct video_info snow_dp_video_info = { /* FIXME: move some place more appropriate */ #define EXYNOS5250_DP1_BASE 0x145b0000 -#define SNOW_MAX_DP_TRIES 5 +#define MAX_DP_TRIES 5 /* * This function disables the USB3.0 PLL to save power @@ -183,12 +184,12 @@ static void mainboard_init(device_t dev) int dp_tries; struct s5p_dp_device dp_device = { .base = (struct exynos5_dp *)EXYNOS5250_DP1_BASE, - .video_info = &snow_dp_video_info, + .video_info = &dp_video_info, }; void *fb_addr; - i2c_init(TPS69050_BUS, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - i2c_init(7, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + i2c_init(TPS69050_BUS, I2C_0_SPEED, I2C_SLAVE); + i2c_init(7, I2C_0_SPEED, I2C_SLAVE); tmu_init(&exynos5250_tmu_info); @@ -199,15 +200,15 @@ static void mainboard_init(device_t dev) disable_usb30_pll(); fb_addr = cbmem_find(CBMEM_ID_CONSOLE); - set_vbe_mode_info_valid(&snow_edid, (uintptr_t)(fb_addr) + 64*KiB); + set_vbe_mode_info_valid(&edid, (uintptr_t)(fb_addr) + 64*KiB); - snow_lcd_vdd(); + lcd_vdd(); do { udelay(50); } while (!exynos_dp_hotplug()); exynos_dp_bridge_setup(); - for (dp_tries = 1; dp_tries <= SNOW_MAX_DP_TRIES; dp_tries++) { + for (dp_tries = 1; dp_tries <= MAX_DP_TRIES; dp_tries++) { exynos_dp_bridge_init(); if (exynos_dp_hotplug()) { exynos_dp_reset(); @@ -219,14 +220,14 @@ static void mainboard_init(device_t dev) udelay(LCD_T3_DELAY_MS * 1000); - snow_backlight_vdd(); - snow_backlight_pwm(); - snow_backlight_en(); + backlight_vdd(); + backlight_pwm(); + backlight_en(); /* if we're here, we're successful */ break; } - if (dp_tries > SNOW_MAX_DP_TRIES) + if (dp_tries > MAX_DP_TRIES) printk(BIOS_ERR, "%s: Failed to set up displayport\n", __func__); } @@ -235,6 +236,7 @@ static void mainboard_enable(device_t dev) dev->ops->init = &mainboard_init; /* set up coreboot tables */ + /* FIXME: this should happen somewhere else */ high_tables_size = CONFIG_COREBOOT_TABLES_SIZE; high_tables_base = CONFIG_SYS_SDRAM_BASE + ((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) - diff --git a/src/mainboard/google/snow/mainboard.h b/src/mainboard/google/snow/mainboard.h deleted file mode 100644 index a91bed49da..0000000000 --- a/src/mainboard/google/snow/mainboard.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef MAINBOARD_H -#define MAINBOARD_H -enum { - SNOW_IS_NOT_WAKEUP, // A normal boot (not suspend/resume). - SNOW_WAKEUP_DIRECT, // A wake up event that can be resumed any time. - SNOW_WAKEUP_NEED_CLOCK_RESET, // A wake up event that must be resumed - // only after clock and memory - // controllers are re-initialized. -}; - -int snow_get_wakeup_state(void); -void snow_wakeup(void); - -#endif /* MAINBOARD_H */ diff --git a/src/mainboard/google/snow/memory.c b/src/mainboard/google/snow/memory.c index 0f72e69ff8..fc5a7bde73 100644 --- a/src/mainboard/google/snow/memory.c +++ b/src/mainboard/google/snow/memory.c @@ -1,9 +1,8 @@ /* - * This file is part of the coreboot project. It is based off code - * from Das U-Boot. + * This file is part of the coreboot project. * * Copyright (C) 2012 Samsung Electronics - * Copyright (C) 2013 The ChromiumOS Authors. + * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -30,8 +29,6 @@ #include <cpu/samsung/exynos5250/dmc.h> #include <cpu/samsung/exynos5250/clock_init.h> -#include "mainboard.h" - const struct mem_timings mem_timings[] = { { .mem_manuf = MEM_MANUF_ELPIDA, @@ -453,10 +450,10 @@ const struct mem_timings mem_timings[] = { } }; -#define SNOW_BOARD_ID0_GPIO 88 /* GPD0, pin 0 */ -#define SNOW_BOARD_ID1_GPIO 89 /* GPD0, pin 1 */ +#define BOARD_ID0_GPIO 88 /* GPD0, pin 0 */ +#define BOARD_ID1_GPIO 89 /* GPD0, pin 1 */ -enum snow_board_config { +enum board_config { SNOW_CONFIG_UNKNOWN = -1, SNOW_CONFIG_SAMSUNG_EVT, SNOW_CONFIG_ELPIDA_EVT, @@ -471,8 +468,8 @@ enum snow_board_config { struct { enum mvl3 id0, id1; - enum snow_board_config config; -} snow_id_map[] = { + enum board_config config; +} id_map[] = { /* ID0 ID1 config */ { LOGIC_0, LOGIC_0, SNOW_CONFIG_SAMSUNG_MP }, { LOGIC_0, LOGIC_1, SNOW_CONFIG_ELPIDA_MP }, @@ -489,17 +486,17 @@ static int board_get_config(void) { int i; int id0, id1; - enum snow_board_config config = SNOW_CONFIG_UNKNOWN; + enum board_config config = SNOW_CONFIG_UNKNOWN; - id0 = gpio_read_mvl3(SNOW_BOARD_ID0_GPIO); - id1 = gpio_read_mvl3(SNOW_BOARD_ID1_GPIO); + id0 = gpio_read_mvl3(BOARD_ID0_GPIO); + id1 = gpio_read_mvl3(BOARD_ID1_GPIO); if (id0 < 0 || id1 < 0) return -1; printk(BIOS_DEBUG, "%s: id0: %u, id1: %u\n", __func__, id0, id1); - for (i = 0; i < ARRAY_SIZE(snow_id_map); i++) { - if (id0 == snow_id_map[i].id0 && id1 == snow_id_map[i].id1) { - config = snow_id_map[i].config; + for (i = 0; i < ARRAY_SIZE(id_map); i++) { + if (id0 == id_map[i].id0 && id1 == id_map[i].id1) { + config = id_map[i].config; break; } } @@ -507,18 +504,17 @@ static int board_get_config(void) return config; } - struct mem_timings *get_mem_timings(void) { int i; - enum snow_board_config board_config; + enum board_config config; enum ddr_mode mem_type; unsigned int frequency_mhz; enum mem_manuf mem_manuf; const struct mem_timings *mem; - board_config = board_get_config(); - switch (board_config) { + config = board_get_config(); + switch (config) { case SNOW_CONFIG_ELPIDA_EVT: case SNOW_CONFIG_ELPIDA_DVT: case SNOW_CONFIG_ELPIDA_PVT: @@ -536,7 +532,7 @@ struct mem_timings *get_mem_timings(void) frequency_mhz = 800; break; default: - printk(BIOS_CRIT, "Unable to determine board config\n"); + printk(BIOS_CRIT, "Unknown board configuration.\n"); return NULL; } diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 508dac6590..3894f5a743 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -34,25 +34,26 @@ #include <cpu/samsung/exynos5250/periph.h> #include <cpu/samsung/exynos5250/power.h> #include <cpu/samsung/exynos5250/clock_init.h> +#include <cpu/samsung/exynos5250/wakeup.h> #include <console/console.h> #include <arch/stages.h> #include <drivers/maxim/max77686/max77686.h> #include <device/i2c.h> -#include "mainboard.h" +#include "exynos5250.h" #define PMIC_BUS 0 #define MMC0_GPIO_PIN (58) -static void snow_setup_power(void) +static void setup_power(void) { int error = 0; power_init(); /* Initialize I2C bus to configure PMIC. */ - i2c_init(0, CONFIG_SYS_I2C_SPEED, 0x00); + i2c_init(0, I2C_0_SPEED, 0x00); printk(BIOS_DEBUG, "%s: Setting up PMIC...\n", __func__); /* @@ -67,21 +68,21 @@ static void snow_setup_power(void) */ error = max77686_disable_backup_batt(PMIC_BUS); - error |= max77686_volsetting(PMIC_BUS, PMIC_BUCK2, CONFIG_VDD_ARM_MV, + error |= max77686_volsetting(PMIC_BUS, PMIC_BUCK2, VDD_ARM_MV, REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_BUS, PMIC_BUCK3, CONFIG_VDD_INT_UV, + error |= max77686_volsetting(PMIC_BUS, PMIC_BUCK3, VDD_INT_UV, REG_ENABLE, MAX77686_UV); - error |= max77686_volsetting(PMIC_BUS, PMIC_BUCK1, CONFIG_VDD_MIF_MV, + error |= max77686_volsetting(PMIC_BUS, PMIC_BUCK1, VDD_MIF_MV, REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_BUS, PMIC_BUCK4, CONFIG_VDD_G3D_MV, + error |= max77686_volsetting(PMIC_BUS, PMIC_BUCK4, VDD_G3D_MV, REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_BUS, PMIC_LDO2, CONFIG_VDD_LDO2_MV, + error |= max77686_volsetting(PMIC_BUS, PMIC_LDO2, VDD_LDO2_MV, REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_BUS, PMIC_LDO3, CONFIG_VDD_LDO3_MV, + error |= max77686_volsetting(PMIC_BUS, PMIC_LDO3, VDD_LDO3_MV, REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_BUS, PMIC_LDO5, CONFIG_VDD_LDO5_MV, + error |= max77686_volsetting(PMIC_BUS, PMIC_LDO5, VDD_LDO5_MV, REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_BUS, PMIC_LDO10, CONFIG_VDD_LDO10_MV, + error |= max77686_volsetting(PMIC_BUS, PMIC_LDO10, VDD_LDO10_MV, REG_ENABLE, MAX77686_MV); error |= max77686_enable_32khz_cp(PMIC_BUS); @@ -92,7 +93,7 @@ static void snow_setup_power(void) } } -static void snow_setup_storage(void) +static void setup_storage(void) { /* MMC0: Fixed, 8 bit mode, connected with GPIO. */ if (clock_set_mshci(PERIPH_ID_SDMMC0)) @@ -109,12 +110,12 @@ static void snow_setup_storage(void) exynos_pinmux_config(PERIPH_ID_SDMMC2, 0); } -static void snow_setup_graphics(void) +static void setup_graphics(void) { exynos_pinmux_config(PERIPH_ID_DPHPD, 0); } -static void snow_setup_gpio(void) +static void setup_gpio(void) { struct exynos5_gpio_part1 *gpio_pt1; struct exynos5_gpio_part2 *gpio_pt2; @@ -142,7 +143,7 @@ static void snow_setup_gpio(void) s5p_gpio_set_pull(&gpio_pt2->x1, POWER_GPIO, EXYNOS_GPIO_PULL_NONE); } -static void snow_setup_memory(struct mem_timings *mem, int is_resume) +static void setup_memory(struct mem_timings *mem, int is_resume) { printk(BIOS_SPEW, "man: 0x%x type: 0x%x, div: 0x%x, mhz: 0x%x\n", mem->mem_manuf, @@ -162,7 +163,7 @@ static void snow_setup_memory(struct mem_timings *mem, int is_resume) } } -static struct mem_timings *snow_setup_clock(void) +static struct mem_timings *setup_clock(void) { struct mem_timings *mem = get_mem_timings(); struct arm_clk_ratios *arm_ratios = get_arm_clk_ratios(); @@ -177,31 +178,30 @@ void main(void) { struct mem_timings *mem; void *entry; - int is_resume = (snow_get_wakeup_state() != SNOW_IS_NOT_WAKEUP); + int is_resume = (get_wakeup_state() != IS_NOT_WAKEUP); /* Clock must be initialized before console_init, otherwise you may need * to re-initialize serial console drivers again. */ - mem = snow_setup_clock(); + mem = setup_clock(); if (!is_resume) { console_init(); - snow_setup_power(); + setup_power(); } - snow_setup_memory(mem, is_resume); + setup_memory(mem, is_resume); if (is_resume) { - snow_wakeup(); + wakeup(); } - snow_setup_storage(); - snow_setup_gpio(); - snow_setup_graphics(); + setup_storage(); + setup_gpio(); + setup_graphics(); /* Set SPI (primary CBFS media) clock to 50MHz. */ clock_set_rate(PERIPH_ID_SPI1, 50000000); - entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); - printk(BIOS_INFO, "entry is 0x%p, leaving romstage.\n", entry); + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); stage_exit(entry); } diff --git a/src/mainboard/google/snow/wakeup.c b/src/mainboard/google/snow/wakeup.c index 8bb1724a2d..7a78721d02 100644 --- a/src/mainboard/google/snow/wakeup.c +++ b/src/mainboard/google/snow/wakeup.c @@ -24,39 +24,12 @@ #include <cpu/samsung/exynos5250/power.h> #include <cpu/samsung/exynos5-common/exynos5-common.h> -#include "mainboard.h" +#include <cpu/samsung/exynos5250/wakeup.h> -static int snow_wakeup_need_reset(void) +int wakeup_need_reset(void) { /* The "wake up" event is not reliable (known as "bad wakeup") and needs * reset if GPIO value is high. */ return gpio_get_value(GPIO_Y10); } -void snow_wakeup(void) -{ - if (snow_wakeup_need_reset()) - power_reset(); - - power_init(); /* Ensure ps_hold_setup() for early wakeup. */ - power_exit_wakeup(); - /* Should never return. */ - die("Failed to wake up.\n"); -} - -int snow_get_wakeup_state() -{ - uint32_t status = power_read_reset_status(); - - /* DIDLE/LPA can be resumed without clock reset (ex, bootblock), - * and SLEEP requires resetting clock (should be done in ROM stage). - */ - - if (status == S5P_CHECK_DIDLE || status == S5P_CHECK_LPA) - return SNOW_WAKEUP_DIRECT; - - if (status == S5P_CHECK_SLEEP) - return SNOW_WAKEUP_NEED_CLOCK_RESET; - - return SNOW_IS_NOT_WAKEUP; -} |