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-rw-r--r--src/mainboard/google/kahlee/variants/nuwani/devicetree.cb1
-rw-r--r--src/mainboard/google/kahlee/variants/nuwani/mainboard.c11
-rw-r--r--src/mainboard/google/kahlee/variants/treeya/devicetree.cb1
-rw-r--r--src/mainboard/google/kahlee/variants/treeya/mainboard.c11
4 files changed, 2 insertions, 22 deletions
diff --git a/src/mainboard/google/kahlee/variants/nuwani/devicetree.cb b/src/mainboard/google/kahlee/variants/nuwani/devicetree.cb
index 8c9f1cd47f..9d4ff0e6a4 100644
--- a/src/mainboard/google/kahlee/variants/nuwani/devicetree.cb
+++ b/src/mainboard/google/kahlee/variants/nuwani/devicetree.cb
@@ -62,6 +62,7 @@ chip soc/amd/stoneyridge
device pci 2.4 on
chip drivers/generic/bayhub
register "power_saving" = "1"
+ register "vih_tuning_value" = "0x35"
device pci 00.0 on end
end
end #
diff --git a/src/mainboard/google/kahlee/variants/nuwani/mainboard.c b/src/mainboard/google/kahlee/variants/nuwani/mainboard.c
index ce98d62c18..afb62ba5dd 100644
--- a/src/mainboard/google/kahlee/variants/nuwani/mainboard.c
+++ b/src/mainboard/google/kahlee/variants/nuwani/mainboard.c
@@ -77,17 +77,6 @@ void board_bh720(struct device *dev)
write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000001);
write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0);
write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x80000000);
-
- /* Tune VIH */
- pci_write_config32(dev, BH720_PROTECT,
- BH720_PROTECT_OFF | BH720_PROTECT_LOCK_OFF);
- bh720_pcr_data = pci_read_config32(dev, BH720_PCR_DrvStrength_PLL);
- bh720_pcr_data &= 0xFFFFFF00;
- /* CLK = 3 and DAT = 2 */
- bh720_pcr_data |= 0x35;
- pci_write_config32(dev, BH720_PCR_DrvStrength_PLL, bh720_pcr_data);
- pci_write_config32(dev, BH720_PROTECT,
- BH720_PROTECT_ON | BH720_PROTECT_LOCK_ON);
}
const char *smbios_mainboard_manufacturer(void)
diff --git a/src/mainboard/google/kahlee/variants/treeya/devicetree.cb b/src/mainboard/google/kahlee/variants/treeya/devicetree.cb
index 132172e750..183e3ddacd 100644
--- a/src/mainboard/google/kahlee/variants/treeya/devicetree.cb
+++ b/src/mainboard/google/kahlee/variants/treeya/devicetree.cb
@@ -62,6 +62,7 @@ chip soc/amd/stoneyridge
device pci 2.4 on
chip drivers/generic/bayhub
register "power_saving" = "1"
+ register "vih_tuning_value" = "0x35"
device pci 00.0 on end
end
end #
diff --git a/src/mainboard/google/kahlee/variants/treeya/mainboard.c b/src/mainboard/google/kahlee/variants/treeya/mainboard.c
index ce98d62c18..afb62ba5dd 100644
--- a/src/mainboard/google/kahlee/variants/treeya/mainboard.c
+++ b/src/mainboard/google/kahlee/variants/treeya/mainboard.c
@@ -77,17 +77,6 @@ void board_bh720(struct device *dev)
write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000001);
write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0);
write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x80000000);
-
- /* Tune VIH */
- pci_write_config32(dev, BH720_PROTECT,
- BH720_PROTECT_OFF | BH720_PROTECT_LOCK_OFF);
- bh720_pcr_data = pci_read_config32(dev, BH720_PCR_DrvStrength_PLL);
- bh720_pcr_data &= 0xFFFFFF00;
- /* CLK = 3 and DAT = 2 */
- bh720_pcr_data |= 0x35;
- pci_write_config32(dev, BH720_PCR_DrvStrength_PLL, bh720_pcr_data);
- pci_write_config32(dev, BH720_PROTECT,
- BH720_PROTECT_ON | BH720_PROTECT_LOCK_ON);
}
const char *smbios_mainboard_manufacturer(void)