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-rw-r--r--src/mainboard/google/guybrush/Kconfig3
-rw-r--r--src/mainboard/google/guybrush/port_descriptors.c4
2 files changed, 7 insertions, 0 deletions
diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig
index 5326616edb..0e7d15e755 100644
--- a/src/mainboard/google/guybrush/Kconfig
+++ b/src/mainboard/google/guybrush/Kconfig
@@ -32,6 +32,9 @@ config BOARD_SPECIFIC_OPTIONS
select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_HAS_I2C_TPM_CR50
select MAINBOARD_HAS_TPM2
+ select PCIEXP_ASPM
+ select PCIEXP_CLK_PM
+ select PCIEXP_COMMON_CLOCK
select PSP_DISABLE_POSTCODES
select SOC_AMD_CEZANNE
select SOC_AMD_COMMON_BLOCK_USE_ESPI
diff --git a/src/mainboard/google/guybrush/port_descriptors.c b/src/mainboard/google/guybrush/port_descriptors.c
index cc1fa1a7b2..540d3d19a7 100644
--- a/src/mainboard/google/guybrush/port_descriptors.c
+++ b/src/mainboard/google/guybrush/port_descriptors.c
@@ -13,6 +13,7 @@ static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = {
.end_logical_lane = 0,
.device_number = 2,
.function_number = 1,
+ .link_aspm = ASPM_L1,
.turn_off_unused_lanes = true,
.clk_req = CLK_REQ0,
.gpio_group_id = GPIO_29,
@@ -25,6 +26,7 @@ static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = {
.end_logical_lane = 1,
.device_number = 2,
.function_number = 2,
+ .link_aspm = ASPM_L1,
.turn_off_unused_lanes = true,
.clk_req = CLK_REQ1,
.gpio_group_id = GPIO_70,
@@ -37,6 +39,7 @@ static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = {
.end_logical_lane = 2,
.device_number = 2,
.function_number = 3,
+ .link_aspm = ASPM_L1,
.turn_off_unused_lanes = true,
.clk_req = CLK_REQ2,
.gpio_group_id = GPIO_18,
@@ -49,6 +52,7 @@ static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = {
.end_logical_lane = 7,
.device_number = 2,
.function_number = 4,
+ .link_aspm = ASPM_L1,
.turn_off_unused_lanes = true,
.clk_req = CLK_REQ3,
.gpio_group_id = GPIO_40,