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-rw-r--r--src/mainboard/system76/tgl-u/variants/darp7/ramstage.c3
-rw-r--r--src/mainboard/system76/tgl-u/variants/galp5/ramstage.c3
-rw-r--r--src/mainboard/system76/tgl-u/variants/lemp10/ramstage.c3
3 files changed, 9 insertions, 0 deletions
diff --git a/src/mainboard/system76/tgl-u/variants/darp7/ramstage.c b/src/mainboard/system76/tgl-u/variants/darp7/ramstage.c
index a60587d5d4..2b64f9f130 100644
--- a/src/mainboard/system76/tgl-u/variants/darp7/ramstage.c
+++ b/src/mainboard/system76/tgl-u/variants/darp7/ramstage.c
@@ -12,4 +12,7 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
// IOM config
params->PchUsbOverCurrentEnable = 0;
params->PortResetMessageEnable[5] = 1; // J_TYPEC2
+
+ // Enable reporting CPU C10 state over eSPI
+ params->PchEspiHostC10ReportEnable = 1;
}
diff --git a/src/mainboard/system76/tgl-u/variants/galp5/ramstage.c b/src/mainboard/system76/tgl-u/variants/galp5/ramstage.c
index a60587d5d4..2b64f9f130 100644
--- a/src/mainboard/system76/tgl-u/variants/galp5/ramstage.c
+++ b/src/mainboard/system76/tgl-u/variants/galp5/ramstage.c
@@ -12,4 +12,7 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
// IOM config
params->PchUsbOverCurrentEnable = 0;
params->PortResetMessageEnable[5] = 1; // J_TYPEC2
+
+ // Enable reporting CPU C10 state over eSPI
+ params->PchEspiHostC10ReportEnable = 1;
}
diff --git a/src/mainboard/system76/tgl-u/variants/lemp10/ramstage.c b/src/mainboard/system76/tgl-u/variants/lemp10/ramstage.c
index 2064836977..8b80740294 100644
--- a/src/mainboard/system76/tgl-u/variants/lemp10/ramstage.c
+++ b/src/mainboard/system76/tgl-u/variants/lemp10/ramstage.c
@@ -12,4 +12,7 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
// IOM config
params->PchUsbOverCurrentEnable = 0;
params->PortResetMessageEnable[2] = 1; // J_TYPEC1
+
+ // Enable reporting CPU C10 state over eSPI
+ params->PchEspiHostC10ReportEnable = 1;
}