diff options
Diffstat (limited to 'src/mainboard')
9 files changed, 5 insertions, 25 deletions
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 1fa7d2fa5f..5e5a5863dd 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -87,9 +87,6 @@ chip soc/intel/tigerlake register "pmc_gpe0_dw1" = "GPP_D" register "pmc_gpe0_dw2" = "GPP_E" - # Enable heci communication - register "HeciEnabled" = "1" - # FSP configuration register "SaGv" = "SaGv_Enabled" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index d01fdd6352..2c9a548ae0 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -8,9 +8,6 @@ chip soc/intel/tigerlake register "pmc_gpe0_dw1" = "GPP_C" register "pmc_gpe0_dw2" = "GPP_D" - # Enable heci1 communication - register "HeciEnabled" = "1" - # FSP configuration register "SaGv" = "SaGv_Enabled" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index c0adcc3f50..d19747a5c0 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -8,9 +8,6 @@ chip soc/intel/tigerlake register "pmc_gpe0_dw1" = "GPP_C" register "pmc_gpe0_dw2" = "GPP_D" - # Enable heci1 communication - register "HeciEnabled" = "1" - # FSP configuration register "SaGv" = "SaGv_Disabled" diff --git a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb index fb559d284e..66b8e86eb7 100644 --- a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb +++ b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb @@ -18,7 +18,6 @@ chip soc/intel/tigerlake register "CnviBtCore" = "true" register "CnviBtAudioOffload" = "1" register "enable_c6dram" = "1" - register "HeciEnabled" = "1" register "SaGv" = "SaGv_Enabled" register "TcssD3ColdDisable" = "1" diff --git a/src/mainboard/system76/darp7/devicetree.cb b/src/mainboard/system76/darp7/devicetree.cb index ae91bdd005..21f8141c5f 100644 --- a/src/mainboard/system76/darp7/devicetree.cb +++ b/src/mainboard/system76/darp7/devicetree.cb @@ -242,9 +242,7 @@ chip soc/intel/tigerlake # TODO: USB-PD? register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci" end - device ref heci1 on - register "HeciEnabled" = "1" - end + device ref heci1 on end device ref uart2 on # Debug console register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit" diff --git a/src/mainboard/system76/galp5/devicetree.cb b/src/mainboard/system76/galp5/devicetree.cb index 716afd4d0a..8bc74e34e1 100644 --- a/src/mainboard/system76/galp5/devicetree.cb +++ b/src/mainboard/system76/galp5/devicetree.cb @@ -253,9 +253,7 @@ chip soc/intel/tigerlake # TODO: Pantone ROM? register "SerialIoI2cMode[PchSerialIoIndexI2C2]" = "PchSerialIoPci" end - device ref heci1 on - register "HeciEnabled" = "1" - end + device ref heci1 on end device ref uart2 on # Debug console register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit" diff --git a/src/mainboard/system76/gaze16/devicetree.cb b/src/mainboard/system76/gaze16/devicetree.cb index 8b43202860..a92f044975 100644 --- a/src/mainboard/system76/gaze16/devicetree.cb +++ b/src/mainboard/system76/gaze16/devicetree.cb @@ -123,9 +123,7 @@ chip soc/intel/tigerlake device i2c 15 on end end end - device ref heci1 on - register "HeciEnabled" = "1" - end + device ref heci1 on end device ref uart2 on # Debug console register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit" diff --git a/src/mainboard/system76/lemp10/devicetree.cb b/src/mainboard/system76/lemp10/devicetree.cb index f097bacece..fc6c3b1774 100644 --- a/src/mainboard/system76/lemp10/devicetree.cb +++ b/src/mainboard/system76/lemp10/devicetree.cb @@ -223,9 +223,7 @@ chip soc/intel/tigerlake # TODO: USB-PD? register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci" end - device ref heci1 on - register "HeciEnabled" = "1" - end + device ref heci1 on end device ref uart2 on # Debug console register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit" diff --git a/src/mainboard/system76/oryp8/devicetree.cb b/src/mainboard/system76/oryp8/devicetree.cb index b85818d892..d3cf5de9c9 100644 --- a/src/mainboard/system76/oryp8/devicetree.cb +++ b/src/mainboard/system76/oryp8/devicetree.cb @@ -158,9 +158,7 @@ chip soc/intel/tigerlake device i2c 2c on end end end - device ref heci1 on - register "HeciEnabled" = "1" - end + device ref heci1 on end device ref uart2 on # Debug console register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit" |