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-rw-r--r--src/mainboard/google/rush/Kconfig2
-rw-r--r--src/mainboard/google/rush/Makefile.inc6
-rw-r--r--src/mainboard/google/rush/boardid.c38
-rw-r--r--src/mainboard/google/rush/boardid.h27
-rw-r--r--src/mainboard/google/rush/bootblock.c90
-rw-r--r--src/mainboard/google/rush/pmic.c116
-rw-r--r--src/mainboard/google/rush/pmic.h48
-rw-r--r--src/mainboard/google/rush/reset.c29
-rw-r--r--src/mainboard/google/rush/reset.h25
9 files changed, 381 insertions, 0 deletions
diff --git a/src/mainboard/google/rush/Kconfig b/src/mainboard/google/rush/Kconfig
index 9e36cacffd..5f7ae163d0 100644
--- a/src/mainboard/google/rush/Kconfig
+++ b/src/mainboard/google/rush/Kconfig
@@ -22,8 +22,10 @@ if BOARD_GOOGLE_RUSH
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select SOC_NVIDIA_TEGRA132
+ select MAINBOARD_HAS_BOOTBLOCK_INIT
select BOARD_ROMSIZE_KB_4096
+
config MAINBOARD_DIR
string
default google/rush
diff --git a/src/mainboard/google/rush/Makefile.inc b/src/mainboard/google/rush/Makefile.inc
index a0bd819442..4c6273f99f 100644
--- a/src/mainboard/google/rush/Makefile.inc
+++ b/src/mainboard/google/rush/Makefile.inc
@@ -27,6 +27,12 @@ $(obj)/generated/bct.cfg:
subdirs-y += bct
+bootblock-y += boardid.c
+bootblock-y += bootblock.c
+bootblock-y += pmic.c
+bootblock-y += reset.c
+
romstage-y += romstage.c
+romstage-y += reset.c
ramstage-y += mainboard.c \ No newline at end of file
diff --git a/src/mainboard/google/rush/boardid.c b/src/mainboard/google/rush/boardid.c
new file mode 100644
index 0000000000..76bd4d9a84
--- /dev/null
+++ b/src/mainboard/google/rush/boardid.c
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <soc/nvidia/tegra132/gpio.h>
+
+#include "boardid.h"
+
+uint8_t board_id(void)
+{
+ static int id = -1;
+
+ if (id < 0) {
+ id = gpio_get_in_value(GPIO(Q3)) << 0 |
+ gpio_get_in_value(GPIO(T1)) << 1 |
+ gpio_get_in_value(GPIO(X1)) << 2 |
+ gpio_get_in_value(GPIO(X4)) << 3;
+ printk(BIOS_SPEW, "Board ID: %#x.\n", id);
+ }
+
+ return id;
+}
diff --git a/src/mainboard/google/rush/boardid.h b/src/mainboard/google/rush/boardid.h
new file mode 100644
index 0000000000..aa2ea5f903
--- /dev/null
+++ b/src/mainboard/google/rush/boardid.h
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __MAINBOARD_GOOGLE_RUSH_BOARDID_H__
+#define __MAINBOARD_GOOGLE_RUSH_BOARDID_H__
+
+#include <stdint.h>
+
+uint8_t board_id(void);
+
+#endif /* __MAINBOARD_GOOGLE_RUSH_BOARDID_H__ */
diff --git a/src/mainboard/google/rush/bootblock.c b/src/mainboard/google/rush/bootblock.c
new file mode 100644
index 0000000000..51fe9b3e99
--- /dev/null
+++ b/src/mainboard/google/rush/bootblock.c
@@ -0,0 +1,90 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <bootblock_common.h>
+#include <console/console.h>
+#include <device/i2c.h>
+#include <soc/addressmap.h>
+#include <soc/clock.h>
+#include <soc/nvidia/tegra/i2c.h>
+#include <soc/nvidia/tegra132/clk_rst.h>
+#include <soc/nvidia/tegra132/gpio.h>
+#include <soc/nvidia/tegra132/pinmux.h>
+#include <soc/nvidia/tegra132/spi.h> /* FIXME: move back to soc code? */
+
+#include "pmic.h"
+
+static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
+
+static void set_clock_sources(void)
+{
+ /* UARTA gets PLLP, deactivate CLK_UART_DIV_OVERRIDE */
+ writel(PLLP << CLK_SOURCE_SHIFT, &clk_rst->clk_src_uarta);
+
+ clock_configure_source(mselect, PLLP, 102000);
+
+ /* The PMIC is on I2C5 and can run at 400 KHz. */
+ clock_configure_i2c_scl_freq(i2c5, PLLP, 400);
+
+ /* TODO: We should be able to set this to 50MHz, but that did not seem
+ * reliable. */
+ clock_configure_source(sbc4, PLLP, 33333);
+}
+
+void bootblock_mainboard_init(void)
+{
+ set_clock_sources();
+
+ clock_enable_clear_reset(CLK_L_CACHE2 | CLK_L_TMR,
+ CLK_H_I2C5 | CLK_H_APBDMA,
+ 0, CLK_V_MSELECT, 0, 0);
+
+ // Board ID GPIOs, bits 0-3.
+ gpio_input(GPIO(Q3));
+ gpio_input(GPIO(T1));
+ gpio_input(GPIO(X1));
+ gpio_input(GPIO(X4));
+
+ // I2C5 (PMU) clock.
+ pinmux_set_config(PINMUX_PWR_I2C_SCL_INDEX,
+ PINMUX_PWR_I2C_SCL_FUNC_I2CPMU | PINMUX_INPUT_ENABLE);
+ // I2C5 (PMU) data.
+ pinmux_set_config(PINMUX_PWR_I2C_SDA_INDEX,
+ PINMUX_PWR_I2C_SDA_FUNC_I2CPMU | PINMUX_INPUT_ENABLE);
+ i2c_init(4);
+ pmic_init(4);
+
+ /* SPI4 data out (MOSI) */
+ pinmux_set_config(PINMUX_GPIO_PG6_INDEX,
+ PINMUX_GPIO_PG6_FUNC_SPI4 | PINMUX_INPUT_ENABLE |
+ PINMUX_PULL_UP);
+ /* SPI4 data in (MISO) */
+ pinmux_set_config(PINMUX_GPIO_PG7_INDEX,
+ PINMUX_GPIO_PG7_FUNC_SPI4 | PINMUX_INPUT_ENABLE |
+ PINMUX_PULL_UP);
+ /* SPI4 clock */
+ pinmux_set_config(PINMUX_GPIO_PG5_INDEX,
+ PINMUX_GPIO_PG5_FUNC_SPI4 | PINMUX_INPUT_ENABLE);
+ /* SPI4 chip select 0 */
+ pinmux_set_config(PINMUX_GPIO_PI3_INDEX,
+ PINMUX_GPIO_PI3_FUNC_SPI4 | PINMUX_INPUT_ENABLE);
+
+ tegra_spi_init(4);
+}
diff --git a/src/mainboard/google/rush/pmic.c b/src/mainboard/google/rush/pmic.c
new file mode 100644
index 0000000000..c114066e8e
--- /dev/null
+++ b/src/mainboard/google/rush/pmic.c
@@ -0,0 +1,116 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <delay.h>
+#include <device/i2c.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+#include "boardid.h"
+#include "pmic.h"
+#include "reset.h"
+
+enum {
+ AS3722_I2C_ADDR = 0x40
+};
+
+struct as3722_init_reg {
+ u8 reg;
+ u8 val;
+ u8 delay;
+};
+
+static struct as3722_init_reg init_list[] = {
+ {AS3722_SDO0, 0x3C, 1},
+ {AS3722_SDO1, 0x32, 0},
+ {AS3722_LDO3, 0x59, 0},
+ {AS3722_SDO2, 0x3C, 0},
+ {AS3722_SDO3, 0x00, 0},
+ {AS3722_SDO4, 0x00, 0},
+ {AS3722_SDO5, 0x50, 0},
+ {AS3722_SDO6, 0x28, 1},
+ {AS3722_LDO0, 0x8A, 0},
+ {AS3722_LDO1, 0x00, 0},
+ {AS3722_LDO2, 0x10, 0},
+ {AS3722_LDO4, 0x00, 0},
+ {AS3722_LDO5, 0x00, 0},
+ {AS3722_LDO6, 0x00, 0},
+ {AS3722_LDO7, 0x00, 0},
+ {AS3722_LDO9, 0x00, 0},
+ {AS3722_LDO10, 0x00, 0},
+ {AS3722_LDO11, 0x00, 1},
+};
+
+static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int do_delay)
+{
+ if (i2c_writeb(bus, AS3722_I2C_ADDR, reg, val)) {
+ printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n",
+ __func__, reg, val);
+ /* Reset the SoC on any PMIC write error */
+ cpu_reset();
+ } else {
+ if (do_delay)
+ udelay(500);
+ }
+}
+
+static void pmic_slam_defaults(unsigned bus)
+{
+ int i;
+ for (i = 0; i < ARRAY_SIZE(init_list); i++) {
+ struct as3722_init_reg *reg = &init_list[i];
+ pmic_write_reg(bus, reg->reg, reg->val, reg->delay);
+ }
+}
+
+void pmic_init(unsigned bus)
+{
+ /*
+ * Don't need to set up VDD_CORE - already done - by OTP
+ * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
+ * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
+ */
+
+ /* Restore PMIC POR defaults, in case kernel changed 'em */
+ pmic_slam_defaults(bus);
+
+ /* First set VDD_CPU to 1.2V, then enable the VDD_CPU regulator. */
+ if (board_id() == 0)
+ pmic_write_reg(bus, 0x00, 0x3c, 1);
+ else
+ pmic_write_reg(bus, 0x00, 0x50, 1);
+
+ /* First set VDD_GPU to 1.0V, then enable the VDD_GPU regulator. */
+ pmic_write_reg(bus, 0x06, 0x28, 1);
+
+ /*
+ * First set +1.2V_GEN_AVDD to 1.2V, then enable the +1.2V_GEN_AVDD
+ * regulator.
+ */
+ pmic_write_reg(bus, 0x12, 0x10, 1);
+
+ /*
+ * Panel power GPIO O4. Set mode for GPIO4 (0x0c to 7), then set
+ * the value (register 0x20 bit 4)
+ */
+ pmic_write_reg(bus, 0x0c, 0x07, 0);
+ pmic_write_reg(bus, 0x20, 0x10, 1);
+}
diff --git a/src/mainboard/google/rush/pmic.h b/src/mainboard/google/rush/pmic.h
new file mode 100644
index 0000000000..b56c513416
--- /dev/null
+++ b/src/mainboard/google/rush/pmic.h
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __MAINBOARD_GOOGLE_RUSH_PMIC_H__
+#define __MAINBOARD_GOOGLE_RUSH_PMIC_H__
+
+enum {
+ AS3722_SDO0 = 0,
+ AS3722_SDO1,
+ AS3722_SDO2,
+ AS3722_SDO3,
+ AS3722_SDO4,
+ AS3722_SDO5,
+ AS3722_SDO6,
+
+ AS3722_LDO0 = 0x10,
+ AS3722_LDO1,
+ AS3722_LDO2,
+ AS3722_LDO3,
+ AS3722_LDO4,
+ AS3722_LDO5,
+ AS3722_LDO6,
+ AS3722_LDO7,
+
+ AS3722_LDO9 = 0x19,
+ AS3722_LDO10,
+ AS3722_LDO11,
+};
+
+void pmic_init(unsigned bus);
+
+#endif /* __MAINBOARD_GOOGLE_RUSH_PMIC_H__ */
diff --git a/src/mainboard/google/rush/reset.c b/src/mainboard/google/rush/reset.c
new file mode 100644
index 0000000000..381634078b
--- /dev/null
+++ b/src/mainboard/google/rush/reset.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <soc/nvidia/tegra132/gpio.h>
+
+#include "reset.h"
+
+void cpu_reset(void)
+{
+ gpio_output(GPIO(I5), 0);
+ while(1);
+}
diff --git a/src/mainboard/google/rush/reset.h b/src/mainboard/google/rush/reset.h
new file mode 100644
index 0000000000..be723ce316
--- /dev/null
+++ b/src/mainboard/google/rush/reset.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __MAINBOARD_GOOGLE_RUSH_BOOTBLOCK_H__
+#define __MAINBOARD_GOOGLE_RUSH_BOOTBLOCK_H__
+
+void cpu_reset(void);
+
+#endif /* __MAINBOARD_GOOGLE_RUSH_BOOTBLOCK_H__ */
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-28 01:54:35 +0000