diff options
Diffstat (limited to 'src/mainboard')
40 files changed, 256 insertions, 2047 deletions
diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c index 697319356f..7f5a2700e7 100644 --- a/src/mainboard/amd/dbm690t/romstage.c +++ b/src/mainboard/amd/dbm690t/romstage.c @@ -100,60 +100,10 @@ static inline int spd_read_byte(u32 device, u32 address) #include "cpu/amd/model_fxx/fidvid.c" -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "northbridge/amd/amdk8/early_ht.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - /* Is this a cpu only reset? Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal()) { /* RTC already inited */ - goto normal_image; - } else { - goto fallback_image; - } - } - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - enumerate_ht_chain(); - - /* sb600_lpc_port80(); */ - sb600_pci_port80(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } else { - goto fallback_image; - } -normal_image: - post_code(0x23); - __asm__ volatile ("jmp __normal_image": /* outputs */ - :"a" (bist), "b"(cpu_init_detectedx) /* inputs */); - -fallback_image: - post_code(0x25); -} -#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */ - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, }; int needs_reset = 0; u32 bsp_apicid = 0; @@ -161,6 +111,14 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) struct cpuid_result cpuid1; struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + enumerate_ht_chain(); + + /* sb600_lpc_port80(); */ + sb600_pci_port80(); + } if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); diff --git a/src/mainboard/amd/mahogany/cache_as_ram_auto.c b/src/mainboard/amd/mahogany/cache_as_ram_auto.c deleted file mode 100644 index 9538611e95..0000000000 --- a/src/mainboard/amd/mahogany/cache_as_ram_auto.c +++ /dev/null @@ -1,239 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#define ASSEMBLY 1 -#define __PRE_RAM__ - -#define RAMINIT_SYSINFO 1 -#define K8_SET_FIDVID 1 -#define QRANK_DIMM_SUPPORT 1 -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 -#endif - -#define RC0 (6<<8) -#define RC1 (7<<8) - -#define DIMM0 0x50 -#define DIMM1 0x51 - -#define ICS951462_ADDRESS 0x69 -#define SMBUS_HUB 0x71 - -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <arch/romcc_io.h> -#include <cpu/x86/lapic.h> -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "arch/i386/lib/console.c" - -#define post_code(x) outb(x, 0x80) - -#include <cpu/amd/model_fxx_rev.h> -#include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" -#include "lib/delay.c" - -#include "cpu/x86/lapic/boot_cpu.c" -#include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" -#include "superio/ite/it8718f/it8718f_early_serial.c" - -#include "cpu/amd/mtrr/amd_earlymtrr.c" -#include "cpu/x86/bist.h" - -#include "northbridge/amd/amdk8/setup_resource_map.c" - -#include "southbridge/amd/rs780/rs780_early_setup.c" -#include "southbridge/amd/sb700/sb700_early_setup.c" - -/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/ -static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} - -/* called in raminit_f.c */ -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ -} - -/*called in raminit_f.c */ -static inline int spd_read_byte(u32 device, u32 address) -{ - return smbus_read_byte(device, address); -} - -#include "northbridge/amd/amdk8/amdk8.h" -#include "northbridge/amd/amdk8/incoherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" -#include "northbridge/amd/amdk8/coherent_ht.c" -#include "lib/generic_sdram.c" -#include "resourcemap.c" - -#include "cpu/amd/dualcore/dualcore.c" - -#include "cpu/amd/car/copy_and_run.c" -#include "cpu/amd/car/post_cache_as_ram.c" - -#include "cpu/amd/model_fxx/init_cpus.c" - -#include "cpu/amd/model_fxx/fidvid.c" - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - -#include "northbridge/amd/amdk8/early_ht.c" - -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - /* Is this a cpu only reset? Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal()) { /* RTC already inited */ - goto normal_image; - } else { - goto fallback_image; - } - } - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - enumerate_ht_chain(); - - /* sb700_lpc_port80(); */ - sb700_pci_port80(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } else { - goto fallback_image; - } -normal_image: - post_code(0x23); - __asm__ volatile ("jmp __normal_image": /* outputs */ - :"a" (bist), "b"(cpu_init_detectedx) /* inputs */); - -fallback_image: - post_code(0x25); -} -#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */ - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, }; - int needs_reset = 0; - u32 bsp_apicid = 0; - msr_t msr; - struct cpuid_result cpuid1; - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - - if (bist == 0) { - bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - } - - enable_rs780_dev8(); - sb700_lpc_init(); - - it8718f_enable_serial(0, CONFIG_TTYS0_BASE); - uart_init(); - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - printk_debug("bsp_apicid=0x%x\n", bsp_apicid); - - setup_mahogany_resource_map(); - - setup_coherent_ht_domain(); - -#if CONFIG_LOGICAL_CPUS==1 - /* It is said that we should start core1 after all core0 launched */ - wait_all_core0_started(); - start_other_cores(); -#endif - wait_all_aps_started(bsp_apicid); - - ht_setup_chains_x(sysinfo); - - /* run _early_setup before soft-reset. */ - rs780_early_setup(); - sb700_early_setup(); - -/* Check to see if processor is capable of changing FIDVID */ - /* otherwise it will throw a GP# when reading FIDVID_STATUS */ - cpuid1 = cpuid(0x80000007); - if( (cpuid1.edx & 0x6) == 0x6 ) { - - /* Read FIDVID_STATUS */ - msr=rdmsr(0xc0010042); - printk_debug("begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); - - enable_fid_change(); - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - init_fidvid_bsp(bsp_apicid); - - /* show final fid and vid */ - msr=rdmsr(0xc0010042); - printk_debug("end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); - - } else { - printk_debug("Changing FIDVID not supported\n"); - } - - needs_reset = optimize_link_coherent_ht(); - needs_reset |= optimize_link_incoherent_ht(sysinfo); - rs780_htinit(); - printk_debug("needs_reset=0x%x\n", needs_reset); - - if (needs_reset) { - print_info("ht reset -\r\n"); - soft_reset(); - } - - allow_all_aps_stop(bsp_apicid); - - /* It's the time to set ctrl now; */ - printk_debug("sysinfo->nodes: %2x sysinfo->ctrl: %2x spd_addr: %2x\n", - sysinfo->nodes, sysinfo->ctrl, spd_addr); - fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); - sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); - - rs780_before_pci_init(); - sb700_before_pci_init(); - - post_cache_as_ram(); -} diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c index 8aaeb64152..a6d2435e99 100644 --- a/src/mainboard/amd/mahogany/romstage.c +++ b/src/mainboard/amd/mahogany/romstage.c @@ -100,60 +100,10 @@ static inline int spd_read_byte(u32 device, u32 address) #include "cpu/amd/model_fxx/fidvid.c" -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "northbridge/amd/amdk8/early_ht.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - /* Is this a cpu only reset? Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal()) { /* RTC already inited */ - goto normal_image; - } else { - goto fallback_image; - } - } - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - enumerate_ht_chain(); - - /* sb700_lpc_port80(); */ - sb700_pci_port80(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } else { - goto fallback_image; - } -normal_image: - post_code(0x23); - __asm__ volatile ("jmp __normal_image": /* outputs */ - :"a" (bist), "b"(cpu_init_detectedx) /* inputs */); - -fallback_image: - post_code(0x25); -} -#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */ - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, }; int needs_reset = 0; u32 bsp_apicid = 0; @@ -161,6 +111,15 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) struct cpuid_result cpuid1; struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + enumerate_ht_chain(); + + /* sb700_lpc_port80(); */ + sb700_pci_port80(); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c index d440f4d2f9..0db2f3413b 100644 --- a/src/mainboard/amd/pistachio/romstage.c +++ b/src/mainboard/amd/pistachio/romstage.c @@ -94,60 +94,10 @@ static inline int spd_read_byte(u32 device, u32 address) #include "cpu/amd/model_fxx/fidvid.c" -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "northbridge/amd/amdk8/early_ht.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - /* Is this a cpu only reset? Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal()) { /* RTC already inited */ - goto normal_image; - } else { - goto fallback_image; - } - } - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - enumerate_ht_chain(); - - sb600_lpc_port80(); - /* sb600_pci_port80(); */ - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } else { - goto fallback_image; - } - normal_image: - post_code(0x01); - __asm__ volatile ("jmp __normal_image": /* outputs */ - :"a" (bist), "b"(cpu_init_detectedx)); /* inputs */ - - fallback_image: - post_code(0x02); -} -#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */ - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, }; int needs_reset = 0; u32 bsp_apicid = 0; @@ -157,6 +107,15 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + enumerate_ht_chain(); + + sb600_lpc_port80(); + /* sb600_pci_port80(); */ + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } diff --git a/src/mainboard/arima/hdama/romstage.c b/src/mainboard/arima/hdama/romstage.c index 19c4c6bc3f..7a851d6b1b 100644 --- a/src/mainboard/arima/hdama/romstage.c +++ b/src/mainboard/arima/hdama/romstage.c @@ -95,66 +95,11 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) , "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const uint16_t spd_addr [] = { (0xa<<3)|0, (0xa<<3)|2, 0, 0, (0xa<<3)|1, (0xa<<3)|3, 0, 0, @@ -169,6 +114,15 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) struct mem_controller ctrl[8]; unsigned nodes; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + amd8111_enable_rom(); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx); } diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index b6c3c3f686..2161e43180 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -176,68 +176,8 @@ void sio_init(void) pnp_exit_ext_func_mode(GPIO_DEV); } -#if CONFIG_USE_FALLBACK_IMAGE == 1 - -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - /* unsigned last_boot_normal_x = last_boot_normal(); */ - /* FIXME */ - unsigned last_boot_normal_x = 1; - - sio_init(); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - uart_init(); - console_init(); - enable_rom_decode(); - - print_info("now booting... fallback\r\n"); - - /* Is this a CPU only reset? Or is this a secondary CPU? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) - goto normal_image; - else - goto fallback_image; - } - - /* Nothing special needs to be done to find bus 0. */ - /* Allow the HT devices to be found. */ - enumerate_ht_chain(); - - /* Is this a deliberate reset by the BIOS? */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary CPU, how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } else { - goto fallback_image; - } - -normal_image: - /* print_info("JMP normal image\r\n"); */ - - __asm__ __volatile__("jmp __normal_image": - :"a" (bist), "b" (cpu_init_detectedx)); - -fallback_image: - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const uint16_t spd_addr[] = { (0xa << 3) | 0, (0xa << 3) | 2, 0, 0, (0xa << 3) | 1, (0xa << 3) | 3, 0, 0, @@ -258,6 +198,21 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) console_init(); enable_rom_decode(); + print_info("now booting... fallback\r\n"); + + /* Is this a CPU only reset? Or is this a secondary CPU? */ + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0. */ + /* Allow the HT devices to be found. */ + enumerate_ht_chain(); + } + + sio_init(); + w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + uart_init(); + console_init(); + enable_rom_decode(); + print_info("now booting... real_main\r\n"); if (bist == 0) diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c index 6169841f69..74d7bdebe2 100644 --- a/src/mainboard/broadcom/blast/romstage.c +++ b/src/mainboard/broadcom/blast/romstage.c @@ -106,74 +106,10 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "northbridge/amd/amdk8/early_ht.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - - - /* Is this a cpu only reset? Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal()) { // RTC already inited - goto normal_image; - } else { - goto fallback_image; - } - } - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - bcm5785_enable_rom(); - - bcm5785_enable_lpc(); - - //enable RTC - pc87417_enable_dev(RTC_DEV); - - /* Is this a deliberate reset by the bios */ -// post_code(0x22); - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: -// post_code(0x23); - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: -// post_code(0x25); - ; -} -#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */ - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const uint16_t spd_addr[] = { RC0|DIMM0, RC0|DIMM2, 0, 0, RC0|DIMM1, RC0|DIMM3, 0, 0, @@ -189,6 +125,20 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) struct mem_controller ctrl[8]; unsigned nodes; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + bcm5785_enable_rom(); + + bcm5785_enable_lpc(); + + //enable RTC + pc87417_enable_dev(RTC_DEV); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx); } diff --git a/src/mainboard/dell/s1850/failover.c b/src/mainboard/dell/s1850/failover.c index 1e03b08af8..3cc2c3d487 100644 --- a/src/mainboard/dell/s1850/failover.c +++ b/src/mainboard/dell/s1850/failover.c @@ -15,35 +15,5 @@ static unsigned long main(unsigned long bist) { /* skip all this nonsense as we are not doing fallback yet */ - goto fallback_image; - /* Did just the cpu reset? */ - if (memory_initialized()) { - if (last_boot_normal()) { - goto normal_image; - } else { - goto cpu_reset; - } - } - - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: return bist; } diff --git a/src/mainboard/emulation/qemu-x86/failover.c b/src/mainboard/emulation/qemu-x86/failover.c index 6caba22698..c018d78f25 100644 --- a/src/mainboard/emulation/qemu-x86/failover.c +++ b/src/mainboard/emulation/qemu-x86/failover.c @@ -10,20 +10,5 @@ static void main(void) { -#if 0 - /* Is this a cpu reset? */ - if (cpu_init_detected()) { - if (last_boot_normal()) { - asm("jmp __normal_image"); - } else { - asm("jmp __cpu_reset"); - } - } - - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - asm("jmp __normal_image"); - } -#endif } diff --git a/src/mainboard/ibm/e325/romstage.c b/src/mainboard/ibm/e325/romstage.c index 6621bf1272..7f461ba784 100644 --- a/src/mainboard/ibm/e325/romstage.c +++ b/src/mainboard/ibm/e325/romstage.c @@ -93,67 +93,11 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) , "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const struct mem_controller cpu[] = { { .node_id = 0, @@ -179,6 +123,15 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) int needs_reset; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + amd8111_enable_rom(); + } + if (bist == 0) { init_cpus(cpu_init_detectedx); } diff --git a/src/mainboard/ibm/e326/romstage.c b/src/mainboard/ibm/e326/romstage.c index 0ec2c52f48..e3e10bb435 100644 --- a/src/mainboard/ibm/e326/romstage.c +++ b/src/mainboard/ibm/e326/romstage.c @@ -92,68 +92,11 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) , "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const struct mem_controller cpu[] = { { .node_id = 0, @@ -179,6 +122,15 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) int needs_reset; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + amd8111_enable_rom(); + } + if (bist == 0) { init_cpus(cpu_init_detectedx); } diff --git a/src/mainboard/intel/jarrell/failover.c b/src/mainboard/intel/jarrell/failover.c index ac78182199..f561611a89 100644 --- a/src/mainboard/intel/jarrell/failover.c +++ b/src/mainboard/intel/jarrell/failover.c @@ -14,34 +14,5 @@ static unsigned long main(unsigned long bist) { - /* Did just the cpu reset? */ - if (memory_initialized()) { - if (last_boot_normal()) { - goto normal_image; - } else { - goto cpu_reset; - } - } - - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: return bist; } diff --git a/src/mainboard/intel/xe7501devkit/failover.c b/src/mainboard/intel/xe7501devkit/failover.c index 9daf3b27d6..775acca28b 100644 --- a/src/mainboard/intel/xe7501devkit/failover.c +++ b/src/mainboard/intel/xe7501devkit/failover.c @@ -13,36 +13,5 @@ static unsigned long main(unsigned long bist) { - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else { - - check_cmos_failed(); - - if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); -#if 0 - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); -#endif - fallback_image: return bist; } diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c index 224f60365d..a2d20b9488 100644 --- a/src/mainboard/kontron/kt690/romstage.c +++ b/src/mainboard/kontron/kt690/romstage.c @@ -101,60 +101,10 @@ static inline int spd_read_byte(u32 device, u32 address) #include "cpu/amd/model_fxx/fidvid.c" -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "northbridge/amd/amdk8/early_ht.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - /* Is this a cpu only reset? Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal()) { /* RTC already inited */ - goto normal_image; - } else { - goto fallback_image; - } - } - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - enumerate_ht_chain(); - - /* sb600_lpc_port80(); */ - sb600_pci_port80(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } else { - goto fallback_image; - } -normal_image: - post_code(0x23); - __asm__ volatile ("jmp __normal_image": /* outputs */ - :"a" (bist), "b"(cpu_init_detectedx) /* inputs */); - -fallback_image: - post_code(0x25); -} -#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */ - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ device_t dev; static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, }; int needs_reset = 0; @@ -163,6 +113,14 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) struct cpuid_result cpuid1; struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + enumerate_ht_chain(); + + /* sb600_lpc_port80(); */ + sb600_pci_port80(); + } if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index 4903b3edd7..1696ac9e2c 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -153,73 +153,10 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/fidvid.c" -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "northbridge/amd/amdk8/early_ht.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - - /* Is this a cpu only reset? Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal()) { // RTC already inited - goto normal_image; - } else { - goto fallback_image; - } - } - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - bcm5785_enable_rom(); - - bcm5785_enable_lpc(); - - //enable RTC - pc87417_enable_dev(RTC_DEV); - - /* Is this a deliberate reset by the bios */ -// post_code(0x22); - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: -// post_code(0x23); - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: -// post_code(0x25); - ; - -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const uint16_t spd_addr[] = { //first node RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6, @@ -237,6 +174,20 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) int needs_reset; unsigned bsp_apicid = 0; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + bcm5785_enable_rom(); + + bcm5785_enable_lpc(); + + //enable RTC + pc87417_enable_dev(RTC_DEV); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index b552788a54..5e67feb4c0 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -133,8 +133,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -156,68 +154,12 @@ static void sio_setup(void) } -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - sio_setup(); - - /* Setup the mcp55 */ - mcp55_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b"(cpu_init_detectedx) /* inputs */ - ); - - fallback_image: - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -} //CPU 1 mem is on SMBUS_HUB channel 2, and CPU 2 mem is on channel 1. #define RC0 (2<<8) #define RC1 (1<<8) -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { RC0|(0xa<<3)|0, RC0|(0xa<<3)|2, RC0|(0xa<<3)|4, RC0|(0xa<<3)|6, @@ -233,6 +175,18 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); char *p ; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + sio_setup(); + + /* Setup the mcp55 */ + mcp55_enable_rom(); + } + if (bist == 0) { //init_cpus(cpu_init_detectedx); bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); diff --git a/src/mainboard/newisys/khepri/romstage.c b/src/mainboard/newisys/khepri/romstage.c index e4c52d0843..65c562a347 100644 --- a/src/mainboard/newisys/khepri/romstage.c +++ b/src/mainboard/newisys/khepri/romstage.c @@ -108,71 +108,11 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - /* Setup the amd8111 */ - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ -// post_code(0x22); - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: -// post_code(0x23); - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: -// post_code(0x25); - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const uint16_t spd_addr [] = { (0xa<<3)|0, (0xa<<3)|2, 0, 0, (0xa<<3)|1, (0xa<<3)|3, 0, 0, @@ -188,6 +128,16 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) struct mem_controller ctrl[8]; unsigned nodes; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + /* Setup the amd8111 */ + amd8111_enable_rom(); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx); } diff --git a/src/mainboard/olpc/btest/failover.c b/src/mainboard/olpc/btest/failover.c index 1b6c6da9b1..8f000489ec 100644 --- a/src/mainboard/olpc/btest/failover.c +++ b/src/mainboard/olpc/btest/failover.c @@ -9,27 +9,5 @@ static unsigned long main(unsigned long bist) { -#if 0 - /* This is the primary cpu how should I boot? */ - if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: -#endif return bist; } diff --git a/src/mainboard/olpc/rev_a/failover.c b/src/mainboard/olpc/rev_a/failover.c index 1b6c6da9b1..8f000489ec 100644 --- a/src/mainboard/olpc/rev_a/failover.c +++ b/src/mainboard/olpc/rev_a/failover.c @@ -9,27 +9,5 @@ static unsigned long main(unsigned long bist) { -#if 0 - /* This is the primary cpu how should I boot? */ - if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: -#endif return bist; } diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c index 9a3f948036..ef97cf4417 100644 --- a/src/mainboard/sunw/ultra40/romstage.c +++ b/src/mainboard/sunw/ultra40/romstage.c @@ -112,8 +112,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/nvidia/ck804/ck804_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -146,65 +144,8 @@ static void sio_setup(void) } -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - sio_setup(); - - /* Setup the ck804 */ - ck804_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const uint16_t spd_addr [] = { (0xa<<3)|0, (0xa<<3)|2, 0, 0, (0xa<<3)|1, (0xa<<3)|3, 0, 0, @@ -220,6 +161,18 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) struct mem_controller ctrl[8]; unsigned nodes; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + sio_setup(); + + /* Setup the ck804 */ + ck804_enable_rom(); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx); } diff --git a/src/mainboard/supermicro/x6dai_g/failover.c b/src/mainboard/supermicro/x6dai_g/failover.c index 94befc5270..c50fbcabcb 100644 --- a/src/mainboard/supermicro/x6dai_g/failover.c +++ b/src/mainboard/supermicro/x6dai_g/failover.c @@ -14,34 +14,5 @@ static unsigned long main(unsigned long bist) { - /* Did just the cpu reset? */ - if (memory_initialized()) { - if (last_boot_normal()) { - goto normal_image; - } else { - goto cpu_reset; - } - } - - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: return bist; } diff --git a/src/mainboard/supermicro/x6dhe_g/failover.c b/src/mainboard/supermicro/x6dhe_g/failover.c index ac78182199..f561611a89 100644 --- a/src/mainboard/supermicro/x6dhe_g/failover.c +++ b/src/mainboard/supermicro/x6dhe_g/failover.c @@ -14,34 +14,5 @@ static unsigned long main(unsigned long bist) { - /* Did just the cpu reset? */ - if (memory_initialized()) { - if (last_boot_normal()) { - goto normal_image; - } else { - goto cpu_reset; - } - } - - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: return bist; } diff --git a/src/mainboard/supermicro/x6dhe_g2/failover.c b/src/mainboard/supermicro/x6dhe_g2/failover.c index ac78182199..f561611a89 100644 --- a/src/mainboard/supermicro/x6dhe_g2/failover.c +++ b/src/mainboard/supermicro/x6dhe_g2/failover.c @@ -14,34 +14,5 @@ static unsigned long main(unsigned long bist) { - /* Did just the cpu reset? */ - if (memory_initialized()) { - if (last_boot_normal()) { - goto normal_image; - } else { - goto cpu_reset; - } - } - - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: return bist; } diff --git a/src/mainboard/supermicro/x6dhr_ig/failover.c b/src/mainboard/supermicro/x6dhr_ig/failover.c index ac78182199..f561611a89 100644 --- a/src/mainboard/supermicro/x6dhr_ig/failover.c +++ b/src/mainboard/supermicro/x6dhr_ig/failover.c @@ -14,34 +14,5 @@ static unsigned long main(unsigned long bist) { - /* Did just the cpu reset? */ - if (memory_initialized()) { - if (last_boot_normal()) { - goto normal_image; - } else { - goto cpu_reset; - } - } - - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: return bist; } diff --git a/src/mainboard/supermicro/x6dhr_ig2/failover.c b/src/mainboard/supermicro/x6dhr_ig2/failover.c index ac78182199..f561611a89 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/failover.c +++ b/src/mainboard/supermicro/x6dhr_ig2/failover.c @@ -14,34 +14,5 @@ static unsigned long main(unsigned long bist) { - /* Did just the cpu reset? */ - if (memory_initialized()) { - if (last_boot_normal()) { - goto normal_image; - } else { - goto cpu_reset; - } - } - - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: return bist; } diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c index 4919078424..7dccfe2047 100644 --- a/src/mainboard/technexion/tim5690/romstage.c +++ b/src/mainboard/technexion/tim5690/romstage.c @@ -103,61 +103,10 @@ static inline int spd_read_byte(u32 device, u32 address) #include "tn_post_code.c" #include "speaker.c" - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "northbridge/amd/amdk8/early_ht.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - /* Is this a cpu only reset? Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal()) { /* RTC already inited */ - goto normal_image; - } else { - goto fallback_image; - } - } - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - enumerate_ht_chain(); - - /* sb600_lpc_port80(); */ - sb600_pci_port80(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } else { - goto fallback_image; - } -normal_image: - post_code(0x23); - __asm__ volatile ("jmp __normal_image": /* outputs */ - :"a" (bist), "b"(cpu_init_detectedx) /* inputs */); - -fallback_image: - post_code(0x25); -} -#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */ - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, }; int needs_reset = 0; u32 bsp_apicid = 0; @@ -165,6 +114,15 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) struct cpuid_result cpuid1; struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + enumerate_ht_chain(); + + /* sb600_lpc_port80(); */ + sb600_pci_port80(); + } + technexion_post_code_init(); technexion_post_code(LED_MESSAGE_START); diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c index ff86ba3713..a101b1a495 100644 --- a/src/mainboard/technexion/tim8690/romstage.c +++ b/src/mainboard/technexion/tim8690/romstage.c @@ -100,60 +100,10 @@ static inline int spd_read_byte(u32 device, u32 address) #include "cpu/amd/model_fxx/fidvid.c" -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "northbridge/amd/amdk8/early_ht.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - /* Is this a cpu only reset? Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal()) { /* RTC already inited */ - goto normal_image; - } else { - goto fallback_image; - } - } - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - enumerate_ht_chain(); - - /* sb600_lpc_port80(); */ - sb600_pci_port80(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } else { - goto fallback_image; - } -normal_image: - post_code(0x23); - __asm__ volatile ("jmp __normal_image": /* outputs */ - :"a" (bist), "b"(cpu_init_detectedx) /* inputs */); - -fallback_image: - post_code(0x25); -} -#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */ - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, }; int needs_reset = 0; u32 bsp_apicid = 0; @@ -162,6 +112,15 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + enumerate_ht_chain(); + + /* sb600_lpc_port80(); */ + sb600_pci_port80(); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } diff --git a/src/mainboard/tyan/s2735/romstage.c b/src/mainboard/tyan/s2735/romstage.c index 5e2678a047..6bcb459236 100644 --- a/src/mainboard/tyan/s2735/romstage.c +++ b/src/mainboard/tyan/s2735/romstage.c @@ -80,54 +80,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/x86/car/copy_and_run.c" -#if CONFIG_USE_FALLBACK_IMAGE == 1 - -#include "southbridge/intel/i82801ex/cmos_failover.c" - -void real_main(unsigned long bist); - void amd64_main(unsigned long bist) { - /* Is this a deliberate reset by the bios */ -// post_code(0x22); - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else { - check_cmos_failed(); - if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - } - normal_image: -// post_code(0x23); - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - ); - cpu_reset: -// post_code(0x24); -#if 0 - //CPU reset will reset memtroller ??? - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - ); -#endif - - fallback_image: -// post_code(0x25); - real_main(bist); -} -void real_main(unsigned long bist) -#else -void amd64_main(unsigned long bist) -#endif -{ static const struct mem_controller memctrl[] = { { .d0 = PCI_DEV(0, 0, 0), diff --git a/src/mainboard/tyan/s2850/romstage.c b/src/mainboard/tyan/s2850/romstage.c index 352feadf70..d6b13b0b55 100644 --- a/src/mainboard/tyan/s2850/romstage.c +++ b/src/mainboard/tyan/s2850/romstage.c @@ -93,72 +93,11 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - /* Setup the amd8111 */ - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ -// post_code(0x22); - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: -// post_code(0x23); - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: -// post_code(0x25); - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const struct mem_controller cpu[] = { { .node_id = 0, @@ -173,6 +112,16 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) int needs_reset; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + /* Setup the amd8111 */ + amd8111_enable_rom(); + } + if (bist == 0) { init_cpus(cpu_init_detectedx); } diff --git a/src/mainboard/tyan/s2875/romstage.c b/src/mainboard/tyan/s2875/romstage.c index 50b12f1ff6..12f41e0ff4 100644 --- a/src/mainboard/tyan/s2875/romstage.c +++ b/src/mainboard/tyan/s2875/romstage.c @@ -84,69 +84,11 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx)/* inputs */ - ); - - fallback_image: - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const struct mem_controller cpu[] = { { .node_id = 0, @@ -172,6 +114,15 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) int needs_reset; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + amd8111_enable_rom(); + } + if (bist == 0) { init_cpus(cpu_init_detectedx); } diff --git a/src/mainboard/tyan/s2880/romstage.c b/src/mainboard/tyan/s2880/romstage.c index c97f3b7708..553910ae73 100644 --- a/src/mainboard/tyan/s2880/romstage.c +++ b/src/mainboard/tyan/s2880/romstage.c @@ -85,68 +85,11 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const struct mem_controller cpu[] = { { .node_id = 0, @@ -172,6 +115,15 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) int needs_reset; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + amd8111_enable_rom(); + } + if (bist == 0) { init_cpus(cpu_init_detectedx); } diff --git a/src/mainboard/tyan/s2881/romstage.c b/src/mainboard/tyan/s2881/romstage.c index 9d5edcb462..536f887112 100644 --- a/src/mainboard/tyan/s2881/romstage.c +++ b/src/mainboard/tyan/s2881/romstage.c @@ -98,72 +98,11 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - /* Setup the amd8111 */ - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ -// post_code(0x22); - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: -// post_code(0x23); - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: -// post_code(0x25); - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const uint16_t spd_addr [] = { (0xa<<3)|0, (0xa<<3)|2, 0, 0, (0xa<<3)|1, (0xa<<3)|3, 0, 0, @@ -179,6 +118,16 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) struct mem_controller ctrl[8]; unsigned nodes; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + /* Setup the amd8111 */ + amd8111_enable_rom(); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx); } diff --git a/src/mainboard/tyan/s2882/romstage.c b/src/mainboard/tyan/s2882/romstage.c index cdea6933ed..2fe7561deb 100644 --- a/src/mainboard/tyan/s2882/romstage.c +++ b/src/mainboard/tyan/s2882/romstage.c @@ -88,68 +88,11 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) , "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const struct mem_controller cpu[] = { { .node_id = 0, @@ -175,6 +118,15 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) int needs_reset; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + amd8111_enable_rom(); + } + if (bist == 0) { init_cpus(cpu_init_detectedx); } diff --git a/src/mainboard/tyan/s2885/romstage.c b/src/mainboard/tyan/s2885/romstage.c index d561e033c6..5b178f7e9f 100644 --- a/src/mainboard/tyan/s2885/romstage.c +++ b/src/mainboard/tyan/s2885/romstage.c @@ -98,72 +98,11 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - /* Setup the amd8111 */ - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ -// post_code(0x22); - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: -// post_code(0x23); - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: -// post_code(0x25); - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const uint16_t spd_addr [] = { (0xa<<3)|0, (0xa<<3)|2, 0, 0, (0xa<<3)|1, (0xa<<3)|3, 0, 0, @@ -179,6 +118,16 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) struct mem_controller ctrl[8]; unsigned nodes; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + /* Setup the amd8111 */ + amd8111_enable_rom(); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx); } diff --git a/src/mainboard/tyan/s2891/romstage.c b/src/mainboard/tyan/s2891/romstage.c index 9ace5e30ae..0505493dc1 100644 --- a/src/mainboard/tyan/s2891/romstage.c +++ b/src/mainboard/tyan/s2891/romstage.c @@ -77,8 +77,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/nvidia/ck804/ck804_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -112,68 +110,8 @@ static void sio_setup(void) } -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - sio_setup(); - - /* Setup the ck804 */ - ck804_enable_rom(); - - /* Is this a deliberate reset by the bios */ -// post_code(0x22); - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: -// post_code(0x23); - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b"(cpu_init_detectedx) /* inputs */ - ); - - fallback_image: -// post_code(0x25); - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const uint16_t spd_addr [] = { (0xa<<3)|0, (0xa<<3)|2, 0, 0, (0xa<<3)|1, (0xa<<3)|3, 0, 0, @@ -189,6 +127,18 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) struct mem_controller ctrl[8]; unsigned nodes; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + sio_setup(); + + /* Setup the ck804 */ + ck804_enable_rom(); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx); } diff --git a/src/mainboard/tyan/s2892/romstage.c b/src/mainboard/tyan/s2892/romstage.c index e94017e532..1a4766cbea 100644 --- a/src/mainboard/tyan/s2892/romstage.c +++ b/src/mainboard/tyan/s2892/romstage.c @@ -82,8 +82,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/nvidia/ck804/ck804_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -101,66 +99,8 @@ static void sio_setup(void) pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword); } -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - sio_setup(); - - /* Setup the ck804 */ - ck804_enable_rom(); - - /* Is this a deliberate reset by the bios */ -// post_code(0x22); - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: -// post_code(0x23); - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b"(cpu_init_detectedx) /* inputs */ - ); - - fallback_image: -// post_code(0x25); - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - #if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); - #endif - real_main(bist, cpu_init_detectedx); -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const uint16_t spd_addr [] = { (0xa<<3)|0, (0xa<<3)|2, 0, 0, (0xa<<3)|1, (0xa<<3)|3, 0, 0, @@ -176,6 +116,18 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) struct mem_controller ctrl[8]; unsigned nodes; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + sio_setup(); + + /* Setup the ck804 */ + ck804_enable_rom(); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx); } diff --git a/src/mainboard/tyan/s4880/romstage.c b/src/mainboard/tyan/s4880/romstage.c index 9f38ec1992..590de9f922 100644 --- a/src/mainboard/tyan/s4880/romstage.c +++ b/src/mainboard/tyan/s4880/romstage.c @@ -111,68 +111,11 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const struct mem_controller cpu[] = { { .node_id = 0, @@ -222,6 +165,15 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) int needs_reset; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + amd8111_enable_rom(); + } + if (bist == 0) { init_cpus(cpu_init_detectedx); } diff --git a/src/mainboard/tyan/s4882/romstage.c b/src/mainboard/tyan/s4882/romstage.c index 1c8d3b42fe..d1233b4d31 100644 --- a/src/mainboard/tyan/s4882/romstage.c +++ b/src/mainboard/tyan/s4882/romstage.c @@ -119,67 +119,11 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" ( cpu_init_detectedx ) /* inputs */ - ); - - fallback_image: - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const uint16_t spd_addr [] = { RC0|DIMM0, RC0|DIMM2, 0, 0, RC0|DIMM1, RC0|DIMM3, 0, 0, @@ -201,6 +145,15 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) struct mem_controller ctrl[8]; unsigned nodes; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + amd8111_enable_rom(); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx); } diff --git a/src/mainboard/via/epia-m/failover.c b/src/mainboard/via/epia-m/failover.c index 1b6c6da9b1..8f000489ec 100644 --- a/src/mainboard/via/epia-m/failover.c +++ b/src/mainboard/via/epia-m/failover.c @@ -9,27 +9,5 @@ static unsigned long main(unsigned long bist) { -#if 0 - /* This is the primary cpu how should I boot? */ - if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: -#endif return bist; } diff --git a/src/mainboard/via/epia-n/failover.c b/src/mainboard/via/epia-n/failover.c index 1b6c6da9b1..8f000489ec 100644 --- a/src/mainboard/via/epia-n/failover.c +++ b/src/mainboard/via/epia-n/failover.c @@ -9,27 +9,5 @@ static unsigned long main(unsigned long bist) { -#if 0 - /* This is the primary cpu how should I boot? */ - if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: -#endif return bist; } |