diff options
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/dmp/Kconfig | 31 | ||||
| -rw-r--r-- | src/mainboard/dmp/Kconfig.name | 2 | ||||
| -rw-r--r-- | src/mainboard/dmp/vortex86ex/Kconfig | 1352 | ||||
| -rw-r--r-- | src/mainboard/dmp/vortex86ex/Kconfig.name | 2 | ||||
| -rw-r--r-- | src/mainboard/dmp/vortex86ex/board_info.txt | 1 | ||||
| -rw-r--r-- | src/mainboard/dmp/vortex86ex/devicetree.cb | 28 | ||||
| -rw-r--r-- | src/mainboard/dmp/vortex86ex/hda_verb.c | 64 | ||||
| -rw-r--r-- | src/mainboard/dmp/vortex86ex/irq_tables.c | 53 | ||||
| -rw-r--r-- | src/mainboard/dmp/vortex86ex/romstage.c | 352 |
9 files changed, 0 insertions, 1885 deletions
diff --git a/src/mainboard/dmp/Kconfig b/src/mainboard/dmp/Kconfig deleted file mode 100644 index 055d88f533..0000000000 --- a/src/mainboard/dmp/Kconfig +++ /dev/null @@ -1,31 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013 DMP Electronics Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -if VENDOR_DMP - -choice - prompt "Mainboard model" - -source "src/mainboard/dmp/*/Kconfig.name" - -endchoice - -source "src/mainboard/dmp/*/Kconfig" - -config MAINBOARD_VENDOR - string - default "DMP" - -endif # VENDOR_DMP diff --git a/src/mainboard/dmp/Kconfig.name b/src/mainboard/dmp/Kconfig.name deleted file mode 100644 index ddce56a39f..0000000000 --- a/src/mainboard/dmp/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config VENDOR_DMP - bool "DMP" diff --git a/src/mainboard/dmp/vortex86ex/Kconfig b/src/mainboard/dmp/vortex86ex/Kconfig deleted file mode 100644 index 9c4c178f69..0000000000 --- a/src/mainboard/dmp/vortex86ex/Kconfig +++ /dev/null @@ -1,1352 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013 DMP Electronics Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -if BOARD_DMP_EX - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_DMP_VORTEX86EX - select SOC_DMP_VORTEX86EX - select HAVE_PIRQ_TABLE - select BOARD_ROMSIZE_KB_256 - select ROMCC - select HAVE_DEBUG_RAM_SETUP - -config MAINBOARD_DIR - string - default dmp/vortex86ex - -config MAINBOARD_PART_NUMBER - string - default "Vortex86EX" - -config IRQ_SLOT_COUNT - int - default 12 - -config ID_SECTION_OFFSET - # Vortex86 ROM fixed data areas used too big range, we need - # to move ID from default address to another place. - # 18K below top of ROM should be ok. - hex - default 0x4800 - -# SPI I/O base address control. -config I2C_BASE - hex - default 0xfb00 - -menu "On-Chip Device Power Down Control" - - config TEMP_POWERDOWN - bool "Temperature sensor power-down" - - config SATA_POWERDOWN - bool "SATA power-down" - - config ADC_POWERDOWN - bool "ADC power-down" - - config PCIE0_POWERDOWN - bool "PCIE0 power-down" - - config MAC_POWERDOWN - bool "MAC power-down" - - config USB1_POWERDOWN - bool "USB2.0 Host Controller 1 power-down" - - config IDE_POWERDOWN - bool "IDE power-down" - -endmenu - -menu "Watchdog Timer setting" - -config WDT1_INITIALIZE - bool "Initialize WDT1" - default n - -config WDT1_ENABLE - depends on WDT1_INITIALIZE - bool "Enable WDT1" - default n - -choice - depends on WDT1_INITIALIZE - prompt "WDT1 Signal Select" - default WDT1_SIGNAL_RESET - -config WDT1_SINGAL_NMI - bool "NMI" -config WDT1_SIGNAL_RESET - bool "Reset" -config WDT1_SIGNAL_SMI - bool "SMI" - -endchoice - -endmenu - -menu "IDE controller setting" - -choice - prompt "Operation Mode" - default IDE_NATIVE_MODE - -config IDE_NATIVE_MODE - bool "Native Mode" -config IDE_LEGACY_MODE - bool "Legacy Mode" - -endchoice - -config IDE1_ENABLE - bool "IDE Primary channel Enable" - default y - -config IDE2_ENABLE - bool "IDE Secondary channel Enable" - default y - -config IDE_STANDARD_COMPATIBLE - bool "Standard IDE Compatible" - default n - help - Built-in IDE controller PCI vendor/device ID is 17F3:1012, which - is not recognized by some OSes. - - This option can change IDE controller PCI vendor/device ID to - other value for software compatibility. - -config IDE_COMPATIBLE_SELECTION - depends on IDE_STANDARD_COMPATIBLE - hex "IDE Compatible Selection" - default 0x808624db - help - IDE controller PCI vendor/device ID value setting. - - Higher 16-bit is vendor ID, lower 16-bit is device ID. - -endmenu - -# GPIO setting : -menu "GPIO setting" - -# Begin of GPIO0 -config GPIO_P0_ENABLE - bool "GPIO port 0 Enable" - default n - -config GPIO_P0_DATA_ADDR - hex "GPIO port 0 data address" - depends on GPIO_P0_ENABLE - -config GPIO_P0_DIR_ADDR - hex "GPIO port 0 direction address" - depends on GPIO_P0_ENABLE - -config GPIO_P0_INIT_DIR - hex "GPIO port 0 initial direction" - default 0x00 - depends on GPIO_P0_ENABLE - -config GPIO_P0_INIT_DATA - hex "GPIO port 0 initial data" - depends on GPIO_P0_ENABLE -# end of GPIO0 - -# Begin of GPIO1 -config GPIO_P1_ENABLE - bool "GPIO port 1 Enable" - default n - -config GPIO_P1_DATA_ADDR - hex "GPIO port 1 data address" - depends on GPIO_P1_ENABLE - -config GPIO_P1_DIR_ADDR - hex "GPIO port 1 direction address" - depends on GPIO_P1_ENABLE - -config GPIO_P1_INIT_DIR - hex "GPIO port 1 initial direction" - default 0x00 - depends on GPIO_P1_ENABLE - -config GPIO_P1_INIT_DATA - hex "GPIO port 1 initial data" - depends on GPIO_P1_ENABLE -# end of GPIO1 - -# Begin of GPIO2 -config GPIO_P2_ENABLE - bool "GPIO port 2 Enable" - default n - -config GPIO_P2_DATA_ADDR - hex "GPIO port 2 data address" - depends on GPIO_P2_ENABLE - -config GPIO_P2_DIR_ADDR - hex "GPIO port 2 direction address" - depends on GPIO_P2_ENABLE - -config GPIO_P2_INIT_DIR - hex "GPIO port 2 initial direction" - default 0x00 - depends on GPIO_P2_ENABLE - -config GPIO_P2_INIT_DATA - hex "GPIO port 2 initial data" - depends on GPIO_P2_ENABLE -# end of GPIO2 - -# Begin of GPIO3 -config GPIO_P3_ENABLE - bool "GPIO port 3 Enable" - default n - -config GPIO_P3_DATA_ADDR - hex "GPIO port 3 data address" - depends on GPIO_P3_ENABLE - -config GPIO_P3_DIR_ADDR - hex "GPIO port 3 direction address" - depends on GPIO_P3_ENABLE - -config GPIO_P3_INIT_DIR - hex "GPIO port 3 initial direction" - default 0x00 - depends on GPIO_P3_ENABLE - -config GPIO_P3_INIT_DATA - hex "GPIO port 3 initial data" - depends on GPIO_P3_ENABLE -# end of GPIO3 - -# Begin of GPIO4 -config GPIO_P4_ENABLE - bool "GPIO port 4 Enable" - default n - -config GPIO_P4_DATA_ADDR - hex "GPIO port 4 data address" - depends on GPIO_P4_ENABLE - -config GPIO_P4_DIR_ADDR - hex "GPIO port 4 direction address" - depends on GPIO_P4_ENABLE - -config GPIO_P4_INIT_DIR - hex "GPIO port 4 initial direction" - default 0x00 - depends on GPIO_P4_ENABLE - -config GPIO_P4_INIT_DATA - hex "GPIO port 4 initial data" - depends on GPIO_P4_ENABLE -# end of GPIO4 - -# Begin of GPIO5 -config GPIO_P5_ENABLE - bool "GPIO port 5 Enable" - default n - -config GPIO_P5_DATA_ADDR - hex "GPIO port 5 data address" - depends on GPIO_P5_ENABLE - -config GPIO_P5_DIR_ADDR - hex "GPIO port 5 direction address" - depends on GPIO_P5_ENABLE - -config GPIO_P5_INIT_DIR - hex "GPIO port 5 initial direction" - default 0x00 - depends on GPIO_P5_ENABLE - -config GPIO_P5_INIT_DATA - hex "GPIO port 5 initial data" - depends on GPIO_P5_ENABLE -# end of GPIO5 - -# Begin of GPIO6 -config GPIO_P6_ENABLE - bool "GPIO port 6 Enable" - default n - -config GPIO_P6_DATA_ADDR - hex "GPIO port 6 data address" - depends on GPIO_P6_ENABLE - -config GPIO_P6_DIR_ADDR - hex "GPIO port 6 direction address" - depends on GPIO_P6_ENABLE - -config GPIO_P6_INIT_DIR - hex "GPIO port 6 initial direction" - default 0x00 - depends on GPIO_P6_ENABLE - -config GPIO_P6_INIT_DATA - hex "GPIO port 6 initial data" - depends on GPIO_P6_ENABLE -# end of GPIO6 - -# Begin of GPIO7 -config GPIO_P7_ENABLE - bool "GPIO port 7 Enable" - default n - -config GPIO_P7_DATA_ADDR - hex "GPIO port 7 data address" - depends on GPIO_P7_ENABLE - -config GPIO_P7_DIR_ADDR - hex "GPIO port 7 direction address" - depends on GPIO_P7_ENABLE - -config GPIO_P7_INIT_DIR - hex "GPIO port 7 initial direction" - default 0x00 - depends on GPIO_P7_ENABLE - -config GPIO_P7_INIT_DATA - hex "GPIO port 7 initial data" - depends on GPIO_P7_ENABLE -# end of GPIO7 - -# Begin of GPIO8 -config GPIO_P8_ENABLE - bool "GPIO port 8 Enable" - default n - -config GPIO_P8_DATA_ADDR - hex "GPIO port 8 data address" - depends on GPIO_P8_ENABLE - -config GPIO_P8_DIR_ADDR - hex "GPIO port 8 direction address" - depends on GPIO_P8_ENABLE - -config GPIO_P8_INIT_DIR - hex "GPIO port 8 initial direction" - default 0x00 - depends on GPIO_P8_ENABLE - -config GPIO_P8_INIT_DATA - hex "GPIO port 8 initial data" - depends on GPIO_P8_ENABLE -# end of GPIO8 - -# Begin of GPIO9 -config GPIO_P9_ENABLE - bool "GPIO port 9 Enable" - default n - -config GPIO_P9_DATA_ADDR - hex "GPIO port 9 data address" - depends on GPIO_P9_ENABLE - -config GPIO_P9_DIR_ADDR - hex "GPIO port 9 direction address" - depends on GPIO_P9_ENABLE - -config GPIO_P9_INIT_DIR - hex "GPIO port 9 initial direction" - default 0x00 - depends on GPIO_P9_ENABLE - -config GPIO_P9_INIT_DATA - hex "GPIO port 9 initial data" - depends on GPIO_P9_ENABLE -# end of GPIO9 - -endmenu - -# UART setting : -menu "UART setting" - -# Begin of UART1 -config UART1_ENABLE - bool "UART1 Enable" - default y - -choice - prompt "UART1 I/O port" - default UART1_IO_PORT_3F8 - depends on UART1_ENABLE - -config UART1_IO_PORT_3F8 - bool "0x3f8, COM1" -config UART1_IO_PORT_2F8 - bool "0x2f8, COM2" -config UART1_IO_PORT_3E8 - bool "0x3e8, COM3" -config UART1_IO_PORT_2E8 - bool "0x2e8, COM4" -config UART1_IO_PORT_OTHER - bool "Other" - -endchoice - -config UART1_IO_PORT_OTHER_INPUT - hex "UART1 I/O port" - depends on UART1_ENABLE && UART1_IO_PORT_OTHER - -config UART1_IO - hex - depends on UART1_ENABLE - default 0x3f8 if UART1_IO_PORT_3F8 - default 0x2f8 if UART1_IO_PORT_2F8 - default 0x3e8 if UART1_IO_PORT_3E8 - default 0x2e8 if UART1_IO_PORT_2E8 - default UART1_IO_PORT_OTHER_INPUT if UART1_IO_PORT_OTHER - -choice - prompt "UART1 IRQ" - default UART1_IRQ4 - depends on UART1_ENABLE - -config UART1_IRQ_DISABLE - bool "Disable" -config UART1_IRQ3 - bool "IRQ3, COM2" -config UART1_IRQ4 - bool "IRQ4, COM1" -config UART1_IRQ5 - bool "IRQ5" -config UART1_IRQ6 - bool "IRQ6" -config UART1_IRQ7 - bool "IRQ7" -config UART1_IRQ9 - bool "IRQ9" -config UART1_IRQ10 - bool "IRQ10, COM3" -config UART1_IRQ11 - bool "IRQ11, COM4" -config UART1_IRQ12 - bool "IRQ12" -config UART1_IRQ14 - bool "IRQ14" -config UART1_IRQ15 - bool "IRQ15" - -endchoice - -config UART1_IRQ - int - depends on UART1_ENABLE - default 0 if UART1_IRQ_DISABLE - default 3 if UART1_IRQ3 - default 4 if UART1_IRQ4 - default 5 if UART1_IRQ5 - default 6 if UART1_IRQ6 - default 7 if UART1_IRQ7 - default 9 if UART1_IRQ9 - default 10 if UART1_IRQ10 - default 11 if UART1_IRQ11 - default 12 if UART1_IRQ12 - default 14 if UART1_IRQ14 - default 15 if UART1_IRQ15 - -# end of UART1 - -# Begin of UART2 -config UART2_ENABLE - bool "UART2 Enable" - default y - -choice - prompt "UART2 I/O port" - default UART2_IO_PORT_2F8 - depends on UART2_ENABLE - -config UART2_IO_PORT_3F8 - bool "0x3f8, COM1" -config UART2_IO_PORT_2F8 - bool "0x2f8, COM2" -config UART2_IO_PORT_3E8 - bool "0x3e8, COM3" -config UART2_IO_PORT_2E8 - bool "0x2e8, COM4" -config UART2_IO_PORT_OTHER - bool "Other" - -endchoice - -config UART2_IO_PORT_OTHER_INPUT - hex "UART2 I/O port" - depends on UART2_ENABLE && UART2_IO_PORT_OTHER - -config UART2_IO - hex - depends on UART2_ENABLE - default 0x3f8 if UART2_IO_PORT_3F8 - default 0x2f8 if UART2_IO_PORT_2F8 - default 0x3e8 if UART2_IO_PORT_3E8 - default 0x2e8 if UART2_IO_PORT_2E8 - default UART2_IO_PORT_OTHER_INPUT if UART2_IO_PORT_OTHER - -choice - prompt "UART2 IRQ" - default UART2_IRQ3 - depends on UART2_ENABLE - -config UART2_IRQ_DISABLE - bool "Disable" -config UART2_IRQ3 - bool "IRQ3, COM2" -config UART2_IRQ4 - bool "IRQ4, COM1" -config UART2_IRQ5 - bool "IRQ5" -config UART2_IRQ6 - bool "IRQ6" -config UART2_IRQ7 - bool "IRQ7" -config UART2_IRQ9 - bool "IRQ9" -config UART2_IRQ10 - bool "IRQ10, COM3" -config UART2_IRQ11 - bool "IRQ11, COM4" -config UART2_IRQ12 - bool "IRQ12" -config UART2_IRQ14 - bool "IRQ14" -config UART2_IRQ15 - bool "IRQ15" - -endchoice - -config UART2_IRQ - int - depends on UART2_ENABLE - default 0 if UART2_IRQ_DISABLE - default 3 if UART2_IRQ3 - default 4 if UART2_IRQ4 - default 5 if UART2_IRQ5 - default 6 if UART2_IRQ6 - default 7 if UART2_IRQ7 - default 9 if UART2_IRQ9 - default 10 if UART2_IRQ10 - default 11 if UART2_IRQ11 - default 12 if UART2_IRQ12 - default 14 if UART2_IRQ14 - default 15 if UART2_IRQ15 - -# end of UART2 - -# Begin of UART3 -config UART3_ENABLE - bool "UART3 Enable" - default y - -choice - prompt "UART3 I/O port" - default UART3_IO_PORT_3E8 - depends on UART3_ENABLE - -config UART3_IO_PORT_3F8 - bool "0x3f8, COM1" -config UART3_IO_PORT_2F8 - bool "0x2f8, COM2" -config UART3_IO_PORT_3E8 - bool "0x3e8, COM3" -config UART3_IO_PORT_2E8 - bool "0x2e8, COM4" -config UART3_IO_PORT_OTHER - bool "Other" - -endchoice - -config UART3_IO_PORT_OTHER_INPUT - hex "UART3 I/O port" - depends on UART3_ENABLE && UART3_IO_PORT_OTHER - -config UART3_IO - hex - depends on UART3_ENABLE - default 0x3f8 if UART3_IO_PORT_3F8 - default 0x2f8 if UART3_IO_PORT_2F8 - default 0x3e8 if UART3_IO_PORT_3E8 - default 0x2e8 if UART3_IO_PORT_2E8 - default UART3_IO_PORT_OTHER_INPUT if UART3_IO_PORT_OTHER - -choice - prompt "UART3 IRQ" - default UART3_IRQ10 - depends on UART3_ENABLE - -config UART3_IRQ_DISABLE - bool "Disable" -config UART3_IRQ3 - bool "IRQ3, COM2" -config UART3_IRQ4 - bool "IRQ4, COM1" -config UART3_IRQ5 - bool "IRQ5" -config UART3_IRQ6 - bool "IRQ6" -config UART3_IRQ7 - bool "IRQ7" -config UART3_IRQ9 - bool "IRQ9" -config UART3_IRQ10 - bool "IRQ10, COM3" -config UART3_IRQ11 - bool "IRQ11, COM4" -config UART3_IRQ12 - bool "IRQ12" -config UART3_IRQ14 - bool "IRQ14" -config UART3_IRQ15 - bool "IRQ15" - -endchoice - -config UART3_IRQ - int - depends on UART3_ENABLE - default 0 if UART3_IRQ_DISABLE - default 3 if UART3_IRQ3 - default 4 if UART3_IRQ4 - default 5 if UART3_IRQ5 - default 6 if UART3_IRQ6 - default 7 if UART3_IRQ7 - default 9 if UART3_IRQ9 - default 10 if UART3_IRQ10 - default 11 if UART3_IRQ11 - default 12 if UART3_IRQ12 - default 14 if UART3_IRQ14 - default 15 if UART3_IRQ15 - -# end of UART3 - -# Begin of UART4 -config UART4_ENABLE - bool "UART4 Enable" - default y - -choice - prompt "UART4 I/O port" - default UART4_IO_PORT_2E8 - depends on UART4_ENABLE - -config UART4_IO_PORT_3F8 - bool "0x3f8, COM1" -config UART4_IO_PORT_2F8 - bool "0x2f8, COM2" -config UART4_IO_PORT_3E8 - bool "0x3e8, COM3" -config UART4_IO_PORT_2E8 - bool "0x2e8, COM4" -config UART4_IO_PORT_OTHER - bool "Other" - -endchoice - -config UART4_IO_PORT_OTHER_INPUT - hex "UART4 I/O port" - depends on UART4_ENABLE && UART4_IO_PORT_OTHER - -config UART4_IO - hex - depends on UART4_ENABLE - default 0x3f8 if UART4_IO_PORT_3F8 - default 0x2f8 if UART4_IO_PORT_2F8 - default 0x3e8 if UART4_IO_PORT_3E8 - default 0x2e8 if UART4_IO_PORT_2E8 - default UART4_IO_PORT_OTHER_INPUT if UART4_IO_PORT_OTHER - -choice - prompt "UART4 IRQ" - default UART4_IRQ11 - depends on UART4_ENABLE - -config UART4_IRQ_DISABLE - bool "Disable" -config UART4_IRQ3 - bool "IRQ3, COM2" -config UART4_IRQ4 - bool "IRQ4, COM1" -config UART4_IRQ5 - bool "IRQ5" -config UART4_IRQ6 - bool "IRQ6" -config UART4_IRQ7 - bool "IRQ7" -config UART4_IRQ9 - bool "IRQ9" -config UART4_IRQ10 - bool "IRQ10, COM3" -config UART4_IRQ11 - bool "IRQ11, COM4" -config UART4_IRQ12 - bool "IRQ12" -config UART4_IRQ14 - bool "IRQ14" -config UART4_IRQ15 - bool "IRQ15" - -endchoice - -config UART4_IRQ - int - depends on UART4_ENABLE - default 0 if UART4_IRQ_DISABLE - default 3 if UART4_IRQ3 - default 4 if UART4_IRQ4 - default 5 if UART4_IRQ5 - default 6 if UART4_IRQ6 - default 7 if UART4_IRQ7 - default 9 if UART4_IRQ9 - default 10 if UART4_IRQ10 - default 11 if UART4_IRQ11 - default 12 if UART4_IRQ12 - default 14 if UART4_IRQ14 - default 15 if UART4_IRQ15 - -# end of UART4 - -# Begin of UART5 -config UART5_ENABLE - bool "UART5 Enable" - default n - -choice - prompt "UART5 I/O port" - default UART5_IO_PORT_OTHER - depends on UART5_ENABLE - -config UART5_IO_PORT_3F8 - bool "0x3f8, COM1" -config UART5_IO_PORT_2F8 - bool "0x2f8, COM2" -config UART5_IO_PORT_3E8 - bool "0x3e8, COM3" -config UART5_IO_PORT_2E8 - bool "0x2e8, COM4" -config UART5_IO_PORT_OTHER - bool "Other" - -endchoice - -config UART5_IO_PORT_OTHER_INPUT - hex "UART5 I/O port" - depends on UART5_ENABLE && UART5_IO_PORT_OTHER - -config UART5_IO - hex - depends on UART5_ENABLE - default 0x3f8 if UART5_IO_PORT_3F8 - default 0x2f8 if UART5_IO_PORT_2F8 - default 0x3e8 if UART5_IO_PORT_3E8 - default 0x2e8 if UART5_IO_PORT_2E8 - default UART5_IO_PORT_OTHER_INPUT if UART5_IO_PORT_OTHER - -choice - prompt "UART5 IRQ" - default UART5_IRQ_DISABLE - depends on UART5_ENABLE - -config UART5_IRQ_DISABLE - bool "Disable" -config UART5_IRQ3 - bool "IRQ3, COM2" -config UART5_IRQ4 - bool "IRQ4, COM1" -config UART5_IRQ5 - bool "IRQ5" -config UART5_IRQ6 - bool "IRQ6" -config UART5_IRQ7 - bool "IRQ7" -config UART5_IRQ9 - bool "IRQ9" -config UART5_IRQ10 - bool "IRQ10, COM3" -config UART5_IRQ11 - bool "IRQ11, COM4" -config UART5_IRQ12 - bool "IRQ12" -config UART5_IRQ14 - bool "IRQ14" -config UART5_IRQ15 - bool "IRQ15" - -endchoice - -config UART5_IRQ - int - depends on UART5_ENABLE - default 0 if UART5_IRQ_DISABLE - default 3 if UART5_IRQ3 - default 4 if UART5_IRQ4 - default 5 if UART5_IRQ5 - default 6 if UART5_IRQ6 - default 7 if UART5_IRQ7 - default 9 if UART5_IRQ9 - default 10 if UART5_IRQ10 - default 11 if UART5_IRQ11 - default 12 if UART5_IRQ12 - default 14 if UART5_IRQ14 - default 15 if UART5_IRQ15 - -# end of UART5 - -# Begin of UART6 -config UART6_ENABLE - bool "UART6 Enable" - default n - -choice - prompt "UART6 I/O port" - default UART6_IO_PORT_OTHER - depends on UART6_ENABLE - -config UART6_IO_PORT_3F8 - bool "0x3f8, COM1" -config UART6_IO_PORT_2F8 - bool "0x2f8, COM2" -config UART6_IO_PORT_3E8 - bool "0x3e8, COM3" -config UART6_IO_PORT_2E8 - bool "0x2e8, COM4" -config UART6_IO_PORT_OTHER - bool "Other" - -endchoice - -config UART6_IO_PORT_OTHER_INPUT - hex "UART6 I/O port" - depends on UART6_ENABLE && UART6_IO_PORT_OTHER - -config UART6_IO - hex - depends on UART6_ENABLE - default 0x3f8 if UART6_IO_PORT_3F8 - default 0x2f8 if UART6_IO_PORT_2F8 - default 0x3e8 if UART6_IO_PORT_3E8 - default 0x2e8 if UART6_IO_PORT_2E8 - default UART6_IO_PORT_OTHER_INPUT if UART6_IO_PORT_OTHER - -choice - prompt "UART6 IRQ" - default UART6_IRQ_DISABLE - depends on UART6_ENABLE - -config UART6_IRQ_DISABLE - bool "Disable" -config UART6_IRQ3 - bool "IRQ3, COM2" -config UART6_IRQ4 - bool "IRQ4, COM1" -config UART6_IRQ5 - bool "IRQ5" -config UART6_IRQ6 - bool "IRQ6" -config UART6_IRQ7 - bool "IRQ7" -config UART6_IRQ9 - bool "IRQ9" -config UART6_IRQ10 - bool "IRQ10, COM3" -config UART6_IRQ11 - bool "IRQ11, COM4" -config UART6_IRQ12 - bool "IRQ12" -config UART6_IRQ14 - bool "IRQ14" -config UART6_IRQ15 - bool "IRQ15" - -endchoice - -config UART6_IRQ - int - depends on UART6_ENABLE - default 0 if UART6_IRQ_DISABLE - default 3 if UART6_IRQ3 - default 4 if UART6_IRQ4 - default 5 if UART6_IRQ5 - default 6 if UART6_IRQ6 - default 7 if UART6_IRQ7 - default 9 if UART6_IRQ9 - default 10 if UART6_IRQ10 - default 11 if UART6_IRQ11 - default 12 if UART6_IRQ12 - default 14 if UART6_IRQ14 - default 15 if UART6_IRQ15 - -# end of UART6 - -# Begin of UART7 -config UART7_ENABLE - bool "UART7 Enable" - default n - -choice - prompt "UART7 I/O port" - default UART7_IO_PORT_OTHER - depends on UART7_ENABLE - -config UART7_IO_PORT_3F8 - bool "0x3f8, COM1" -config UART7_IO_PORT_2F8 - bool "0x2f8, COM2" -config UART7_IO_PORT_3E8 - bool "0x3e8, COM3" -config UART7_IO_PORT_2E8 - bool "0x2e8, COM4" -config UART7_IO_PORT_OTHER - bool "Other" - -endchoice - -config UART7_IO_PORT_OTHER_INPUT - hex "UART7 I/O port" - depends on UART7_ENABLE && UART7_IO_PORT_OTHER - -config UART7_IO - hex - depends on UART7_ENABLE - default 0x3f8 if UART7_IO_PORT_3F8 - default 0x2f8 if UART7_IO_PORT_2F8 - default 0x3e8 if UART7_IO_PORT_3E8 - default 0x2e8 if UART7_IO_PORT_2E8 - default UART7_IO_PORT_OTHER_INPUT if UART7_IO_PORT_OTHER - -choice - prompt "UART7 IRQ" - default UART7_IRQ_DISABLE - depends on UART7_ENABLE - -config UART7_IRQ_DISABLE - bool "Disable" -config UART7_IRQ3 - bool "IRQ3, COM2" -config UART7_IRQ4 - bool "IRQ4, COM1" -config UART7_IRQ5 - bool "IRQ5" -config UART7_IRQ6 - bool "IRQ6" -config UART7_IRQ7 - bool "IRQ7" -config UART7_IRQ9 - bool "IRQ9" -config UART7_IRQ10 - bool "IRQ10, COM3" -config UART7_IRQ11 - bool "IRQ11, COM4" -config UART7_IRQ12 - bool "IRQ12" -config UART7_IRQ14 - bool "IRQ14" -config UART7_IRQ15 - bool "IRQ15" - -endchoice - -config UART7_IRQ - int - depends on UART7_ENABLE - default 0 if UART7_IRQ_DISABLE - default 3 if UART7_IRQ3 - default 4 if UART7_IRQ4 - default 5 if UART7_IRQ5 - default 6 if UART7_IRQ6 - default 7 if UART7_IRQ7 - default 9 if UART7_IRQ9 - default 10 if UART7_IRQ10 - default 11 if UART7_IRQ11 - default 12 if UART7_IRQ12 - default 14 if UART7_IRQ14 - default 15 if UART7_IRQ15 - -# end of UART7 - -# Begin of UART8 -config UART8_ENABLE - bool "UART8 Enable" - default n - -choice - prompt "UART8 I/O port" - default UART8_IO_PORT_OTHER - depends on UART8_ENABLE - -config UART8_IO_PORT_3F8 - bool "0x3f8, COM1" -config UART8_IO_PORT_2F8 - bool "0x2f8, COM2" -config UART8_IO_PORT_3E8 - bool "0x3e8, COM3" -config UART8_IO_PORT_2E8 - bool "0x2e8, COM4" -config UART8_IO_PORT_OTHER - bool "Other" - -endchoice - -config UART8_IO_PORT_OTHER_INPUT - hex "UART8 I/O port" - depends on UART8_ENABLE && UART8_IO_PORT_OTHER - -config UART8_IO - hex - depends on UART8_ENABLE - default 0x3f8 if UART8_IO_PORT_3F8 - default 0x2f8 if UART8_IO_PORT_2F8 - default 0x3e8 if UART8_IO_PORT_3E8 - default 0x2e8 if UART8_IO_PORT_2E8 - default UART8_IO_PORT_OTHER_INPUT if UART8_IO_PORT_OTHER - -choice - prompt "UART8 IRQ" - default UART8_IRQ_DISABLE - depends on UART8_ENABLE - -config UART8_IRQ_DISABLE - bool "Disable" -config UART8_IRQ3 - bool "IRQ3, COM2" -config UART8_IRQ4 - bool "IRQ4, COM1" -config UART8_IRQ5 - bool "IRQ5" -config UART8_IRQ6 - bool "IRQ6" -config UART8_IRQ7 - bool "IRQ7" -config UART8_IRQ9 - bool "IRQ9" -config UART8_IRQ10 - bool "IRQ10, COM3" -config UART8_IRQ11 - bool "IRQ11, COM4" -config UART8_IRQ12 - bool "IRQ12" -config UART8_IRQ14 - bool "IRQ14" -config UART8_IRQ15 - bool "IRQ15" - -endchoice - -config UART8_IRQ - int - depends on UART8_ENABLE - default 0 if UART8_IRQ_DISABLE - default 3 if UART8_IRQ3 - default 4 if UART8_IRQ4 - default 5 if UART8_IRQ5 - default 6 if UART8_IRQ6 - default 7 if UART8_IRQ7 - default 9 if UART8_IRQ9 - default 10 if UART8_IRQ10 - default 11 if UART8_IRQ11 - default 12 if UART8_IRQ12 - default 14 if UART8_IRQ14 - default 15 if UART8_IRQ15 - -# end of UART8 - -# Begin of UART9 -config UART9_ENABLE - bool "UART9 Enable" - default n - -choice - prompt "UART9 I/O port" - default UART9_IO_PORT_OTHER - depends on UART9_ENABLE - -config UART9_IO_PORT_3F8 - bool "0x3f8, COM1" -config UART9_IO_PORT_2F8 - bool "0x2f8, COM2" -config UART9_IO_PORT_3E8 - bool "0x3e8, COM3" -config UART9_IO_PORT_2E8 - bool "0x2e8, COM4" -config UART9_IO_PORT_OTHER - bool "Other" - -endchoice - -config UART9_IO_PORT_OTHER_INPUT - hex "UART9 I/O port" - depends on UART9_ENABLE && UART9_IO_PORT_OTHER - -config UART9_IO - hex - depends on UART9_ENABLE - default 0x3f8 if UART9_IO_PORT_3F8 - default 0x2f8 if UART9_IO_PORT_2F8 - default 0x3e8 if UART9_IO_PORT_3E8 - default 0x2e8 if UART9_IO_PORT_2E8 - default UART9_IO_PORT_OTHER_INPUT if UART9_IO_PORT_OTHER - -choice - prompt "UART9 IRQ" - default UART9_IRQ_DISABLE - depends on UART9_ENABLE - -config UART9_IRQ_DISABLE - bool "Disable" -config UART9_IRQ3 - bool "IRQ3, COM2" -config UART9_IRQ4 - bool "IRQ4, COM1" -config UART9_IRQ5 - bool "IRQ5" -config UART9_IRQ6 - bool "IRQ6" -config UART9_IRQ7 - bool "IRQ7" -config UART9_IRQ9 - bool "IRQ9" -config UART9_IRQ10 - bool "IRQ10, COM3" -config UART9_IRQ11 - bool "IRQ11, COM4" -config UART9_IRQ12 - bool "IRQ12" -config UART9_IRQ14 - bool "IRQ14" -config UART9_IRQ15 - bool "IRQ15" - -endchoice - -config UART9_IRQ - int - depends on UART9_ENABLE - default 0 if UART9_IRQ_DISABLE - default 3 if UART9_IRQ3 - default 4 if UART9_IRQ4 - default 5 if UART9_IRQ5 - default 6 if UART9_IRQ6 - default 7 if UART9_IRQ7 - default 9 if UART9_IRQ9 - default 10 if UART9_IRQ10 - default 11 if UART9_IRQ11 - default 12 if UART9_IRQ12 - default 14 if UART9_IRQ14 - default 15 if UART9_IRQ15 - -# end of UART9 - -# Begin of UART10 -config UART10_ENABLE - bool "UART10 Enable" - default n - -choice - prompt "UART10 I/O port" - default UART10_IO_PORT_OTHER - depends on UART10_ENABLE - -config UART10_IO_PORT_3F8 - bool "0x3f8, COM1" -config UART10_IO_PORT_2F8 - bool "0x2f8, COM2" -config UART10_IO_PORT_3E8 - bool "0x3e8, COM3" -config UART10_IO_PORT_2E8 - bool "0x2e8, COM4" -config UART10_IO_PORT_OTHER - bool "Other" - -endchoice - -config UART10_IO_PORT_OTHER_INPUT - hex "UART10 I/O port" - depends on UART10_ENABLE && UART10_IO_PORT_OTHER - -config UART10_IO - hex - depends on UART10_ENABLE - default 0x3f8 if UART10_IO_PORT_3F8 - default 0x2f8 if UART10_IO_PORT_2F8 - default 0x3e8 if UART10_IO_PORT_3E8 - default 0x2e8 if UART10_IO_PORT_2E8 - default UART10_IO_PORT_OTHER_INPUT if UART10_IO_PORT_OTHER - -choice - prompt "UART10 IRQ" - default UART10_IRQ_DISABLE - depends on UART10_ENABLE - -config UART10_IRQ_DISABLE - bool "Disable" -config UART10_IRQ3 - bool "IRQ3, COM2" -config UART10_IRQ4 - bool "IRQ4, COM1" -config UART10_IRQ5 - bool "IRQ5" -config UART10_IRQ6 - bool "IRQ6" -config UART10_IRQ7 - bool "IRQ7" -config UART10_IRQ9 - bool "IRQ9" -config UART10_IRQ10 - bool "IRQ10, COM3" -config UART10_IRQ11 - bool "IRQ11, COM4" -config UART10_IRQ12 - bool "IRQ12" -config UART10_IRQ14 - bool "IRQ14" -config UART10_IRQ15 - bool "IRQ15" - -endchoice - -config UART10_IRQ - int - depends on UART10_ENABLE - default 0 if UART10_IRQ_DISABLE - default 3 if UART10_IRQ3 - default 4 if UART10_IRQ4 - default 5 if UART10_IRQ5 - default 6 if UART10_IRQ6 - default 7 if UART10_IRQ7 - default 9 if UART10_IRQ9 - default 10 if UART10_IRQ10 - default 11 if UART10_IRQ11 - default 12 if UART10_IRQ12 - default 14 if UART10_IRQ14 - default 15 if UART10_IRQ15 - -# end of UART10 - -endmenu - -# LPT setting : -menu "LPT setting" - -# Begin of LPT -config LPT_ENABLE - bool "LPT Enable" - default n - -choice - prompt "LPT I/O port" - default LPT_IO_PORT_278 - depends on LPT_ENABLE - -config LPT_IO_PORT_378 - bool "0x378, LPT1" -config LPT_IO_PORT_278 - bool "0x278, LPT2" -config LPT_IO_PORT_OTHER - bool "Other" - -endchoice - -config LPT_IO_PORT_OTHER_INPUT - hex "LPT I/O port" - depends on LPT_ENABLE && LPT_IO_PORT_OTHER - -config LPT_IO - hex - depends on LPT_ENABLE - default 0x378 if LPT_IO_PORT_378 - default 0x278 if LPT_IO_PORT_278 - default LPT_IO_PORT_OTHER_INPUT if LPT_IO_PORT_OTHER - -choice - prompt "LPT IRQ" - default LPT_IRQ_DISABLE - depends on LPT_ENABLE - -config LPT_IRQ_DISABLE - bool "Disable" -config LPT_IRQ3 - bool "IRQ3" -config LPT_IRQ4 - bool "IRQ4" -config LPT_IRQ5 - bool "IRQ5" -config LPT_IRQ6 - bool "IRQ6" -config LPT_IRQ7 - bool "IRQ7" -config LPT_IRQ9 - bool "IRQ9" -config LPT_IRQ10 - bool "IRQ10" -config LPT_IRQ11 - bool "IRQ11" -config LPT_IRQ12 - bool "IRQ12" -config LPT_IRQ14 - bool "IRQ14" -config LPT_IRQ15 - bool "IRQ15" - -endchoice - -config LPT_IRQ - int - depends on LPT_ENABLE - default 0 if LPT_IRQ_DISABLE - default 3 if LPT_IRQ3 - default 4 if LPT_IRQ4 - default 5 if LPT_IRQ5 - default 6 if LPT_IRQ6 - default 7 if LPT_IRQ7 - default 9 if LPT_IRQ9 - default 10 if LPT_IRQ10 - default 11 if LPT_IRQ11 - default 12 if LPT_IRQ12 - default 14 if LPT_IRQ14 - default 15 if LPT_IRQ15 - -choice - prompt "LPT Mode Setting" - default LPT_MODE_SPP - depends on LPT_ENABLE - -config LPT_MODE_BPP - bool "BPP mode" -config LPT_MODE_EPP_19_AND_SPP - bool "EPP 1.9 and SPP mode" -config LPT_MODE_ECP - bool "ECP Mode" -config LPT_MODE_ECP_AND_EPP_19 - bool "ECP and EPP 1.9 mode" -config LPT_MODE_SPP - bool "SPP Mode" -config LPT_MODE_EPP_17_AND_SPP - bool "EPP 1.7 and SPP mode" -config LPT_MODE_ECP_AND_EPP_17 - bool "ECP and EPP 1.7 mode" - -endchoice - -# end of LPT - -endmenu - -endif # BOARD_DMP_EX diff --git a/src/mainboard/dmp/vortex86ex/Kconfig.name b/src/mainboard/dmp/vortex86ex/Kconfig.name deleted file mode 100644 index 8e1a5647d7..0000000000 --- a/src/mainboard/dmp/vortex86ex/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_DMP_EX - bool "Vortex86EX" diff --git a/src/mainboard/dmp/vortex86ex/board_info.txt b/src/mainboard/dmp/vortex86ex/board_info.txt deleted file mode 100644 index c67b641a94..0000000000 --- a/src/mainboard/dmp/vortex86ex/board_info.txt +++ /dev/null @@ -1 +0,0 @@ -Category: sbc diff --git a/src/mainboard/dmp/vortex86ex/devicetree.cb b/src/mainboard/dmp/vortex86ex/devicetree.cb deleted file mode 100644 index 4106bed448..0000000000 --- a/src/mainboard/dmp/vortex86ex/devicetree.cb +++ /dev/null @@ -1,28 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013 DMP Electronics Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -chip soc/dmp/vortex86ex # North Bridge - device domain 0 on - device pci 0.0 on end # Host Bridge - device pci 7.0 on end # ISA Bridge - device pci 8.0 on end # Ethernet - device pci a.0 on end # USB 1.1 - device pci a.1 on end # USB 2.0 - device pci b.0 on end # USB 1.1 - device pci b.1 on end # USB 2.0 - device pci c.0 on end # IDE - end # pci domain 0 - chip cpu/dmp/vortex86ex end # CPU -end diff --git a/src/mainboard/dmp/vortex86ex/hda_verb.c b/src/mainboard/dmp/vortex86ex/hda_verb.c deleted file mode 100644 index 5c728077da..0000000000 --- a/src/mainboard/dmp/vortex86ex/hda_verb.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 DMP Electronics Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/azalia_device.h> - -const u32 cim_verb_data[] = { - /* coreboot specific header */ - 0x10ec0262, // Codec Vendor / Device ID: Realtek ALC262 - 0x10714700, // Subsystem ID - 0x0000000f, // Number of jacks - - /* ===== HDA Codec Subsystem ID Verb-table ===== */ - /* HDA Codec Subsystem ID : 0x10EC0000 */ - AZALIA_SUBVENDOR(0x0, 0x10ec0000), - - /* ===== Pin Widget Verb-table ===== */ - /* Widget node 0x01 : */ - 0x0017ff00, - 0x0017ff00, - 0x0017ff00, - 0x0017ff00, - /* Pin widget 0x11 - S/PDIF-OUT2 */ - AZALIA_PIN_CFG(0x0, 0x11, 0x40000000), - /* Pin widget 0x12 - DMIC */ - AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0), - /* Pin widget 0x14 - LINE-OUT (Port-D) */ - AZALIA_PIN_CFG(0x0, 0x14, 0x01014110), - /* Pin widget 0x15 - HP-OUT (Port-A) */ - AZALIA_PIN_CFG(0x0, 0x15, 0x411111f0), - /* Pin widget 0x16 - MONO-OUT */ - AZALIA_PIN_CFG(0x0, 0x16, 0x411111f0), - /* Pin widget 0x18 - MIC1 (Port-B) */ - AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0), - /* Pin widget 0x19 - MIC2 (Port-F) */ - AZALIA_PIN_CFG(0x0, 0x19, 0x02a19130), - /* Pin widget 0x1A - LINE1 (Port-C) */ - AZALIA_PIN_CFG(0x0, 0x1a, 0x01813140), - /* Pin widget 0x1B - LINE2 (Port-E) */ - AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0), - /* Pin widget 0x1C - CD-IN */ - AZALIA_PIN_CFG(0x0, 0x1c, 0x411111f0), - /* Pin widget 0x1D - BEEP-IN */ - AZALIA_PIN_CFG(0x0, 0x1d, 0x40354629), - /* Pin widget 0x1E - S/PDIF-OUT */ - AZALIA_PIN_CFG(0x0, 0x1e, 0x18561120), - /* Pin widget 0x1F - S/PDIF-IN */ - AZALIA_PIN_CFG(0x0, 0x1f, 0x411111f0), -}; - -const u32 pc_beep_verbs[0] = {}; - -AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/dmp/vortex86ex/irq_tables.c b/src/mainboard/dmp/vortex86ex/irq_tables.c deleted file mode 100644 index 9e4e77fd60..0000000000 --- a/src/mainboard/dmp/vortex86ex/irq_tables.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 DMP Electronics Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/pirq_routing.h> - -static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32 + 16 * 12, /* Max. number of devices on the bus */ - 0x00, /* Interrupt router bus */ - (0x07 << 3) | 0x0, /* Interrupt router dev */ - 0, /* IRQs devoted exclusively to PCI usage */ - 0x17f3, /* Vendor */ - 0x6031, /* Device */ - 0, /* Miniport */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0xa, /* Checksum (has to be set to some value that - * would give 0 after the sum of all bytes - * for this structure (including checksum). - */ - { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, (0x01 << 3) | 0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}}, 0x1, 0x0}, - {0x00, (0x02 << 3) | 0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}}, 0x2, 0x0}, - {0x00, (0x03 << 3) | 0x0, {{0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}}, 0x0, 0x0}, - {0x00, (0x04 << 3) | 0x0, {{0x04, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}}, 0x4, 0x0}, - {0x00, (0x05 << 3) | 0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}}, 0x5, 0x0}, - {0x00, (0x06 << 3) | 0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}}, 0x6, 0x0}, - {0x00, (0x08 << 3) | 0x0, {{0x05, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, - {0x00, (0x0a << 3) | 0x0, {{0x07, 0xdef8}, {0x08, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, - {0x00, (0x0b << 3) | 0x0, {{0x09, 0xdef8}, {0x0a, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, - {0x00, (0x0c << 3) | 0x0, {{0x0b, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, - {0x00, (0x0f << 3) | 0x0, {{0x0d, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, - {0x00, (0x0e << 3) | 0x0, {{0x0e, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/dmp/vortex86ex/romstage.c b/src/mainboard/dmp/vortex86ex/romstage.c deleted file mode 100644 index 108cc1d669..0000000000 --- a/src/mainboard/dmp/vortex86ex/romstage.c +++ /dev/null @@ -1,352 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Andrew Wu <arw@dmp.com.tw> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <arch/io.h> -#include <stdlib.h> -#include "arch/x86/romcc_console.c" -#include <console/console.h> -#include <cpu/x86/cache.h> -#include <halt.h> -#include "drivers/pc80/pc/i8254.c" -#include <soc/dmp/vortex86ex/northbridge.h> -#include <soc/dmp/vortex86ex/southbridge.h> -#include "soc/dmp/vortex86ex/raminit.c" -#include <cpu/dmp/dmp_post_code.h> - -#define DMP_CPUID_SX 0x31504d44 -#define DMP_CPUID_DX 0x32504d44 -#define DMP_CPUID_MX 0x33504d44 -#define DMP_CPUID_DX2 0x34504d44 -#define DMP_CPUID_MX_PLUS 0x35504d44 -#define DMP_CPUID_EX 0x37504d44 - -static u32 get_dmp_id(void) -{ - return pci_read_config32(NB, NB_REG_CID); -} - -/* Indirect access registers for Watch-dog timer, GPIO PORT 0,1 - * Index port is for I/O port 22h - * Index port 13h (00: lock register, C5h: unlock register) for lock/unlock function - * Index port 37h, 39h, 3Ah, 3Bh, 3Ch for Watchdog timer - * Index port 46h, 47h, 4Ch, 4Dh, 4Eh, 4Fh for GPIO port 0, 1 - */ -static void write_indirect_reg(u8 index, u8 data) -{ - outb(index, 0x22); - outb(data, 0x23); -} - -static void lock_indirect_reg(void) -{ - write_indirect_reg(0x13, 0x00); -} - -static void unlock_indirect_reg(void) -{ - write_indirect_reg(0x13, 0xc5); -} - -static void disable_watchdog(void) -{ - unlock_indirect_reg(); - // disable watchdog timer - write_indirect_reg(0x37, 0x0); -} - -void set_ex_powerdown_control(void) -{ - u32 powerdown_ctrl; - powerdown_ctrl = pci_read_config32(SB, 0xbc); -#if IS_ENABLED(CONFIG_TEMP_POWERDOWN) - powerdown_ctrl |= (1 << 31); -#endif -#if IS_ENABLED(CONFIG_SATA_POWERDOWN) - powerdown_ctrl |= (1 << 30); -#endif -#if IS_ENABLED(CONFIG_ADC_POWERDOWN) - powerdown_ctrl |= (1 << 28); -#endif -#if IS_ENABLED(CONFIG_PCIE0_POWERDOWN) - powerdown_ctrl |= (1 << 13); -#endif -#if IS_ENABLED(CONFIG_MAC_POWERDOWN) - powerdown_ctrl |= (1 << 3); -#endif -#if IS_ENABLED(CONFIG_USB1_POWERDOWN) - powerdown_ctrl |= (1 << 1); -#endif -#if IS_ENABLED(CONFIG_IDE_POWERDOWN) - powerdown_ctrl |= (1 << 0); -#endif - pci_write_config32(SB, 0xbc, powerdown_ctrl); -} - -static void set_pci_nb_pmcr(void) -{ - u8 pmcr = pci_read_config8(NB, NB_REG_PMCR); - /* - * Set PCI Master Max Cycle Length (MCL) to 32 PCI clocks. - * Set PCI Master Burst Write Length (BL) to Burst length over 3. - */ - pmcr |= 0x0f; - pci_write_config8(NB, NB_REG_PMCR, pmcr); -} - -static void set_pci_sb_lpccr(void) -{ - u8 lpccr = pci_read_config8(SB, SB_REG_LPCCR); - /* Set PCI Soft Reset Control to 1. - * (When the CPU soft reset is initialized, PCIRST# will be active.) - * Set P92FE to 1. (I/O port 92 Register Write Function Enable.) - * Set P92S to 1. (Internal Port 92h Selected.) - */ - lpccr |= 0x16; - pci_write_config8(SB, SB_REG_LPCCR, lpccr); - /* enable fast ga20 */ - outb(inb(SYSTEM_CTL_PORT) | 0x02, SYSTEM_CTL_PORT); -} - -static u32 make_uart_config(u16 base, u8 irq) -{ - /* Set base IO address only, skip IRQ. IRQ will be setup in - * southbridge stage. */ - u32 cfg = 0; - cfg |= 1 << 23; // UE = enabled. - cfg |= base; // UIOA. - return cfg; -} - -#define SETUP_UART(n) \ - uart_cfg = make_uart_config(CONFIG_UART##n##_IO, CONFIG_UART##n##_IRQ);\ - outl(uart_cfg, 0xc00 + (n - 1) * 4); - -static void ex_uart_early_init(void) -{ -#if CONFIG_TTYS0_BASE - u32 uart_cfg = 0; - /* Set UART Config I/O base address to 0xc00 */ - pci_write_config16(SB, 0x60, 0xc01); - /* If serial console base address is defined, find out which - * UART uses this address, and setup this UART first. */ -#if CONFIG_TTYS0_BASE == CONFIG_UART1_IO - SETUP_UART(1) -#elif CONFIG_TTYS0_BASE == CONFIG_UART2_IO - SETUP_UART(2) -#elif CONFIG_TTYS0_BASE == CONFIG_UART3_IO - SETUP_UART(3) -#elif CONFIG_TTYS0_BASE == CONFIG_UART4_IO - SETUP_UART(4) -#elif CONFIG_TTYS0_BASE == CONFIG_UART5_IO - SETUP_UART(5) -#elif CONFIG_TTYS0_BASE == CONFIG_UART6_IO - SETUP_UART(6) -#elif CONFIG_TTYS0_BASE == CONFIG_UART7_IO - SETUP_UART(7) -#elif CONFIG_TTYS0_BASE == CONFIG_UART8_IO - SETUP_UART(8) -#elif CONFIG_TTYS0_BASE == CONFIG_UART9_IO - SETUP_UART(9) -#elif CONFIG_TTYS0_BASE == CONFIG_UART10_IO - SETUP_UART(10) -#endif -#endif -} - -static void init_wdt1(void) -{ -#if IS_ENABLED(CONFIG_WDT1_INITIALIZE) -#if IS_ENABLED(CONFIG_WDT1_ENABLE) - outb(0x1 << 6, 0xa8); -#endif - u8 wdt1_signal_reg = 0; -#if IS_ENABLED(CONFIG_WDT1_SINGAL_NMI) - wdt1_signal_reg = 0x0c << 4; -#elif IS_ENABLED(CONFIG_WDT1_SIGNAL_RESET) - wdt1_signal_reg = 0x0d << 4; -#elif IS_ENABLED(CONFIG_WDT1_SIGNAL_SMI) - wdt1_signal_reg = 0x0e << 4; -#endif - outb(wdt1_signal_reg, 0xa9); -#endif -} - -/* Fill 32bit pattern into specified DRAM region. */ -static void fill_dram(u32 * p, u32 pattern, u32 test_len) -{ - if (test_len == 0) - return; -#if 0 - // C version, very slow. - for (p = (u32 *) 0; (u32) p < test_len; p++) { - *p = pattern; - } -#endif - // ASM version, much faster. - asm volatile ( - "cld\n\t" - "rep\n\t" - "stosl" - : /* no output registers */ - : "c" (test_len / 4), "a" (pattern), "D" (p) - ); -} - -/* Verify 32bit pattern in specified DRAM region. - * Return -1 if ok, failed memory address if error. */ -static int verify_dram(u32 * p, u32 pattern, u32 test_len) -{ - if (test_len == 0) - return -1; -#if 0 - // C version, very slow. - for (p = (u32 *) 0; (u32) p < test_len; p++) { - if (*p != pattern) { - return (int)p; - } - } - return -1; -#endif - u16 flags; - int addr; - asm volatile ( - "cld\n\t" - "rep\n\t" - "scasl\n\t" - "lahf\n\t" - : "=a" (flags), "=D" (addr) - : "c" (test_len / 4), "a" (pattern), "D" (p) - ); - if (flags & (1 << (6 + 8))) // x86 zero flag = bit 6. - { - return -1; // verify ok - } - return addr - 4; // verify error, return error address. -} - -static void test_dram_stability(void) -{ - u32 test_len = 2048 * 1024; - u32 pat = 0x5aa5a55a; - u32 ext_mem_start = 0xc0000; - u32 base_mem_test_len = test_len > 640 * 1024 ? 640 * 1024 : test_len; - u32 ext_mem_test_len = test_len > ext_mem_start ? test_len - ext_mem_start : 0; - if (ext_mem_test_len > 0) { - /* Enable all shadow RAM region C0000 - FFFFF. */ - pci_write_config32(NB, NB_REG_MAR, 0x3ffffff0); - } - int v; - fill_dram((u32 *) 0, pat, base_mem_test_len); - fill_dram((u32 *) ext_mem_start, pat, ext_mem_test_len); - v = verify_dram((u32 *) 0, pat, base_mem_test_len); - if (v == -1) { - v = verify_dram((u32 *) ext_mem_start, pat, ext_mem_test_len); - } - /* Change pattern and test again */ - if (v == -1) { - pat = 0xa55a5aa5; - fill_dram((u32 *) 0, pat, base_mem_test_len); - fill_dram((u32 *) ext_mem_start, pat, ext_mem_test_len); - v = verify_dram((u32 *) 0, pat, base_mem_test_len); - if (v == -1) { - v = verify_dram((u32 *) ext_mem_start, pat, ext_mem_test_len); - } - } - if (v != -1) { - post_code(POST_DMP_DRAM_TEST_ERR); - print_emerg("DRAM stablility test error!\nADDR = "); - print_emerg_hex32(v); - print_emerg(", WRITE = "); - print_emerg_hex32(pat); - u32 r = *(u32 *) v; - print_emerg(", READ = "); - print_emerg_hex32(r); - print_emerg(", XOR = "); - print_emerg_hex32(r ^ pat); - print_emerg("\n"); - die("System halted.\n"); - } - if (ext_mem_test_len > 0) { - /* Disable shadow RAM. */ - pci_write_config32(NB, NB_REG_MAR, 0x0); - } -} - -static void enable_l2_cache(void) -{ - /* - * Enable L2 cache by setting PCI N/B function 1 L2 cache - * control register (0xe8) bit 0 (L2_EN) and bit 1 (L2_WB_EN). - */ - u32 reg_nb_f1_e8; - reg_nb_f1_e8 = pci_read_config8(NB1, 0xe8); - reg_nb_f1_e8 |= 3; - pci_write_config8(NB1, 0xe8, reg_nb_f1_e8); -} - -static void main(unsigned long bist) -{ - u32 dmp_id; - - dmp_id = get_dmp_id(); - if (dmp_id != DMP_CPUID_EX) { - /* Not DMP Vortex86EX CPU. */ - post_code(POST_DMP_ID_ERR); - halt(); - } - disable_watchdog(); - set_ex_powerdown_control(); - set_pci_nb_pmcr(); - set_pci_sb_lpccr(); - ex_uart_early_init(); - - console_init(); - - init_wdt1(); - - /* Initialize i8254 timers */ - post_code(0x42); - setup_i8254(); - - /* Initialize DRAM */ - u8 reg_nb_f1_cc; - /* Setup DDR3 Timing reg 0-3 / Config reg */ - pci_write_config16(NB, 0x6e, 0x0a2f); - pci_write_config32(NB, 0x74, 0x84010200); - pci_write_config32(NB, 0x78, 0x33405544); - pci_write_config32(NB, 0x7c, 0x2e0f0e0b); - /* Disable enhance read push write */ - reg_nb_f1_cc = pci_read_config8(NB1, 0xcc); - reg_nb_f1_cc &= ~(1 << 4); - pci_write_config8(NB1, 0xcc, reg_nb_f1_cc); - if (detect_ddr3_dram_size()) { - post_code(POST_DMP_DRAM_SIZING_ERR); - die("DRAM sizing error!\n"); - } - /* Reset enhance read push write to default(enable) */ - reg_nb_f1_cc |= (1 << 4); - pci_write_config8(NB1, 0xcc, reg_nb_f1_cc); - - print_ddr3_memory_setup(); - test_dram_stability(); - - /* CPU setup, romcc pukes on invd() */ - asm volatile ("invd"); - enable_cache(); - - enable_l2_cache(); -} |