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-rw-r--r--src/mainboard/google/beltino/chromeos.c1
-rw-r--r--src/mainboard/google/jecht/chromeos.c1
-rw-r--r--src/mainboard/intel/glkrvp/chromeos.c7
-rw-r--r--src/mainboard/samsung/lumpy/Kconfig1
-rw-r--r--src/mainboard/samsung/lumpy/chromeos.c46
-rw-r--r--src/mainboard/samsung/stumpy/Kconfig1
-rw-r--r--src/mainboard/samsung/stumpy/chromeos.c48
7 files changed, 25 insertions, 80 deletions
diff --git a/src/mainboard/google/beltino/chromeos.c b/src/mainboard/google/beltino/chromeos.c
index dfa93a263d..1a1d0a29dc 100644
--- a/src/mainboard/google/beltino/chromeos.c
+++ b/src/mainboard/google/beltino/chromeos.c
@@ -26,7 +26,6 @@
#define FLAG_SPI_WP 0
#define FLAG_REC_MODE 1
-#define FLAG_DEV_MODE 2
#if ENV_RAMSTAGE
#include <boot/coreboot_tables.h>
diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c
index 548470ecff..c0b14f3d87 100644
--- a/src/mainboard/google/jecht/chromeos.c
+++ b/src/mainboard/google/jecht/chromeos.c
@@ -27,7 +27,6 @@
#define FLAG_SPI_WP 0
#define FLAG_REC_MODE 1
-#define FLAG_DEV_MODE 2
#if ENV_RAMSTAGE
#include <boot/coreboot_tables.h>
diff --git a/src/mainboard/intel/glkrvp/chromeos.c b/src/mainboard/intel/glkrvp/chromeos.c
index 1da0d29431..07d92e96fe 100644
--- a/src/mainboard/intel/glkrvp/chromeos.c
+++ b/src/mainboard/intel/glkrvp/chromeos.c
@@ -26,7 +26,6 @@ void fill_lb_gpios(struct lb_gpios *gpios)
struct lb_gpio chromeos_gpios[] = {
{-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},
{-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
- {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"},
{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
{-1, ACTIVE_HIGH, 0, "power"},
{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
@@ -35,12 +34,6 @@ void fill_lb_gpios(struct lb_gpios *gpios)
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
}
-int get_developer_mode_switch(void)
-{
- /* No physical developer mode switch. It's virtual. */
- return 0;
-}
-
int get_write_protect_state(void)
{
return 0;
diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig
index 68aeabd041..37c967f804 100644
--- a/src/mainboard/samsung/lumpy/Kconfig
+++ b/src/mainboard/samsung/lumpy/Kconfig
@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS
select INTEL_INT15
config VBOOT
- select VBOOT_PHYSICAL_DEV_SWITCH
select VBOOT_PHYSICAL_REC_SWITCH
select VBOOT_VBNV_CMOS
diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c
index 0dba27a644..5d688fe9f9 100644
--- a/src/mainboard/samsung/lumpy/chromeos.c
+++ b/src/mainboard/samsung/lumpy/chromeos.c
@@ -25,18 +25,16 @@
#define GPIO_SPI_WP 24
#define GPIO_REC_MODE 42
-#define GPIO_DEV_MODE 17
#define FLAG_SPI_WP 0
#define FLAG_REC_MODE 1
-#define FLAG_DEV_MODE 2
#if ENV_RAMSTAGE
#include <boot/coreboot_tables.h>
#include "ec.h"
#include <ec/smsc/mec1308/ec.h>
-#define GPIO_COUNT 6
+#define GPIO_COUNT 5
void fill_lb_gpios(struct lb_gpios *gpios)
{
@@ -60,28 +58,22 @@ void fill_lb_gpios(struct lb_gpios *gpios)
gpios->gpios[1].value = !get_recovery_mode_switch();
strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH);
- /* Developer: GPIO17 = KBC3_DVP_MODE */
- gpios->gpios[2].port = GPIO_DEV_MODE;
+ gpios->gpios[2].port = 100;
gpios->gpios[2].polarity = ACTIVE_HIGH;
- gpios->gpios[2].value = get_developer_mode_switch();
- strncpy((char *)gpios->gpios[2].name,"developer", GPIO_MAX_NAME_LENGTH);
-
- gpios->gpios[3].port = 100;
- gpios->gpios[3].polarity = ACTIVE_HIGH;
- gpios->gpios[3].value = lid & 1;
- strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH);
+ gpios->gpios[2].value = lid & 1;
+ strncpy((char *)gpios->gpios[2].name,"lid", GPIO_MAX_NAME_LENGTH);
/* Power Button */
- gpios->gpios[4].port = 101;
- gpios->gpios[4].polarity = ACTIVE_LOW;
- gpios->gpios[4].value = (gen_pmcon_1 >> 9) & 1;
- strncpy((char *)gpios->gpios[4].name,"power", GPIO_MAX_NAME_LENGTH);
+ gpios->gpios[3].port = 101;
+ gpios->gpios[3].polarity = ACTIVE_LOW;
+ gpios->gpios[3].value = (gen_pmcon_1 >> 9) & 1;
+ strncpy((char *)gpios->gpios[3].name,"power", GPIO_MAX_NAME_LENGTH);
/* Did we load the VGA Option ROM? */
- gpios->gpios[5].port = -1; /* Indicate that this is a pseudo GPIO */
- gpios->gpios[5].polarity = ACTIVE_HIGH;
- gpios->gpios[5].value = gfx_get_init_done();
- strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH);
+ gpios->gpios[4].port = -1; /* Indicate that this is a pseudo GPIO */
+ gpios->gpios[4].polarity = ACTIVE_HIGH;
+ gpios->gpios[4].value = gfx_get_init_done();
+ strncpy((char *)gpios->gpios[4].name,"oprom", GPIO_MAX_NAME_LENGTH);
}
#endif
@@ -95,16 +87,6 @@ int get_write_protect_state(void)
return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1;
}
-int get_developer_mode_switch(void)
-{
-#ifdef __SIMPLE_DEVICE__
- pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
-#else
- struct device *dev = pcidev_on_root(0x1f, 2);
-#endif
- return (pci_read_config32(dev, SATA_SP) >> FLAG_DEV_MODE) & 1;
-}
-
int get_recovery_mode_switch(void)
{
#ifdef __SIMPLE_DEVICE__
@@ -130,16 +112,12 @@ void init_bootmode_straps(void)
/* Recovery: GPIO42 = CHP3_REC_MODE#, active low */
if (!get_gpio(GPIO_REC_MODE))
flags |= (1 << FLAG_REC_MODE);
- /* Developer: GPIO17 = KBC3_DVP_MODE, active high */
- if (get_gpio(GPIO_DEV_MODE))
- flags |= (1 << FLAG_DEV_MODE);
pci_write_config32(dev, SATA_SP, flags);
}
static const struct cros_gpio cros_gpios[] = {
CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME),
- CROS_GPIO_DEV_AH(GPIO_DEV_MODE, CROS_GPIO_DEVICE_NAME),
CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME),
};
diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig
index 36e28ffc6c..d17dc6842f 100644
--- a/src/mainboard/samsung/stumpy/Kconfig
+++ b/src/mainboard/samsung/stumpy/Kconfig
@@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS
select INTEL_INT15
config VBOOT
- select VBOOT_PHYSICAL_DEV_SWITCH
select VBOOT_PHYSICAL_REC_SWITCH
select VBOOT_VBNV_CMOS
diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c
index d0554447d2..295c31f49d 100644
--- a/src/mainboard/samsung/stumpy/chromeos.c
+++ b/src/mainboard/samsung/stumpy/chromeos.c
@@ -24,16 +24,14 @@
#define GPIO_SPI_WP 68
#define GPIO_REC_MODE 42
-#define GPIO_DEV_MODE 17
#define FLAG_SPI_WP 0
#define FLAG_REC_MODE 1
-#define FLAG_DEV_MODE 2
#if ENV_RAMSTAGE
#include <boot/coreboot_tables.h>
-#define GPIO_COUNT 6
+#define GPIO_COUNT 5
void fill_lb_gpios(struct lb_gpios *gpios)
{
@@ -56,29 +54,23 @@ void fill_lb_gpios(struct lb_gpios *gpios)
gpios->gpios[1].value = !get_recovery_mode_switch();
strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH);
- /* Developer: GPIO17 = KBC3_DVP_MODE */
- gpios->gpios[2].port = GPIO_DEV_MODE;
- gpios->gpios[2].polarity = ACTIVE_HIGH;
- gpios->gpios[2].value = get_developer_mode_switch();
- strncpy((char *)gpios->gpios[2].name,"developer", GPIO_MAX_NAME_LENGTH);
-
/* Hard code the lid switch GPIO to open. */
- gpios->gpios[3].port = 100;
- gpios->gpios[3].polarity = ACTIVE_HIGH;
- gpios->gpios[3].value = 1;
- strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH);
+ gpios->gpios[2].port = 100;
+ gpios->gpios[2].polarity = ACTIVE_HIGH;
+ gpios->gpios[2].value = 1;
+ strncpy((char *)gpios->gpios[2].name,"lid", GPIO_MAX_NAME_LENGTH);
/* Power Button */
- gpios->gpios[4].port = 101;
- gpios->gpios[4].polarity = ACTIVE_LOW;
- gpios->gpios[4].value = (gen_pmcon_1 >> 9) & 1;
- strncpy((char *)gpios->gpios[4].name,"power", GPIO_MAX_NAME_LENGTH);
+ gpios->gpios[3].port = 101;
+ gpios->gpios[3].polarity = ACTIVE_LOW;
+ gpios->gpios[3].value = (gen_pmcon_1 >> 9) & 1;
+ strncpy((char *)gpios->gpios[3].name,"power", GPIO_MAX_NAME_LENGTH);
/* Did we load the VGA Option ROM? */
- gpios->gpios[5].port = -1; /* Indicate that this is a pseudo GPIO */
- gpios->gpios[5].polarity = ACTIVE_HIGH;
- gpios->gpios[5].value = gfx_get_init_done();
- strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH);
+ gpios->gpios[4].port = -1; /* Indicate that this is a pseudo GPIO */
+ gpios->gpios[4].polarity = ACTIVE_HIGH;
+ gpios->gpios[4].value = gfx_get_init_done();
+ strncpy((char *)gpios->gpios[4].name,"oprom", GPIO_MAX_NAME_LENGTH);
}
#endif
@@ -92,16 +84,6 @@ int get_write_protect_state(void)
return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1;
}
-int get_developer_mode_switch(void)
-{
-#ifdef __SIMPLE_DEVICE__
- pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
-#else
- struct device *dev = pcidev_on_root(0x1f, 2);
-#endif
- return (pci_read_config32(dev, SATA_SP) >> FLAG_DEV_MODE) & 1;
-}
-
int get_recovery_mode_switch(void)
{
#ifdef __SIMPLE_DEVICE__
@@ -127,16 +109,12 @@ void init_bootmode_straps(void)
/* Recovery: GPIO42 = CHP3_REC_MODE#, active low */
if (!get_gpio(GPIO_REC_MODE))
flags |= (1 << FLAG_REC_MODE);
- /* Developer: GPIO17 = KBC3_DVP_MODE, active high */
- if (get_gpio(GPIO_DEV_MODE))
- flags |= (1 << FLAG_DEV_MODE);
pci_write_config32(dev, SATA_SP, flags);
}
static const struct cros_gpio cros_gpios[] = {
CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME),
- CROS_GPIO_DEV_AH(GPIO_DEV_MODE, CROS_GPIO_DEVICE_NAME),
CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME),
};
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 20:21:43 +0000