summaryrefslogtreecommitdiff
path: root/src/mainboard
diff options
context:
space:
mode:
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb16
-rw-r--r--src/mainboard/google/butterfly/devicetree.cb13
-rw-r--r--src/mainboard/google/link/devicetree.cb17
-rw-r--r--src/mainboard/google/parrot/devicetree.cb16
-rw-r--r--src/mainboard/google/stout/devicetree.cb17
-rw-r--r--src/mainboard/intel/dcp847ske/devicetree.cb17
-rw-r--r--src/mainboard/intel/emeraldlake2/devicetree.cb16
-rw-r--r--src/mainboard/kontron/ktqm77/devicetree.cb16
-rw-r--r--src/mainboard/lenovo/x220/variants/x220/overridetree.cb17
-rw-r--r--src/mainboard/roda/rv11/variants/rv11/devicetree.cb17
-rw-r--r--src/mainboard/roda/rv11/variants/rw11/devicetree.cb17
-rw-r--r--src/mainboard/samsung/lumpy/devicetree.cb16
-rw-r--r--src/mainboard/samsung/stumpy/devicetree.cb17
13 files changed, 210 insertions, 2 deletions
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb
index da34af3b12..2cb94213e3 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb
@@ -12,6 +12,22 @@ chip northbridge/intel/sandybridge
register "gen1_dec" = "0x000c0291"
register "gen4_dec" = "0x0000ff29"
register "pcie_port_coalesce" = "true"
+ register "usb_port_config" = "{
+ {1, 2, 0},
+ {1, 2, 0},
+ {1, 2, 1},
+ {1, 2, 1},
+ {1, 2, 2},
+ {1, 2, 2},
+ {1, 2, 3},
+ {1, 2, 3},
+ {1, 2, 4},
+ {1, 2, 4},
+ {1, 2, 6},
+ {1, 2, 5},
+ {0, 2, 5},
+ {0, 2, 6}
+ }"
device ref pcie_rp1 on end # PCIEX_16_3
device ref pcie_rp2 on end # RTL8111F
diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb
index 1e65ddb397..b8459c9009 100644
--- a/src/mainboard/google/butterfly/devicetree.cb
+++ b/src/mainboard/google/butterfly/devicetree.cb
@@ -69,6 +69,19 @@ chip northbridge/intel/sandybridge
# Enable zero-based linear PCIe root port functions
register "pcie_port_coalesce" = "true"
+ register "usb_port_config" = "{
+ {1, 0, -1}, /* P0: Right USB 3.0 #1 (no OC) */
+ {1, 0, -1}, /* P1: Right USB 3.0 #2 (no OC) */
+ {1, 0, -1}, /* P2: Camera (no OC) */
+ /* P3-P8: Empty */
+ {0, 0, -1}, {0, 0, -1}, {0, 0, -1},
+ {0, 0, -1}, {0, 0, -1}, {0, 0, -1},
+ {1, 1, -1}, /* P9: Left USB 1 (no OC) */
+ {1, 0, -1}, /* P10: Mini PCIe - WLAN / BT (no OC) */
+ /* P11-P13: Empty */
+ {0, 0, -1}, {0, 0, -1}, {0, 0, -1}
+ }"
+
device ref xhci on end # USB 3.0 Controller
device ref mei1 on end # Management Engine Interface 1
device ref mei2 off end # Management Engine Interface 2
diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb
index 88983dcfc6..f14728f643 100644
--- a/src/mainboard/google/link/devicetree.cb
+++ b/src/mainboard/google/link/devicetree.cb
@@ -65,6 +65,23 @@ chip northbridge/intel/sandybridge
# Enable zero-based linear PCIe root port functions
register "pcie_port_coalesce" = "true"
+ register "usb_port_config" = "{
+ { 0, 0, -1 }, /* P0: Empty */
+ { 1, 0, 0 }, /* P1: Left USB 1 (OC0) */
+ { 1, 0, 1 }, /* P2: Left USB 2 (OC1) */
+ { 1, 0, -1 }, /* P3: SDCARD (no OC) */
+ { 0, 0, -1 }, /* P4: Empty */
+ { 1, 0, -1 }, /* P5: WWAN (no OC) */
+ { 0, 0, -1 }, /* P6: Empty */
+ { 0, 0, -1 }, /* P7: Empty */
+ { 1, 0, -1 }, /* P8: Camera (no OC) */
+ { 1, 0, -1 }, /* P9: Bluetooth (no OC) */
+ { 0, 0, -1 }, /* P10: Empty */
+ { 0, 0, -1 }, /* P11: Empty */
+ { 0, 0, -1 }, /* P12: Empty */
+ { 0, 0, -1 }, /* P13: Empty */
+ }"
+
device ref mei1 on end # Management Engine Interface 1
device ref mei2 off end # Management Engine Interface 2
device ref me_ide_r off end # Management Engine IDE-R
diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb
index 35d312a03c..075e407862 100644
--- a/src/mainboard/google/parrot/devicetree.cb
+++ b/src/mainboard/google/parrot/devicetree.cb
@@ -56,6 +56,22 @@ chip northbridge/intel/sandybridge
register "sata_port_map" = "0x1"
+ register "usb_port_config" = "{
+ {0, 0, -1}, /* P0: Empty */
+ {1, 0, 0}, /* P1: Left USB 1 (OC0) */
+ {1, 0, 1}, /* P2: Left USB 2 (OC1) */
+ {1, 0, 1}, /* P3: Left USB 3 (OC1) */
+ {0, 0, -1}, /* P4-P7: Empty */
+ {0, 0, -1},
+ {0, 0, -1},
+ {0, 0, -1},
+ /* Empty and onboard Ports 8-13, set to un-used pin OC4 */
+ {1, 0, -1}, /* P8: MiniPCIe (WLAN) (no OC) */
+ {0, 0, -1}, /* P9: Empty */
+ {1, 0, -1}, /* P10: Camera (no OC) */
+ {0, 0, -1}, {0, 0, -1}, {0, 0, -1}
+ }"
+
# EC range is 0xFD60 (EC_IO) and 0x68/0x6C
register "gen1_dec" = "0x0004fd61"
register "gen2_dec" = "0x00040069"
diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb
index 8fd19fce58..36e8ba79f6 100644
--- a/src/mainboard/google/stout/devicetree.cb
+++ b/src/mainboard/google/stout/devicetree.cb
@@ -79,6 +79,23 @@ chip northbridge/intel/sandybridge
# Enable zero-based linear PCIe root port functions
register "pcie_port_coalesce" = "true"
+ register "usb_port_config" = "{
+ {1, 0, 0}, /* P0: USB 3.0 1 (OC0) */
+ {1, 0, 0}, /* P1: USB 3.0 2 (OC0) */
+ {0, 0, 0}, /* P2: Empty */
+ {1, 0, -1}, /* P3: Camera (no OC) */
+ {1, 0, -1}, /* P4: WLAN (no OC) */
+ {1, 0, -1}, /* P5: WWAN (no OC) */
+ {0, 0, 0}, /* P6: Empty */
+ {0, 0, 0}, /* P7: Empty */
+ {0, 0, 0}, /* P8: Empty */
+ {1, 0, 4}, /* P9: USB 2.0 (AUO4) (OC4) */
+ {0, 0, 0}, /* P10: Empty */
+ {0, 0, 0}, /* P11: Empty */
+ {0, 0, 0}, /* P12: Empty */
+ {1, 0, -1}, /* P13: Bluetooth (no OC) */
+ }"
+
device ref xhci on end # USB 3.0 Controller
device ref mei1 on end # Management Engine Interface 1
device ref mei2 off end # Management Engine Interface 2
diff --git a/src/mainboard/intel/dcp847ske/devicetree.cb b/src/mainboard/intel/dcp847ske/devicetree.cb
index f4e948f76c..8b10b6b36c 100644
--- a/src/mainboard/intel/dcp847ske/devicetree.cb
+++ b/src/mainboard/intel/dcp847ske/devicetree.cb
@@ -43,6 +43,23 @@ chip northbridge/intel/sandybridge
register "gen1_dec" = "0x00fc0a01" # SuperIO @0xa00-0xaff
+ register "usb_port_config" = "{
+ {1, 1, 0}, /* back, towards HDMI plugs */
+ {1, 1, 0}, /* back, towards power plug */
+ {1, 1, 1}, /* half-width miniPCIe */
+ {1, 1, 1}, /* full-width miniPCIe */
+ {1, 1, 2}, /* front-panel header */
+ {1, 1, 2}, /* front-panel header */
+ {1, 1, 3}, /* front connector */
+ {0, 1, 3}, /* not available x7 */
+ {0, 1, 4},
+ {0, 1, 4},
+ {0, 1, 5},
+ {0, 1, 5},
+ {0, 1, 6},
+ {0, 1, 6}
+ }"
+
device ref xhci off end # USB xHCI
device ref mei1 on end # Management Engine Interface 1
device ref mei2 off end # Management Engine Interface 2
diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb
index e75505e270..75e6daa1a3 100644
--- a/src/mainboard/intel/emeraldlake2/devicetree.cb
+++ b/src/mainboard/intel/emeraldlake2/devicetree.cb
@@ -58,6 +58,22 @@ chip northbridge/intel/sandybridge
register "gen2_dec" = "0x000c0181"
# SuperIO range is 0x700-0x73f
register "gen3_dec" = "0x003c0701"
+ register "usb_port_config" = "{
+ { 1, 0, 0 }, /* P0: Front port (OC0) */
+ { 1, 0, 1 }, /* P1: Back port (OC1) */
+ { 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */
+ { 1, 0, -1 }, /* P3: MMC (no OC) */
+ { 1, 0, 2 }, /* P4: Front port (OC2) */
+ { 0, 0, -1 }, /* P5: Empty */
+ { 0, 0, -1 }, /* P6: Empty */
+ { 0, 0, -1 }, /* P7: Empty */
+ { 1, 0, 4 }, /* P8: Back port (OC4) */
+ { 1, 0, -1 }, /* P9: MINIPCIE3 (no OC) */
+ { 1, 0, -1 }, /* P10: BLUETOOTH (no OC) */
+ { 0, 0, -1 }, /* P11: Empty */
+ { 1, 0, 6 }, /* P12: Back port (OC6) */
+ { 1, 0, 5 }, /* P13: Back port (OC5) */
+ }"
device ref mei1 on end # Management Engine Interface 1
device ref mei2 off end # Management Engine Interface 2
diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb
index a03562842c..d17d373578 100644
--- a/src/mainboard/kontron/ktqm77/devicetree.cb
+++ b/src/mainboard/kontron/ktqm77/devicetree.cb
@@ -55,6 +55,22 @@ chip northbridge/intel/sandybridge
register "xhci_switchable_ports" = "0x0f"
register "superspeed_capable_ports" = "0x0f"
+ register "usb_port_config" = "{
+ { 1, 0, 0 }, /* P0: lower left USB 3.0 (OC0) */
+ { 1, 0, 0 }, /* P1: upper left USB 3.0 (OC0) */
+ { 1, 0, 0 }, /* P2: lower right USB 3.0 (OC0) */
+ { 1, 0, 0 }, /* P3: upper right USB 3.0 (OC0) */
+ { 1, 0, 0 }, /* P4: lower USB 2.0 (OC0) */
+ { 1, 0, 0 }, /* P5: upper USB 2.0 (OC0) */
+ { 1, 0, 0 }, /* P6: front panel USB 2.0 (OC0) */
+ { 1, 0, 0 }, /* P7: front panel USB 2.0 (OC0) */
+ { 1, 0, 4 }, /* P8: internal USB 2.0 (OC4) */
+ { 1, 0, 4 }, /* P9: internal USB 2.0 (OC4) */
+ { 1, 0, 4 }, /* P10: internal USB 2.0 (OC4) */
+ { 1, 0, 4 }, /* P11: internal USB 2.0 (OC4) */
+ { 1, 0, 4 }, /* P12: internal USB 2.0 (OC4) */
+ { 1, 0, 4 }, /* P13: internal USB 2.0 (OC4) */
+ }"
device ref xhci on end # USB 3.0 Controller
device ref mei1 on end # Management Engine Interface 1
diff --git a/src/mainboard/lenovo/x220/variants/x220/overridetree.cb b/src/mainboard/lenovo/x220/variants/x220/overridetree.cb
index b9caa255de..626f7eb3a6 100644
--- a/src/mainboard/lenovo/x220/variants/x220/overridetree.cb
+++ b/src/mainboard/lenovo/x220/variants/x220/overridetree.cb
@@ -1,6 +1,23 @@
chip northbridge/intel/sandybridge
device domain 0 on
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "usb_port_config" = "{
+ {1, 0, 0 },
+ {1, 1, 1 },
+ {1, 1, 3 },
+ {1, 1, 3 },
+ {1, 1, -1},
+ {1, 1, -1},
+ {1, 0, 2 },
+ {1, 0, 2 },
+ {1, 1, 6 },
+ {1, 1, 5 },
+ {1, 1, 6 },
+ {1, 1, 6 },
+ {1, 1, 7 },
+ {1, 1, 6 },
+ }"
+
device ref lpc on
chip ec/lenovo/h8
device pnp ff.2 on end # dummy
diff --git a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb
index 9da9cb88e1..841b5dd091 100644
--- a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb
+++ b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb
@@ -69,10 +69,25 @@ chip northbridge/intel/sandybridge
register "pcie_port_coalesce" = "false"
register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
-
register "xhci_overcurrent_mapping" = "0x00080401"
register "xhci_switchable_ports" = "0x0f"
register "superspeed_capable_ports" = "0x0f"
+ register "usb_port_config" = "{
+ { 1, 0, 0 }, /* P00: 1st USB3 (OC #0) */
+ { 1, 0, 4 }, /* P01: 2nd USB3 (OC #4) */
+ { 1, 1, 1 }, /* P02: 1st Multibay USB3 (OC #1) */
+ { 1, 1, 2 }, /* P03: 2nd Multibay USB3 (OC #2) */
+ { 1, 0, 8 }, /* P04: MiniPCIe 1 USB2 (no OC) */
+ { 1, 0, 8 }, /* P05: MiniPCIe 2 USB2 (no OC) */
+ { 1, 0, 8 }, /* P06: MiniPCIe 3 USB2 (no OC) */
+ { 1, 0, 8 }, /* P07: GPS USB2 (no OC) */
+ { 1, 0, 8 }, /* P08: MiniPCIe 4 USB2 (no OC) */
+ { 1, 0, 3 }, /* P09: Express Card USB2 (OC #3) */
+ { 1, 0, 8 }, /* P10: SD card reader USB2 (no OC) */
+ { 1, 0, 8 }, /* P11: Sensors Hub? USB2 (no OC) */
+ { 1, 0, 8 }, /* P12: Touch Screen USB2 (no OC) */
+ { 1, 0, 5 }, /* P13: reserved? USB2 (OC #5) */
+ }"
register "spi_uvscc" = "0x2005"
register "spi_lvscc" = "0x2005"
diff --git a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb
index 9dae3fffa6..783cec65ba 100644
--- a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb
+++ b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb
@@ -73,10 +73,25 @@ chip northbridge/intel/sandybridge
register "pcie_port_coalesce" = "false"
register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 1, 1 }"
-
register "xhci_overcurrent_mapping" = "0x00000c03"
register "xhci_switchable_ports" = "0x0f"
register "superspeed_capable_ports" = "0x0f"
+ register "usb_port_config" = "{
+ { 1, 1, 0 }, /* P00: 1st (left) USB3 (OC #0) */
+ { 1, 1, 0 }, /* P01: 2nd (left) USB3 (OC #0) */
+ { 1, 1, 1 }, /* P02: 1st Multibay USB3 (OC #1) */
+ { 1, 1, 1 }, /* P03: 2nd Multibay USB3 (OC #1) */
+ { 1, 0, 8 }, /* P04: MiniPCIe 1 USB2 (no OC) */
+ { 1, 0, 8 }, /* P05: MiniPCIe 2 USB2 (no OC) */
+ { 1, 0, 8 }, /* P06: USB Hub x4 USB2 (no OC) */
+ { 1, 0, 8 }, /* P07: MiniPCIe 4 USB2 (no OC) */
+ { 1, 1, 8 }, /* P08: SD card reader USB2 (no OC) */
+ { 1, 1, 4 }, /* P09: 3rd (right) USB2 (OC #4) */
+ { 1, 0, 5 }, /* P10: 4th (right) USB2 (OC #5) */
+ { 1, 0, 8 }, /* P11: 3rd Multibay USB2 (no OC) */
+ { 1, 1, 8 }, /* P12: misc internal USB2 (no OC) */
+ { 1, 1, 6 }, /* P13: misc internal USB2 (OC #6) */
+ }"
register "spi_uvscc" = "0x2005"
register "spi_lvscc" = "0x2005"
diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb
index 0bf0b306da..bbfb1e68a3 100644
--- a/src/mainboard/samsung/lumpy/devicetree.cb
+++ b/src/mainboard/samsung/lumpy/devicetree.cb
@@ -56,6 +56,22 @@ chip northbridge/intel/sandybridge
register "gen1_dec" = "0x003c0a01"
register "gen2_dec" = "0x003c0b01"
register "gen3_dec" = "0x00fc1601"
+ register "usb_port_config" = "{
+ { 1, 1, 0 }, /* P0: Port 0 (OC0) */
+ { 1, 1, 1 }, /* P1: Port 1 (OC1) */
+ { 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */
+ { 1, 0, -1 }, /* P3: MMC (no OC) */
+ { 0, 0, -1 }, /* P4: Empty */
+ { 0, 0, -1 }, /* P5: Empty */
+ { 0, 0, -1 }, /* P6: Empty */
+ { 0, 0, -1 }, /* P7: Empty */
+ { 1, 0, -1 }, /* P8: MINIPCIE2 (no OC) */
+ { 0, 0, -1 }, /* P9: Empty */
+ { 0, 0, -1 }, /* P10: Empty */
+ { 1, 0, -1 }, /* P11: Camera (no OC) */
+ { 0, 0, -1 }, /* P12-13: Empty */
+ { 0, 0, -1 }
+ }"
device ref mei1 on end # Management Engine Interface 1
device ref mei2 off end # Management Engine Interface 2
diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb
index bc24464733..e158113746 100644
--- a/src/mainboard/samsung/stumpy/devicetree.cb
+++ b/src/mainboard/samsung/stumpy/devicetree.cb
@@ -54,6 +54,23 @@ chip northbridge/intel/sandybridge
# SuperIO range is 0x700-0x73f
register "gen2_dec" = "0x003c0701"
+ register "usb_port_config" = "{
+ { 1, 1, 0 }, /* P0: Front port (OC0) */
+ { 1, 0, 1 }, /* P1: Back port (OC1) */
+ { 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */
+ { 1, 0, -1 }, /* P3: MMC (no OC) */
+ { 1, 1, 2 }, /* P4: Front port (OC2) */
+ { 0, 0, -1 }, /* P5: Empty */
+ { 0, 0, -1 }, /* P6: Empty */
+ { 0, 0, -1 }, /* P7: Empty */
+ { 1, 0, 4 }, /* P8: Back port (OC4) */
+ { 1, 0, -1 }, /* P9: MINIPCIE3 (no OC) */
+ { 1, 0, -1 }, /* P10: BLUETOOTH (no OC) */
+ { 0, 0, -1 }, /* P11: Empty */
+ { 1, 0, 6 }, /* P12: Back port (OC6) */
+ { 1, 0, 5 }, /* P13: Back port (OC5) */
+ }"
+
device ref mei1 on end # Management Engine Interface 1
device ref mei2 off end # Management Engine Interface 2
device ref me_ide_r off end # Management Engine IDE-R
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-05 14:01:44 +0000