diff options
Diffstat (limited to 'src/mainboard')
40 files changed, 81 insertions, 81 deletions
diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c index 08fbdc7e4d..c595006e14 100644 --- a/src/mainboard/msi/ms7135/romstage.c +++ b/src/mainboard/msi/ms7135/romstage.c @@ -41,7 +41,7 @@ #include <spd.h> #include <northbridge/amd/amdk8/pre_f.h> -#if CONFIG_HAVE_OPTION_TABLE +#if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE) #include "option_table.h" #endif @@ -132,7 +132,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset = setup_coherent_ht_domain(); wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) // It is said that we should start core1 after all core0 launched start_other_cores(); wait_all_other_cores_started(bsp_apicid); @@ -156,7 +156,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) ms7135_set_nf4_voltage(); ms7135_set_ram_voltage(); -#if CONFIG_DEBUG_SMBUS +#if IS_ENABLED(CONFIG_DEBUG_SMBUS) dump_spd_registers(&ctrl[0]); dump_smbus_registers(); #endif diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index 6feddcfef1..5287258a18 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -144,7 +144,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_coherent_ht_domain(); /* Routing table and start other core0. */ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* It is said that we should start core1 after all core0 launched * becase optimize_link_coherent_ht is moved out from * setup_coherent_ht_domain, so here need to make sure last core0 is @@ -158,7 +158,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Set up chains and store link pair for optimization later. */ ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */ -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) { msr_t msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); diff --git a/src/mainboard/msi/ms7721/buildOpts.c b/src/mainboard/msi/ms7721/buildOpts.c index ecb168c638..5191574fef 100644 --- a/src/mainboard/msi/ms7721/buildOpts.c +++ b/src/mainboard/msi/ms7721/buildOpts.c @@ -168,7 +168,7 @@ #define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3 #define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3 -#if CONFIG_GFXUMA +#if IS_ENABLED(CONFIG_GFXUMA) #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED //#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ diff --git a/src/mainboard/msi/ms9185/mptable.c b/src/mainboard/msi/ms9185/mptable.c index 38cc72bbbc..e93602be1c 100644 --- a/src/mainboard/msi/ms9185/mptable.c +++ b/src/mainboard/msi/ms9185/mptable.c @@ -26,7 +26,7 @@ #include <device/pci.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) #include <cpu/amd/multicore.h> #endif #include <cpu/amd/amdk8_sysconf.h> diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index 56eaa6ac8b..5d031795dc 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -123,7 +123,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_coherent_ht_domain(); wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, @@ -144,7 +144,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset |= optimize_link_incoherent_ht(sysinfo); #endif -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) { msr_t msr; msr = rdmsr(0xc0010042); diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index fd9049146a..4fa40bf0ce 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -154,7 +154,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) // It is said that we should start core1 after all core0 launched start_other_cores(); //wait_all_other_cores_started(bsp_apicid); diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 4acb240548..11e9bc0492 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -178,7 +178,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -189,7 +189,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x38); -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index b80f4f37d4..9c04b1cadc 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -142,7 +142,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, @@ -155,7 +155,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) { msr_t msr; msr = rdmsr(0xc0010042); diff --git a/src/mainboard/samsung/lumpy/acpi_tables.c b/src/mainboard/samsung/lumpy/acpi_tables.c index 828546c1b1..65922f3d92 100644 --- a/src/mainboard/samsung/lumpy/acpi_tables.c +++ b/src/mainboard/samsung/lumpy/acpi_tables.c @@ -25,7 +25,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <ec/acpi/ec.h> -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) #include <vendorcode/google/chromeos/gnvs.h> #endif diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 2a4bb4c6ea..3afb196448 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -38,7 +38,7 @@ #include <cpu/x86/msr.h> #include <halt.h> #include "option_table.h" -#if CONFIG_DRIVERS_UART_8250IO +#if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO) #include <superio/smsc/lpc47n207/lpc47n207.h> #endif @@ -47,7 +47,7 @@ void pch_enable_lpc(void) /* Set COM1/COM2 decode range */ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); -#if CONFIG_DRIVERS_UART_8250IO +#if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO) /* Enable SuperIO + EC + KBC + COM1 + lpc47n207 config*/ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN); diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index c4df1e7d82..ec5368dbb0 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -38,12 +38,12 @@ #include <cpu/x86/msr.h> #include <halt.h> #include <tpm.h> -#if CONFIG_DRIVERS_UART_8250IO +#if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO) #include <superio/smsc/lpc47n207/lpc47n207.h> #endif /* Stumpy USB Reset Disable defined in cmos.layout */ -#if CONFIG_USE_OPTION_TABLE +#if IS_ENABLED(CONFIG_USE_OPTION_TABLE) #include "option_table.h" #define CMOS_USB_RESET_DISABLE (CMOS_VSTART_stumpy_usb_reset_disable >> 3) #else @@ -60,7 +60,7 @@ void pch_enable_lpc(void) /* Set COM1/COM2 decode range */ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); -#if CONFIG_DRIVERS_UART_8250IO +#if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO) /* Enable SuperIO + PS/2 Keyboard/Mouse + COM1 + lpc47n207 config*/ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN |\ CNF2_LPC_EN | COMA_LPC_EN); diff --git a/src/mainboard/siemens/mc_bdx1/mainboard.c b/src/mainboard/siemens/mc_bdx1/mainboard.c index c20778d1f1..d4d84b5599 100644 --- a/src/mainboard/siemens/mc_bdx1/mainboard.c +++ b/src/mainboard/siemens/mc_bdx1/mainboard.c @@ -22,7 +22,7 @@ #include <device/pci_ops.h> #include <device/pci_ids.h> #include <console/console.h> -#if CONFIG_VGA_ROM_RUN +#if IS_ENABLED(CONFIG_VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif #include <pc80/mc146818rtc.h> diff --git a/src/mainboard/siemens/mc_tcu3/mainboard.c b/src/mainboard/siemens/mc_tcu3/mainboard.c index a11ff266ec..df084718fb 100644 --- a/src/mainboard/siemens/mc_tcu3/mainboard.c +++ b/src/mainboard/siemens/mc_tcu3/mainboard.c @@ -21,7 +21,7 @@ #include <device/pci_def.h> #include <device/pci_ops.h> #include <console/console.h> -#if CONFIG_VGA_ROM_RUN +#if IS_ENABLED(CONFIG_VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif #include <pc80/mc146818rtc.h> diff --git a/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c b/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c index 0582566c90..30f963e729 100644 --- a/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c +++ b/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c @@ -65,7 +65,7 @@ unsigned long acpi_fill_madt(unsigned long current) /* Write SB600 IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, IO_APIC_ADDR, 0); -#if !CONFIG_LINT01_CONVERSION +#if !IS_ENABLED(CONFIG_LINT01_CONVERSION) current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); diff --git a/src/mainboard/siemens/sitemp_g1p1/mainboard.c b/src/mainboard/siemens/sitemp_g1p1/mainboard.c index 1f266a7a00..bc2c75b752 100644 --- a/src/mainboard/siemens/sitemp_g1p1/mainboard.c +++ b/src/mainboard/siemens/sitemp_g1p1/mainboard.c @@ -30,7 +30,7 @@ #include <southbridge/amd/rs690/chip.h> #include <southbridge/amd/rs690/rs690.h> #include <superio/ite/it8712f/it8712f.h> -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) #include <x86emu/x86emu.h> #endif #include "int15_func.h" @@ -215,7 +215,7 @@ struct fan_control { u8 t_range; }; /* ############################################################################################# */ -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) static int int15_handler(void) { #define BOOT_DISPLAY_DEFAULT 0 @@ -779,14 +779,14 @@ void smm_lock(void) static void mainboard_init(device_t dev) { -#if CONFIG_PCI_OPTION_ROM_RUN_REALMODE +#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) INT15_function_extensions int15_func; #endif printk(BIOS_DEBUG, "%s %s[%x/%x] %s\n", dev_name(dev), dev_path(dev), dev->subsystem_vendor, dev->subsystem_device, __func__); -#if CONFIG_PCI_OPTION_ROM_RUN_REALMODE +#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) if (get_option(&int15_func.regs.func00_LCD_panel_id, "lcd_panel_id") != CB_SUCCESS) int15_func.regs.func00_LCD_panel_id = PANEL_TABLE_ID_NO; int15_func.regs.func05_TV_standard = TV_MODE_NO; @@ -808,7 +808,7 @@ static void mainboard_enable(device_t dev) printk(BIOS_INFO, "%s %s[%x/%x] %s\n", dev_name(dev), dev_path(dev), dev->subsystem_vendor, dev->subsystem_device, __func__); -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) /* Install custom int15 handler for VGA OPROM */ mainboard_interrupt_handlers(0x15, &int15_handler); #endif diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c index 6ac79d1ab0..52d9c2381c 100644 --- a/src/mainboard/siemens/sitemp_g1p1/romstage.c +++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c @@ -117,7 +117,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_coherent_ht_domain(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* It is said that we should start core1 after all core0 launched */ wait_all_core0_started(); start_other_cores(); diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c index 13458716f7..405439fd9b 100644 --- a/src/mainboard/sunw/ultra40/romstage.c +++ b/src/mainboard/sunw/ultra40/romstage.c @@ -124,7 +124,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset = setup_coherent_ht_domain(); wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) // It is said that we should start core1 after all core0 launched start_other_cores(); wait_all_other_cores_started(bsp_apicid); diff --git a/src/mainboard/sunw/ultra40m2/romstage.c b/src/mainboard/sunw/ultra40m2/romstage.c index 44bf8519a1..9145ca540d 100644 --- a/src/mainboard/sunw/ultra40m2/romstage.c +++ b/src/mainboard/sunw/ultra40m2/romstage.c @@ -135,7 +135,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, @@ -148,7 +148,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) { msr_t msr; msr = rdmsr(0xc0010042); diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index d0ab05e027..f173d1a719 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -154,13 +154,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram -#if CONFIG_DEBUG_SMBUS +#if IS_ENABLED(CONFIG_DEBUG_SMBUS) dump_smbus_registers(); #endif setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, @@ -173,7 +173,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) { msr_t msr; msr = rdmsr(0xc0010042); diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index e4ee1c842d..3f01c92ca5 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -137,7 +137,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, @@ -150,7 +150,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) { msr_t msr; msr = rdmsr(0xc0010042); diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index d457f1bd91..e100876d5a 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -173,7 +173,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -183,7 +183,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x38); -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); diff --git a/src/mainboard/supermicro/h8qgi/buildOpts.c b/src/mainboard/supermicro/h8qgi/buildOpts.c index 4db2c6f53c..b146afe0d6 100644 --- a/src/mainboard/supermicro/h8qgi/buildOpts.c +++ b/src/mainboard/supermicro/h8qgi/buildOpts.c @@ -426,10 +426,10 @@ CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] = */ /* -#if CONFIG_CPU_AMD_AGESA_FAMILY15 +#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15) #define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE #endif -#if CONFIG_CPU_AMD_AGESA_FAMILY10 +#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY10) #define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE #endif */ diff --git a/src/mainboard/supermicro/h8qgi/rd890_cfg.h b/src/mainboard/supermicro/h8qgi/rd890_cfg.h index 35ddfbb5b5..6607094281 100644 --- a/src/mainboard/supermicro/h8qgi/rd890_cfg.h +++ b/src/mainboard/supermicro/h8qgi/rd890_cfg.h @@ -27,10 +27,10 @@ * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0. */ #ifndef DEFAULT_HT_PATH -#if CONFIG_CPU_AMD_AGESA_FAMILY10 +#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY10) #define DEFAULT_HT_PATH {0x0, 0x3} #endif -#if CONFIG_CPU_AMD_AGESA_FAMILY15 +#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15) #define DEFAULT_HT_PATH {0x0, 0x1} #endif #endif diff --git a/src/mainboard/supermicro/h8qgi/sb700_cfg.h b/src/mainboard/supermicro/h8qgi/sb700_cfg.h index a5f371dbf1..62b618f70a 100644 --- a/src/mainboard/supermicro/h8qgi/sb700_cfg.h +++ b/src/mainboard/supermicro/h8qgi/sb700_cfg.h @@ -36,13 +36,13 @@ * before AGESA module get call. */ #ifndef BIOS_SIZE -#if CONFIG_COREBOOT_ROMSIZE_KB_1024 +#if IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_1024) #define BIOS_SIZE BIOS_SIZE_1M -#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1 +#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_2048) #define BIOS_SIZE BIOS_SIZE_2M -#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1 +#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_4096) #define BIOS_SIZE BIOS_SIZE_4M -#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1 +#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_8192) #define BIOS_SIZE BIOS_SIZE_8M #endif #endif diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 26f3da710a..3554a05fce 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -239,7 +239,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -249,7 +249,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x38); -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); diff --git a/src/mainboard/supermicro/h8scm/rd890_cfg.h b/src/mainboard/supermicro/h8scm/rd890_cfg.h index 35ddfbb5b5..6607094281 100644 --- a/src/mainboard/supermicro/h8scm/rd890_cfg.h +++ b/src/mainboard/supermicro/h8scm/rd890_cfg.h @@ -27,10 +27,10 @@ * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0. */ #ifndef DEFAULT_HT_PATH -#if CONFIG_CPU_AMD_AGESA_FAMILY10 +#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY10) #define DEFAULT_HT_PATH {0x0, 0x3} #endif -#if CONFIG_CPU_AMD_AGESA_FAMILY15 +#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15) #define DEFAULT_HT_PATH {0x0, 0x1} #endif #endif diff --git a/src/mainboard/supermicro/h8scm/sb700_cfg.h b/src/mainboard/supermicro/h8scm/sb700_cfg.h index c067095d3e..62b618f70a 100644 --- a/src/mainboard/supermicro/h8scm/sb700_cfg.h +++ b/src/mainboard/supermicro/h8scm/sb700_cfg.h @@ -36,13 +36,13 @@ * before AGESA module get call. */ #ifndef BIOS_SIZE -#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1 +#if IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_1024) #define BIOS_SIZE BIOS_SIZE_1M -#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1 +#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_2048) #define BIOS_SIZE BIOS_SIZE_2M -#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1 +#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_4096) #define BIOS_SIZE BIOS_SIZE_4M -#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1 +#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_8192) #define BIOS_SIZE BIOS_SIZE_8M #endif #endif diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index 091514d91a..60288e0329 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -153,7 +153,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -167,7 +167,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sr5650_early_setup(); sb7xx_51xx_early_setup(); -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); diff --git a/src/mainboard/technexion/tim5690/mainboard.c b/src/mainboard/technexion/tim5690/mainboard.c index 8bc1075a8b..edc1170794 100644 --- a/src/mainboard/technexion/tim5690/mainboard.c +++ b/src/mainboard/technexion/tim5690/mainboard.c @@ -184,7 +184,7 @@ static void mb_gpio_init(u16 *iobase) it8712f_exit_conf(); } -#if CONFIG_VGA_ROM_RUN +#if IS_ENABLED(CONFIG_VGA_ROM_RUN) /* The LCD's panel id seletion. */ static void lcd_panel_id(rs690_vbios_regs *vbios_regs, u8 num_id) { @@ -221,7 +221,7 @@ static void lcd_panel_id(rs690_vbios_regs *vbios_regs, u8 num_id) static void mainboard_enable(device_t dev) { u16 gpio_base = IT8712F_SIMPLE_IO_BASE; -#if CONFIG_VGA_ROM_RUN +#if IS_ENABLED(CONFIG_VGA_ROM_RUN) rs690_vbios_regs vbios_regs; u8 port2; #endif @@ -230,7 +230,7 @@ static void mainboard_enable(device_t dev) mb_gpio_init(&gpio_base); -#if CONFIG_VGA_ROM_RUN +#if IS_ENABLED(CONFIG_VGA_ROM_RUN) /* The LCD's panel id seletion by switch. */ port2 = inb(gpio_base+1); lcd_panel_id(&vbios_regs, ((~port2) & 0xf)); diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c index 3b4b4fd656..744ea67921 100644 --- a/src/mainboard/technexion/tim5690/romstage.c +++ b/src/mainboard/technexion/tim5690/romstage.c @@ -95,7 +95,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_coherent_ht_domain(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* It is said that we should start core1 after all core0 launched */ wait_all_core0_started(); start_other_cores(); diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c index 60308649dd..18e3140b11 100644 --- a/src/mainboard/technexion/tim8690/romstage.c +++ b/src/mainboard/technexion/tim8690/romstage.c @@ -91,7 +91,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_coherent_ht_domain(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* It is said that we should start core1 after all core0 launched */ wait_all_core0_started(); start_other_cores(); diff --git a/src/mainboard/thomson/ip1000/spd_table.h b/src/mainboard/thomson/ip1000/spd_table.h index 0ecf1c0083..1de05edce1 100644 --- a/src/mainboard/thomson/ip1000/spd_table.h +++ b/src/mainboard/thomson/ip1000/spd_table.h @@ -16,11 +16,11 @@ #include <spd.h> -#if CONFIG_ONBOARD_MEMORY_64MB +#if IS_ENABLED(CONFIG_ONBOARD_MEMORY_64MB) #define DENSITY 0x10 -#elif CONFIG_ONBOARD_MEMORY_128MB +#elif IS_ENABLED(CONFIG_ONBOARD_MEMORY_128MB) #define DENSITY 0x20 diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c index 6a47612dbe..89f3175c25 100644 --- a/src/mainboard/tyan/s2912/romstage.c +++ b/src/mainboard/tyan/s2912/romstage.c @@ -140,7 +140,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, @@ -153,7 +153,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) { msr_t msr; msr = rdmsr(0xc0010042); diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 4c8c19f665..b449f77731 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -174,7 +174,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -184,7 +184,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x38); -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); diff --git a/src/mainboard/tyan/s8226/buildOpts.c b/src/mainboard/tyan/s8226/buildOpts.c index 13128920b9..e27ec163ee 100644 --- a/src/mainboard/tyan/s8226/buildOpts.c +++ b/src/mainboard/tyan/s8226/buildOpts.c @@ -426,10 +426,10 @@ CONST AP_MTRR_SETTINGS ROMDATA s8226_ap_mtrr_list[] = */ /* -#if CONFIG_CPU_AMD_AGESA_FAMILY15 +#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15) #define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE #endif -#if CONFIG_CPU_AMD_AGESA_FAMILY10 +#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY10) #define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE #endif */ diff --git a/src/mainboard/tyan/s8226/rd890_cfg.h b/src/mainboard/tyan/s8226/rd890_cfg.h index 35ddfbb5b5..6607094281 100644 --- a/src/mainboard/tyan/s8226/rd890_cfg.h +++ b/src/mainboard/tyan/s8226/rd890_cfg.h @@ -27,10 +27,10 @@ * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0. */ #ifndef DEFAULT_HT_PATH -#if CONFIG_CPU_AMD_AGESA_FAMILY10 +#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY10) #define DEFAULT_HT_PATH {0x0, 0x3} #endif -#if CONFIG_CPU_AMD_AGESA_FAMILY15 +#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15) #define DEFAULT_HT_PATH {0x0, 0x1} #endif #endif diff --git a/src/mainboard/tyan/s8226/sb700_cfg.h b/src/mainboard/tyan/s8226/sb700_cfg.h index 3f82931684..bed9161f29 100644 --- a/src/mainboard/tyan/s8226/sb700_cfg.h +++ b/src/mainboard/tyan/s8226/sb700_cfg.h @@ -36,13 +36,13 @@ * before AGESA module get call. */ #ifndef BIOS_SIZE -#if CONFIG_COREBOOT_ROMSIZE_KB_1024 +#if IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_1024) #define BIOS_SIZE BIOS_SIZE_1M -#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 +#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_2048) #define BIOS_SIZE BIOS_SIZE_2M -#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 +#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_4096) #define BIOS_SIZE BIOS_SIZE_4M -#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 +#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_8192) #define BIOS_SIZE BIOS_SIZE_8M #endif #endif diff --git a/src/mainboard/via/epia-m850/mainboard.c b/src/mainboard/via/epia-m850/mainboard.c index 335e86bdac..68c49bc237 100644 --- a/src/mainboard/via/epia-m850/mainboard.c +++ b/src/mainboard/via/epia-m850/mainboard.c @@ -19,7 +19,7 @@ #include <device/pci_ops.h> #include <console/console.h> -#if CONFIG_VGA_ROM_RUN +#if IS_ENABLED(CONFIG_VGA_ROM_RUN) #include <arch/interrupt.h> #include <x86emu/x86emu.h> @@ -96,7 +96,7 @@ static void mainboard_enable(device_t dev) { (void)dev; -#if CONFIG_VGA_ROM_RUN +#if IS_ENABLED(CONFIG_VGA_ROM_RUN) printk(BIOS_DEBUG, "Installing INT15 handler...\n"); mainboard_interrupt_handlers(0x15, &vx900_int15_handler); #endif diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c index 450f7d7a63..a79d419a39 100644 --- a/src/mainboard/via/epia-m850/romstage.c +++ b/src/mainboard/via/epia-m850/romstage.c @@ -90,7 +90,7 @@ void main(unsigned long bist) printk(BIOS_DEBUG, "We passed RAM verify\n"); /* We got RAM working, now we can write the timestamps to RAM */ -#if CONFIG_EARLY_CBMEM_INIT +#if IS_ENABLED(CONFIG_EARLY_CBMEM_INIT) cbmem_recovery(0); #endif /* FIXME: See if this is needed or take this out please */ diff --git a/src/mainboard/winent/mb6047/romstage.c b/src/mainboard/winent/mb6047/romstage.c index 09de180972..ddce5c6954 100644 --- a/src/mainboard/winent/mb6047/romstage.c +++ b/src/mainboard/winent/mb6047/romstage.c @@ -37,7 +37,7 @@ int spd_read_byte(unsigned device, unsigned address) #include <southbridge/nvidia/ck804/early_setup_ss.h> #include "southbridge/nvidia/ck804/early_setup_car.c" #include "cpu/amd/model_fxx/init_cpus.c" -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) #include "cpu/amd/model_fxx/fidvid.c" #endif #include "northbridge/amd/amdk8/early_ht.c" @@ -100,7 +100,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) start_other_cores(); wait_all_other_cores_started(bsp_apicid); -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) /* Check to see if processor is capable of changing FIDVID */ /* otherwise it will throw a GP# when reading FIDVID_STATUS */ if ((cpuid_edx(0x80000007) & 0x6) == 0x6) { |