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-rw-r--r--src/mainboard/amd/inagua/buildOpts.c18
-rw-r--r--src/mainboard/amd/persimmon/buildOpts.c18
-rw-r--r--src/mainboard/amd/south_station/buildOpts.c18
-rw-r--r--src/mainboard/amd/union_station/buildOpts.c18
-rw-r--r--src/mainboard/asrock/e350m1/buildOpts.c18
-rw-r--r--src/mainboard/elmex/pcm205400/buildOpts.c18
-rw-r--r--src/mainboard/gizmosphere/gizmo/buildOpts.c18
-rw-r--r--src/mainboard/jetway/nf81-t56n-lf/buildOpts.c18
-rw-r--r--src/mainboard/lippert/frontrunner-af/buildOpts.c18
-rw-r--r--src/mainboard/lippert/toucan-af/buildOpts.c18
-rw-r--r--src/mainboard/pcengines/apu1/buildOpts.c18
11 files changed, 0 insertions, 198 deletions
diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c
index c40ed43619..781dde3cc7 100644
--- a/src/mainboard/amd/inagua/buildOpts.c
+++ b/src/mainboard/amd/inagua/buildOpts.c
@@ -83,7 +83,6 @@
#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840
//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto
#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
-#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList
#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
//#define BLDCFG_STARTING_BUSNUM 0
//#define BLDCFG_MAXIMUM_BUSNUM 0xf8
@@ -157,23 +156,6 @@
*/
#include <AGESA.h>
-/* The fixed MTRR values to be set after memory initialization. */
-CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
-{
- { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
- { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
- { CPU_LIST_TERMINAL }
-};
-
/* Include the files that instantiate the configuration definitions. */
#include "cpuRegisters.h"
diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c
index 02b248fa7e..cda2d9d461 100644
--- a/src/mainboard/amd/persimmon/buildOpts.c
+++ b/src/mainboard/amd/persimmon/buildOpts.c
@@ -83,7 +83,6 @@
#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840
//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto
#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
-#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList
#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
//#define BLDCFG_STARTING_BUSNUM 0
//#define BLDCFG_MAXIMUM_BUSNUM 0xf8
@@ -157,23 +156,6 @@
*/
#include <AGESA.h>
-/* The fixed MTRR values to be set after memory initialization. */
-CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
-{
- { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
- { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
- { CPU_LIST_TERMINAL }
-};
-
/* Include the files that instantiate the configuration definitions. */
#include "cpuRegisters.h"
diff --git a/src/mainboard/amd/south_station/buildOpts.c b/src/mainboard/amd/south_station/buildOpts.c
index 1d6e6590c9..8bddb38abd 100644
--- a/src/mainboard/amd/south_station/buildOpts.c
+++ b/src/mainboard/amd/south_station/buildOpts.c
@@ -83,7 +83,6 @@
#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840
//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto
#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
-#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList
#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
//#define BLDCFG_STARTING_BUSNUM 0
//#define BLDCFG_MAXIMUM_BUSNUM 0xf8
@@ -157,23 +156,6 @@
*/
#include <AGESA.h>
-/* The fixed MTRR values to be set after memory initialization. */
-CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
-{
- { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
- { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
- { CPU_LIST_TERMINAL }
-};
-
/* Include the files that instantiate the configuration definitions. */
#include "cpuRegisters.h"
diff --git a/src/mainboard/amd/union_station/buildOpts.c b/src/mainboard/amd/union_station/buildOpts.c
index 1d6e6590c9..8bddb38abd 100644
--- a/src/mainboard/amd/union_station/buildOpts.c
+++ b/src/mainboard/amd/union_station/buildOpts.c
@@ -83,7 +83,6 @@
#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840
//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto
#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
-#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList
#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
//#define BLDCFG_STARTING_BUSNUM 0
//#define BLDCFG_MAXIMUM_BUSNUM 0xf8
@@ -157,23 +156,6 @@
*/
#include <AGESA.h>
-/* The fixed MTRR values to be set after memory initialization. */
-CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
-{
- { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
- { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
- { CPU_LIST_TERMINAL }
-};
-
/* Include the files that instantiate the configuration definitions. */
#include "cpuRegisters.h"
diff --git a/src/mainboard/asrock/e350m1/buildOpts.c b/src/mainboard/asrock/e350m1/buildOpts.c
index 5583a8b118..1e2ebb07f1 100644
--- a/src/mainboard/asrock/e350m1/buildOpts.c
+++ b/src/mainboard/asrock/e350m1/buildOpts.c
@@ -62,23 +62,6 @@
* needed by the system.
*/
-/* The fixed MTRR values to be set after memory initialization. */
-CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
-{
- { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
- { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
- { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
- { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1E },
- { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1E },
- { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1E },
- { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1E },
- { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1E },
- { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1E },
- { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1E },
- { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1E },
- { CPU_LIST_TERMINAL }
-};
-
#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
@@ -108,7 +91,6 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840
//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto
#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
-#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList
#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
//#define BLDCFG_STARTING_BUSNUM 0
//#define BLDCFG_MAXIMUM_BUSNUM 0xf8
diff --git a/src/mainboard/elmex/pcm205400/buildOpts.c b/src/mainboard/elmex/pcm205400/buildOpts.c
index ebbf9c7275..bbc8f00b68 100644
--- a/src/mainboard/elmex/pcm205400/buildOpts.c
+++ b/src/mainboard/elmex/pcm205400/buildOpts.c
@@ -83,7 +83,6 @@
#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840
//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto
#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
-#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList
#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
//#define BLDCFG_STARTING_BUSNUM 0
//#define BLDCFG_MAXIMUM_BUSNUM 0xf8
@@ -157,23 +156,6 @@
*/
#include <AGESA.h>
-/* The fixed MTRR values to be set after memory initialization. */
-CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
-{
- { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
- { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
- { CPU_LIST_TERMINAL }
-};
-
/* Include the files that instantiate the configuration definitions. */
#include "cpuRegisters.h"
diff --git a/src/mainboard/gizmosphere/gizmo/buildOpts.c b/src/mainboard/gizmosphere/gizmo/buildOpts.c
index 02b248fa7e..cda2d9d461 100644
--- a/src/mainboard/gizmosphere/gizmo/buildOpts.c
+++ b/src/mainboard/gizmosphere/gizmo/buildOpts.c
@@ -83,7 +83,6 @@
#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840
//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto
#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
-#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList
#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
//#define BLDCFG_STARTING_BUSNUM 0
//#define BLDCFG_MAXIMUM_BUSNUM 0xf8
@@ -157,23 +156,6 @@
*/
#include <AGESA.h>
-/* The fixed MTRR values to be set after memory initialization. */
-CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
-{
- { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
- { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
- { CPU_LIST_TERMINAL }
-};
-
/* Include the files that instantiate the configuration definitions. */
#include "cpuRegisters.h"
diff --git a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
index 39d9d7e28b..02a416a8c1 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
@@ -97,7 +97,6 @@
#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840
//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto
#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
-#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList
#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
//#define BLDCFG_STARTING_BUSNUM 0
//#define BLDCFG_MAXIMUM_BUSNUM 0xf8
@@ -170,23 +169,6 @@
* needed by the system.
*/
-/* The fixed MTRR values to be set after memory initialization. */
-const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
-{
- { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
- { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
- { CPU_LIST_TERMINAL }
-};
-
/* MEMORY_BUS_SPEED */
#define DDR400_FREQUENCY 200 /**< DDR 400 */
#define DDR533_FREQUENCY 266 /**< DDR 533 */
diff --git a/src/mainboard/lippert/frontrunner-af/buildOpts.c b/src/mainboard/lippert/frontrunner-af/buildOpts.c
index 02b248fa7e..cda2d9d461 100644
--- a/src/mainboard/lippert/frontrunner-af/buildOpts.c
+++ b/src/mainboard/lippert/frontrunner-af/buildOpts.c
@@ -83,7 +83,6 @@
#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840
//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto
#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
-#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList
#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
//#define BLDCFG_STARTING_BUSNUM 0
//#define BLDCFG_MAXIMUM_BUSNUM 0xf8
@@ -157,23 +156,6 @@
*/
#include <AGESA.h>
-/* The fixed MTRR values to be set after memory initialization. */
-CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
-{
- { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
- { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
- { CPU_LIST_TERMINAL }
-};
-
/* Include the files that instantiate the configuration definitions. */
#include "cpuRegisters.h"
diff --git a/src/mainboard/lippert/toucan-af/buildOpts.c b/src/mainboard/lippert/toucan-af/buildOpts.c
index 02b248fa7e..cda2d9d461 100644
--- a/src/mainboard/lippert/toucan-af/buildOpts.c
+++ b/src/mainboard/lippert/toucan-af/buildOpts.c
@@ -83,7 +83,6 @@
#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840
//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto
#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
-#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList
#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
//#define BLDCFG_STARTING_BUSNUM 0
//#define BLDCFG_MAXIMUM_BUSNUM 0xf8
@@ -157,23 +156,6 @@
*/
#include <AGESA.h>
-/* The fixed MTRR values to be set after memory initialization. */
-CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
-{
- { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
- { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
- { CPU_LIST_TERMINAL }
-};
-
/* Include the files that instantiate the configuration definitions. */
#include "cpuRegisters.h"
diff --git a/src/mainboard/pcengines/apu1/buildOpts.c b/src/mainboard/pcengines/apu1/buildOpts.c
index 4780c33304..5f9272086a 100644
--- a/src/mainboard/pcengines/apu1/buildOpts.c
+++ b/src/mainboard/pcengines/apu1/buildOpts.c
@@ -83,7 +83,6 @@
#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840
//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto
#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
-#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList
#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
//#define BLDCFG_STARTING_BUSNUM 0
//#define BLDCFG_MAXIMUM_BUSNUM 0xf8
@@ -157,23 +156,6 @@
*/
#include <AGESA.h>
-/* The fixed MTRR values to be set after memory initialization. */
-CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
-{
- { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
- { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
- { CPU_LIST_TERMINAL }
-};
-
/* Include the files that instantiate the configuration definitions. */
#include "cpuRegisters.h"
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 22:34:16 +0000