diff options
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/emulation/qemu-i440fx/Kconfig | 12 | ||||
| -rw-r--r-- | src/mainboard/emulation/qemu-i440fx/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc | 64 | ||||
| -rw-r--r-- | src/mainboard/emulation/qemu-i440fx/romstage.c | 22 | ||||
| -rw-r--r-- | src/mainboard/emulation/qemu-q35/Kconfig | 12 | ||||
| -rw-r--r-- | src/mainboard/emulation/qemu-q35/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/mainboard/emulation/qemu-q35/bootblock.c | 26 | ||||
| -rw-r--r-- | src/mainboard/emulation/qemu-q35/romstage.c | 24 |
8 files changed, 57 insertions, 106 deletions
diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index fc56ab6fa3..2435729ced 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_256 select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT + select BOOTBLOCK_CONSOLE config MAINBOARD_DIR string @@ -25,12 +26,19 @@ config IRQ_SLOT_COUNT int default 6 +# Skip the first 64KiB as coreboot table pointer is installed +# at address 0 config DCACHE_RAM_BASE hex - default 0xd0000 + default 0x10000 +# Memory at 0xa0000 decodes to VGA config DCACHE_RAM_SIZE hex - default 0x10000 + default 0x90000 + +config C_ENV_BOOTBLOCK_SIZE + hex + default 0x4000 endif # BOARD_EMULATION_QEMU_X86_I440FX diff --git a/src/mainboard/emulation/qemu-i440fx/Makefile.inc b/src/mainboard/emulation/qemu-i440fx/Makefile.inc index ecc049ea5c..9e2880a6a0 100644 --- a/src/mainboard/emulation/qemu-i440fx/Makefile.inc +++ b/src/mainboard/emulation/qemu-i440fx/Makefile.inc @@ -1,4 +1,3 @@ -cpu_incs-y += $(src)/mainboard/emulation/qemu-i440fx/cache_as_ram.inc ramstage-y += northbridge.c ramstage-y += fw_cfg.c romstage-y += memory.c diff --git a/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc b/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc deleted file mode 100644 index d36341c78b..0000000000 --- a/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com> - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cpu/x86/mtrr.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/post_code.h> - -#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1) - - /* Save the BIST result. */ - movl %eax, %ebp - -cache_as_ram: - post_code(0x20) - /* - * Nothing to do here on qemu, RAM works just fine without any - * initialization. - */ - - post_code(0x21) - /* - * Set up the stack pointer, use top of real mode (640k) memory. - * This value also keeps the copy_and_run stack out of the way - * of big ramstages. The ramstage will load its own %esp so - * there is no harm in using this value. - */ - movl $0xa0000, %eax - movl %eax, %esp - - /* Restore the BIST result. */ - movl %ebp, %eax - movl %esp, %ebp - pushl %eax - -before_romstage: - post_code(0x29) - /* Call romstage.c main function. */ - call romstage_main - - post_code(0x30) - -__main: - post_code(POST_PREPARE_RAMSTAGE) - cld /* Clear direction flag. */ - - call copy_and_run - -.Lhlt: - post_code(POST_DEAD_CODE) - hlt - jmp .Lhlt diff --git a/src/mainboard/emulation/qemu-i440fx/romstage.c b/src/mainboard/emulation/qemu-i440fx/romstage.c index 953062163d..e31394c282 100644 --- a/src/mainboard/emulation/qemu-i440fx/romstage.c +++ b/src/mainboard/emulation/qemu-i440fx/romstage.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2004 Stefan Reinauer + * Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,30 +17,17 @@ #include <stdint.h> #include <cbmem.h> #include <console/console.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <timestamp.h> -#include <delay.h> -#include <cpu/x86/lapic.h> +#include <program_loading.h> - -void *asmlinkage romstage_main(unsigned long bist) +asmlinkage void car_stage_entry(void) { - int cbmem_was_initted; - - /* init_timer(); */ - post_code(0x05); - console_init(); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - cbmem_was_initted = !cbmem_recovery(0); + cbmem_recovery(0); - timestamp_init(timestamp_get()); timestamp_add_now(TS_START_ROMSTAGE); - /* Emulation uses fixed low stack during ramstage. */ - return NULL; + run_ramstage(); } diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index 10b5a936c4..4394530fad 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_2048 select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT + select BOOTBLOCK_CONSOLE config MAINBOARD_DIR string @@ -28,17 +29,24 @@ config MMCONF_BASE_ADDRESS hex default 0xb0000000 +# Skip the first 64KiB as coreboot table pointer is installed +# at address 0 config DCACHE_RAM_BASE hex - default 0xd0000 + default 0x10000 +# Memory at 0xa0000 decodes to VGA config DCACHE_RAM_SIZE hex - default 0x10000 + default 0x90000 # Do not show IFD/blob options since QEMU doesn't care config HAVE_INTEL_FIRMWARE bool default n +config C_ENV_BOOTBLOCK_SIZE + hex + default 0x4000 + endif # BOARD_EMULATION_QEMU_X86_Q35 diff --git a/src/mainboard/emulation/qemu-q35/Makefile.inc b/src/mainboard/emulation/qemu-q35/Makefile.inc index 923a28ed34..1503220c9c 100644 --- a/src/mainboard/emulation/qemu-q35/Makefile.inc +++ b/src/mainboard/emulation/qemu-q35/Makefile.inc @@ -1,5 +1,5 @@ -cpu_incs-y += $(src)/mainboard/emulation/qemu-i440fx/cache_as_ram.inc ramstage-y += ../qemu-i440fx/northbridge.c ramstage-y += ../qemu-i440fx/memory.c ramstage-y += ../qemu-i440fx/fw_cfg.c romstage-y += ../qemu-i440fx/memory.c +bootblock-y += bootblock.c diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c index 3625cf903a..2125bd1db3 100644 --- a/src/mainboard/emulation/qemu-q35/bootblock.c +++ b/src/mainboard/emulation/qemu-q35/bootblock.c @@ -12,6 +12,8 @@ */ #include <arch/io.h> +#include <bootblock_common.h> +#include <southbridge/intel/i82801ix/i82801ix.h> /* Just define these here, there is no gm35.h file to include. */ #define D0F0_PCIEXBAR_LO 0x60 @@ -39,7 +41,29 @@ static void bootblock_northbridge_init(void) pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_LO, reg); } -static void bootblock_mainboard_init(void) +static void enable_spi_prefetch(void) +{ + u8 reg8; + pci_devfn_t dev; + + dev = PCI_DEV(0, 0x1f, 0); + + reg8 = pci_read_config8(dev, 0xdc); + reg8 &= ~(3 << 2); + reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ + pci_write_config8(dev, 0xdc, reg8); +} + +static void bootblock_southbridge_init(void) +{ + enable_spi_prefetch(); + + /* Enable RCBA */ + pci_write_config32(PCI_DEV(0, 0x1f, 0), D31F0_RCBA, + (uintptr_t)DEFAULT_RCBA | 1); +} + +void bootblock_soc_init(void) { bootblock_northbridge_init(); bootblock_southbridge_init(); diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c index deb94af777..2b8d9351c0 100644 --- a/src/mainboard/emulation/qemu-q35/romstage.c +++ b/src/mainboard/emulation/qemu-q35/romstage.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2004 Stefan Reinauer + * Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,32 +17,19 @@ #include <stdint.h> #include <cbmem.h> #include <console/console.h> -#include <southbridge/intel/i82801ix/i82801ix.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <timestamp.h> -#include <delay.h> -#include <cpu/x86/lapic.h> - +#include <southbridge/intel/i82801ix/i82801ix.h> +#include <program_loading.h> -void * asmlinkage romstage_main(unsigned long bist) +asmlinkage void car_stage_entry(void) { - int cbmem_was_initted; - - /* init_timer(); */ - post_code(0x05); - i82801ix_early_init(); console_init(); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - cbmem_was_initted = !cbmem_recovery(0); + cbmem_recovery(0); - timestamp_init(timestamp_get()); timestamp_add_now(TS_START_ROMSTAGE); - /* Emulation uses fixed low stack during ramstage. */ - return NULL; + run_ramstage(); } |