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-rw-r--r--src/mainboard/apple/macbook21/romstage.c4
-rw-r--r--src/mainboard/cubietech/cubieboard/devicetree.cb2
-rw-r--r--src/mainboard/google/cosmos/chromeos.c2
-rw-r--r--src/mainboard/google/parrot/ec.h4
-rw-r--r--src/mainboard/google/purin/chromeos.c2
-rw-r--r--src/mainboard/google/stout/ec.c4
-rw-r--r--src/mainboard/google/stout/mainboard_smi.c4
-rw-r--r--src/mainboard/google/veyron/chromeos.c2
-rw-r--r--src/mainboard/google/veyron_rialto/chromeos.c2
-rw-r--r--src/mainboard/siemens/sitemp_g1p1/mainboard.c2
-rw-r--r--src/mainboard/technexion/tim5690/mainboard.c2
-rw-r--r--src/mainboard/via/epia-m700/romstage.c2
12 files changed, 16 insertions, 16 deletions
diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c
index 296f8986b3..4d49e89326 100644
--- a/src/mainboard/apple/macbook21/romstage.c
+++ b/src/mainboard/apple/macbook21/romstage.c
@@ -85,8 +85,8 @@ static void ich7_enable_lpc(void)
// Macbook21: 0x0010 == 00000000 00010000
// Bit 9:8 LPT Decode Range. This field determines which range to
// decode for the LPT Port.
- // 00 = 378h ­ 37Fh and 778h ­ 77Fh
- // 10 = 3BCh ­ 3BEh and 7BCh ­ 7BEh
+ // 00 = 378h - 37Fh and 778h - 77Fh
+ // 10 = 3BCh - 3BEh and 7BCh - 7BEh
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
// LPC_EN--LPC I/F Enables Register
diff --git a/src/mainboard/cubietech/cubieboard/devicetree.cb b/src/mainboard/cubietech/cubieboard/devicetree.cb
index 65ea5ff38c..033a89e628 100644
--- a/src/mainboard/cubietech/cubieboard/devicetree.cb
+++ b/src/mainboard/cubietech/cubieboard/devicetree.cb
@@ -1,7 +1,7 @@
chip cpu/allwinner/a10
device cpu_cluster 0 on end
- chip drivers/xpowers/axp209 # AXP209 is on I²C 0
+ chip drivers/xpowers/axp209 # AXP209 is on I2C 0
device i2c 0x34 on end
register "dcdc2_voltage_mv" = "1400" # Vcore
register "dcdc3_voltage_mv" = "1250" # DLL Vdd
diff --git a/src/mainboard/google/cosmos/chromeos.c b/src/mainboard/google/cosmos/chromeos.c
index ca80432a93..a405cf0220 100644
--- a/src/mainboard/google/cosmos/chromeos.c
+++ b/src/mainboard/google/cosmos/chromeos.c
@@ -1,4 +1,4 @@
-/*
+/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
diff --git a/src/mainboard/google/parrot/ec.h b/src/mainboard/google/parrot/ec.h
index 200750a0e9..e389a77602 100644
--- a/src/mainboard/google/parrot/ec.h
+++ b/src/mainboard/google/parrot/ec.h
@@ -49,8 +49,8 @@
* AC power plug-out C8h
* Modem Ring In CAh
* PME signal active CEh
- * Acer Hotkey Function – Make event D5h
- * Acer Hotkey Function – Break event D6h
+ * Acer Hotkey Function - Make event D5h
+ * Acer Hotkey Function - Break event D6h
*/
#ifndef __ACPI__
diff --git a/src/mainboard/google/purin/chromeos.c b/src/mainboard/google/purin/chromeos.c
index 0bd489a1e8..e6843a1489 100644
--- a/src/mainboard/google/purin/chromeos.c
+++ b/src/mainboard/google/purin/chromeos.c
@@ -1,4 +1,4 @@
-/*
+/*
* This file is part of the coreboot project.
*
* Copyright 2015 Google Inc.
diff --git a/src/mainboard/google/stout/ec.c b/src/mainboard/google/stout/ec.c
index 004c492ed9..a7006d9d64 100644
--- a/src/mainboard/google/stout/ec.c
+++ b/src/mainboard/google/stout/ec.c
@@ -48,10 +48,10 @@ void stout_ec_init(void)
* Set USB Power off in S3 (enabled in S3 path if requested in gnvs)
* Bit0 of 0x0D/Bit0 of 0x26
* 0/0 All USB port off
- * 1/0 USB on, all USB port didn’t support wake up
+ * 1/0 USB on, all USB port didn't support wake up
* 0/1 USB on, yellow port support wake up charge, but may not support
* charge smart phone.
- * 1/1 USB on, yellow port in AUTO mode and didn’t support wake up system.
+ * 1/1 USB on, yellow port in AUTO mode and didn't support wake up system.
*/
ec_write(EC_PERIPH_CNTL_3, ec_read(EC_PERIPH_CNTL_3) & 0xE);
ec_write(EC_USB_S3_EN, ec_read(EC_USB_S3_EN) & 0xE);
diff --git a/src/mainboard/google/stout/mainboard_smi.c b/src/mainboard/google/stout/mainboard_smi.c
index 7fed9cf964..e25c576ba1 100644
--- a/src/mainboard/google/stout/mainboard_smi.c
+++ b/src/mainboard/google/stout/mainboard_smi.c
@@ -58,10 +58,10 @@ void mainboard_smi_sleep(u8 slp_typ)
* Tell the EC to Enable USB power for S3 if requested.
* Bit0 of 0x0D/Bit0 of 0x26
* 0/0 All USB port off
- * 1/0 USB on, all USB port didn’t support wake up
+ * 1/0 USB on, all USB port didn't support wake up
* 0/1 USB on, yellow port support wake up charge, but may not support
* charge smart phone.
- * 1/1 USB on, yellow port in AUTO mode and didn’t support wake up system.
+ * 1/1 USB on, yellow port in AUTO mode and didn't support wake up system.
*/
if (smm_get_gnvs()->s3u0 != 0 || smm_get_gnvs()->s3u1 != 0) {
ec_write(EC_PERIPH_CNTL_3, ec_read(EC_PERIPH_CNTL_3) | 0x00);
diff --git a/src/mainboard/google/veyron/chromeos.c b/src/mainboard/google/veyron/chromeos.c
index 42be8ca5ff..b73062295a 100644
--- a/src/mainboard/google/veyron/chromeos.c
+++ b/src/mainboard/google/veyron/chromeos.c
@@ -1,4 +1,4 @@
-/*
+/*
* This file is part of the coreboot project.
*
* Copyright 2014 Rockchip Inc.
diff --git a/src/mainboard/google/veyron_rialto/chromeos.c b/src/mainboard/google/veyron_rialto/chromeos.c
index 74f84d4525..ac1afd9911 100644
--- a/src/mainboard/google/veyron_rialto/chromeos.c
+++ b/src/mainboard/google/veyron_rialto/chromeos.c
@@ -1,4 +1,4 @@
-/*
+/*
* This file is part of the coreboot project.
*
* Copyright 2014 Rockchip Inc.
diff --git a/src/mainboard/siemens/sitemp_g1p1/mainboard.c b/src/mainboard/siemens/sitemp_g1p1/mainboard.c
index f01420f928..41811e4e87 100644
--- a/src/mainboard/siemens/sitemp_g1p1/mainboard.c
+++ b/src/mainboard/siemens/sitemp_g1p1/mainboard.c
@@ -49,7 +49,7 @@
#define PANEL_TABLE_ID8 8 // 1280x1024_108MHz
#define PANEL_TABLE_ID9 9 // 1366x768_86MHz_chimei_V32B1L01
-// Callback Sub-Function 05h – Select Boot-up TV Standard
+// Callback Sub-Function 05h - Select Boot-up TV Standard
#define TV_MODE_00 0x00 /* NTSC */
#define TV_MODE_01 0x01 /* PAL */
#define TV_MODE_02 0x02 /* PALM */
diff --git a/src/mainboard/technexion/tim5690/mainboard.c b/src/mainboard/technexion/tim5690/mainboard.c
index 0362b90c1a..f84b7a0083 100644
--- a/src/mainboard/technexion/tim5690/mainboard.c
+++ b/src/mainboard/technexion/tim5690/mainboard.c
@@ -40,7 +40,7 @@
#define LCD_PANEL_ID_04 0x04 /* 1680x1050, 24 bits, 2 channels */
#define LCD_PANEL_ID_05 0x05 /* 1920x1200, 24 bits, 2 channels */
#define LCD_PANEL_ID_06 0x06 /* 1920x1080, 24 bits, 2 channels */
-//Callback Sub-Function 05h – Select Boot-up TV Standard
+//Callback Sub-Function 05h - Select Boot-up TV Standard
#define TV_MODE_00 0x00 /* NTSC */
#define TV_MODE_01 0x01 /* PAL */
#define TV_MODE_02 0x02 /* PALM */
diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c
index 9f2c14e3bf..83af4260f2 100644
--- a/src/mainboard/via/epia-m700/romstage.c
+++ b/src/mainboard/via/epia-m700/romstage.c
@@ -187,7 +187,7 @@ static const struct VIA_PCI_REG_INIT_TABLE mNbStage1InitTbl[] = {
/* VT3409 no PCI-E */
{ 0x00, 0xFF, NB_APIC_REG(0x61), 0xFF, 0x0E }, // Set Exxxxxxx as pcie mmio config range
{ 0x00, 0xFF, NB_APIC_REG(0x60), 0xF4, 0x0B }, // Support extended cfg address of pcie
- // { 0x00, 0xFF, NB_APIC_REG(0x42), 0xF9, 0x02 }, // APIC Interrupt((BT_INTR)) Control
+ // { 0x00, 0xFF, NB_APIC_REG(0x42), 0xF9, 0x02 }, // APIC Interrupt((BT_INTR)) Control
// Set ROMSIP value by software
/*
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 06:08:17 +0000