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-rw-r--r--src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
index ec6fd96a34..98dd3a5fec 100644
--- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
@@ -61,6 +61,12 @@ chip soc/intel/alderlake
[PchSerialIoIndexUART2] = PchSerialIoDisabled,
}"
+ register "pch_slp_s3_min_assertion_width" = "SLP_S3_ASSERTION_50_MS"
+ register "pch_slp_s4_min_assertion_width" = "SLP_S4_ASSERTION_1S"
+ register "pch_slp_sus_min_assertion_width" = "SLP_SUS_ASSERTION_1_S"
+ register "pch_slp_a_min_assertion_width" = "SLP_A_ASSERTION_98_MS"
+ register "pch_reset_power_cycle_duration" = "POWER_CYCLE_DURATION_1S"
+
# HD Audio
register "PchHdaDspEnable" = "1"
register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T"