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-rwxr-xr-x[-rw-r--r--]src/mainboard/advansus/a785e-i/Makefile.inc15
-rwxr-xr-x[-rw-r--r--]src/mainboard/amd/inagua/Makefile.inc4
-rw-r--r--src/mainboard/amd/mahogany/mainboard.c5
-rw-r--r--src/mainboard/amd/mahogany/romstage.c5
-rw-r--r--src/mainboard/amd/mahogany_fam10/mainboard.c5
-rw-r--r--src/mainboard/amd/mahogany_fam10/romstage.c6
-rwxr-xr-x[-rw-r--r--]src/mainboard/amd/tilapia_fam10/Kconfig9
-rwxr-xr-x[-rw-r--r--]src/mainboard/amd/tilapia_fam10/mainboard.c7
-rwxr-xr-x[-rw-r--r--]src/mainboard/amd/tilapia_fam10/romstage.c5
-rw-r--r--src/mainboard/asrock/939a785gmh/mainboard.c5
-rw-r--r--src/mainboard/asrock/939a785gmh/romstage.c7
-rw-r--r--src/mainboard/asus/m4a78-em/mainboard.c10
-rw-r--r--src/mainboard/asus/m4a78-em/romstage.c5
-rw-r--r--src/mainboard/asus/m4a785-m/mainboard.c9
-rw-r--r--src/mainboard/asus/m4a785-m/romstage.c5
-rw-r--r--src/mainboard/gigabyte/ma785gmt/mainboard.c9
-rw-r--r--src/mainboard/gigabyte/ma785gmt/romstage.c5
-rw-r--r--src/mainboard/gigabyte/ma78gm/mainboard.c5
-rw-r--r--src/mainboard/gigabyte/ma78gm/romstage.c5
-rw-r--r--src/mainboard/iei/kino-780am2-fam10/mainboard.c5
-rw-r--r--src/mainboard/iei/kino-780am2-fam10/romstage.c5
-rw-r--r--src/mainboard/jetway/pa78vm5/mainboard.c5
-rw-r--r--src/mainboard/jetway/pa78vm5/romstage.c5
-rwxr-xr-x[-rw-r--r--]src/mainboard/supermicro/h8scm_fam10/Kconfig2
-rwxr-xr-x[-rw-r--r--]src/mainboard/supermicro/h8scm_fam10/mainboard.c37
-rwxr-xr-x[-rw-r--r--]src/mainboard/supermicro/h8scm_fam10/romstage.c15
26 files changed, 82 insertions, 118 deletions
diff --git a/src/mainboard/advansus/a785e-i/Makefile.inc b/src/mainboard/advansus/a785e-i/Makefile.inc
index a81d135363..cf8ec2664c 100644..100755
--- a/src/mainboard/advansus/a785e-i/Makefile.inc
+++ b/src/mainboard/advansus/a785e-i/Makefile.inc
@@ -6,14 +6,15 @@ ramstage-y += pmio.c
#SB800 CIMx share AGESA V5 lib code
ifneq ($(CONFIG_AMD_AGESA),y)
- romstage-y += ../../../vendorcode/amd/agesa/f14/Lib/amdlib.c
- ramstage-y += ../../../vendorcode/amd/agesa/f14/Lib/amdlib.c
+ AGESA_ROOT ?= src/vendorcode/amd/agesa/f14
+ romstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c
+ ramstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c
- AGESA_INC := -Isrc/vendorcode/amd/agesa/f14/ \
- -Isrc/vendorcode/amd/agesa/f14/Include \
- -Isrc/vendorcode/amd/agesa/f14/Proc/IDS/ \
- -Isrc/vendorcode/amd/agesa/f14/Proc/CPU/ \
- -Isrc/vendorcode/amd/agesa/f14/Proc/CPU/Family
+ AGESA_INC := -I$(AGESA_ROOT)/ \
+ -I$(AGESA_ROOT)/Include \
+ -I$(AGESA_ROOT)/Proc/IDS/ \
+ -I$(AGESA_ROOT)/Proc/CPU/ \
+ -I$(AGESA_ROOT)/Proc/CPU/Family
CFLAGS += $(AGESA_INC)
endif
diff --git a/src/mainboard/amd/inagua/Makefile.inc b/src/mainboard/amd/inagua/Makefile.inc
index 88af2b7302..564d196428 100644..100755
--- a/src/mainboard/amd/inagua/Makefile.inc
+++ b/src/mainboard/amd/inagua/Makefile.inc
@@ -31,3 +31,7 @@ ramstage-y += PlatformGnbPcie.c
ramstage-y += reset.c
ramstage-y += pmio.c
+
+AGESA_ROOT ?= src/vendorcode/amd/agesa/f14
+subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += ../../../../$(AGESA_ROOT)
+#subdirs-$(CONFIG_AMD_CIMX) += ../../../vendorcode/amd/cimx
diff --git a/src/mainboard/amd/mahogany/mainboard.c b/src/mainboard/amd/mahogany/mainboard.c
index 9d471d029a..0ccef102f3 100644
--- a/src/mainboard/amd/mahogany/mainboard.c
+++ b/src/mainboard/amd/mahogany/mainboard.c
@@ -25,11 +25,10 @@
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
-#include <southbridge/amd/sb700/sb700.h>
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "chip.h"
-#define SMBUS_IO_BASE 0x6000
-
uint64_t uma_memory_base, uma_memory_size;
void set_pcie_dereset(void);
diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c
index b4c9635fe9..5c9d5383c2 100644
--- a/src/mainboard/amd/mahogany/romstage.c
+++ b/src/mainboard/amd/mahogany/romstage.c
@@ -44,7 +44,8 @@
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
-#include "southbridge/amd/sb700/early_setup.c"
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */
static void memreset(int controllers, const struct mem_controller *ctrl) { }
@@ -52,7 +53,7 @@ static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(u32 device, u32 address)
{
- return smbus_read_byte(device, address);
+ return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include "northbridge/amd/amdk8/amdk8.h"
diff --git a/src/mainboard/amd/mahogany_fam10/mainboard.c b/src/mainboard/amd/mahogany_fam10/mainboard.c
index 7ed615dd5b..2cbeaf127b 100644
--- a/src/mainboard/amd/mahogany_fam10/mainboard.c
+++ b/src/mainboard/amd/mahogany_fam10/mainboard.c
@@ -25,11 +25,10 @@
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
-#include <southbridge/amd/sb700/sb700.h>
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "chip.h"
-#define SMBUS_IO_BASE 0x6000
-
uint64_t uma_memory_base, uma_memory_size;
void set_pcie_dereset(void);
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index 680e60dbb7..4d26ca392a 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -48,7 +48,8 @@
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
-#include "southbridge/amd/sb700/early_setup.c"
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "northbridge/amd/amdfam10/debug.c"
#include <spd.h>
@@ -56,7 +57,7 @@ static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
{
- return smbus_read_byte(device, address);
+ return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
@@ -73,7 +74,6 @@ static int spd_read_byte(u32 device, u32 address)
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
-#include "southbridge/amd/sb700/early_setup.c"
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
diff --git a/src/mainboard/amd/tilapia_fam10/Kconfig b/src/mainboard/amd/tilapia_fam10/Kconfig
index b18115b8e9..e9d6081912 100644..100755
--- a/src/mainboard/amd/tilapia_fam10/Kconfig
+++ b/src/mainboard/amd/tilapia_fam10/Kconfig
@@ -83,4 +83,13 @@ config RAMBASE
hex
default 0x200000
+config VGA_BIOS
+ bool
+ default n
+
+config VGA_BIOS_ID
+ string
+ depends on VGA_BIOS
+ default "1002,9615"
+
endif # BOARD_AMD_TILAPIA_FAM10
diff --git a/src/mainboard/amd/tilapia_fam10/mainboard.c b/src/mainboard/amd/tilapia_fam10/mainboard.c
index 84ff92884c..357bdac230 100644..100755
--- a/src/mainboard/amd/tilapia_fam10/mainboard.c
+++ b/src/mainboard/amd/tilapia_fam10/mainboard.c
@@ -26,15 +26,12 @@
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
#include <southbridge/amd/sb700/sb700.h>
+#include "southbridge/amd/sb700/smbus.h"
#include "chip.h"
#define ADT7461_ADDRESS 0x4C
#define ARA_ADDRESS 0x0C /* Alert Response Address */
-extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
-extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
- u8 val);
-
#define ADT7461_read_byte(address) \
do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
#define ARA_read_byte(address) \
@@ -42,8 +39,6 @@ extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
#define ADT7461_write_byte(address, val) \
do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
-#define SMBUS_IO_BASE 0x6000
-
uint64_t uma_memory_base, uma_memory_size;
void set_pcie_dereset(void);
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index 3a85a15f84..48b13be1c7 100644..100755
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -48,14 +48,15 @@
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
-#include "southbridge/amd/sb700/early_setup.c"
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "northbridge/amd/amdfam10/debug.c"
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
{
- return smbus_read_byte(device, address);
+ return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
diff --git a/src/mainboard/asrock/939a785gmh/mainboard.c b/src/mainboard/asrock/939a785gmh/mainboard.c
index 1cf1731ce1..945a19f040 100644
--- a/src/mainboard/asrock/939a785gmh/mainboard.c
+++ b/src/mainboard/asrock/939a785gmh/mainboard.c
@@ -25,11 +25,10 @@
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
-#include <southbridge/amd/sb700/sb700.h>
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "chip.h"
-#define SMBUS_IO_BASE 0x6000
-
uint64_t uma_memory_base, uma_memory_size;
void set_pcie_dereset(void);
diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c
index b0ae24794f..bd45c166af 100644
--- a/src/mainboard/asrock/939a785gmh/romstage.c
+++ b/src/mainboard/asrock/939a785gmh/romstage.c
@@ -45,7 +45,8 @@
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
-#include "southbridge/amd/sb700/early_setup.c"
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */
#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
@@ -56,7 +57,7 @@ static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(u32 device, u32 address)
{
- return smbus_read_byte(device, address);
+ return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include "northbridge/amd/amdk8/amdk8.h"
@@ -101,7 +102,7 @@ static void sio_init(void)
pnp_write_config(GPIO2345_DEV, 0xe4, 0x0e); /* data */
pnp_write_config(GPIO2345_DEV, 0xe5, 0x00); /* No inversion */
- /* GPIO30 - unknown output, set to 0
+ /* GPIO30 - unknown output, set to 0
GPI31 - unknown input NC?
GPI32 - unknown input NC?
GPIO33 - unknown output, set to 0.
diff --git a/src/mainboard/asus/m4a78-em/mainboard.c b/src/mainboard/asus/m4a78-em/mainboard.c
index 910fce159d..6042d077c7 100644
--- a/src/mainboard/asus/m4a78-em/mainboard.c
+++ b/src/mainboard/asus/m4a78-em/mainboard.c
@@ -24,17 +24,11 @@
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
-#include <southbridge/amd/sb700/sb700.h>
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "chip.h"
-extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
-extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
- u8 val);
-
-
-#define SMBUS_IO_BASE 0x6000
-
uint64_t uma_memory_base, uma_memory_size;
void set_pcie_dereset(void);
diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c
index 0675ee670f..b14a7c6845 100644
--- a/src/mainboard/asus/m4a78-em/romstage.c
+++ b/src/mainboard/asus/m4a78-em/romstage.c
@@ -48,14 +48,15 @@
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
-#include "southbridge/amd/sb700/early_setup.c"
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "northbridge/amd/amdfam10/debug.c"
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
{
- return smbus_read_byte(device, address);
+ return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
diff --git a/src/mainboard/asus/m4a785-m/mainboard.c b/src/mainboard/asus/m4a785-m/mainboard.c
index a5a15e84d9..e490f31886 100644
--- a/src/mainboard/asus/m4a785-m/mainboard.c
+++ b/src/mainboard/asus/m4a785-m/mainboard.c
@@ -24,16 +24,13 @@
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
-#include <southbridge/amd/sb700/sb700.h>
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "chip.h"
#define ADT7461_ADDRESS 0x4C
#define ARA_ADDRESS 0x0C /* Alert Response Address */
-extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
-extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
- u8 val);
-
#define ADT7461_read_byte(address) \
do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
#define ARA_read_byte(address) \
@@ -41,8 +38,6 @@ extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
#define ADT7461_write_byte(address, val) \
do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
-#define SMBUS_IO_BASE 0x6000
-
uint64_t uma_memory_base, uma_memory_size;
void set_pcie_dereset(void);
diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index 0675ee670f..b14a7c6845 100644
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -48,14 +48,15 @@
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
-#include "southbridge/amd/sb700/early_setup.c"
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "northbridge/amd/amdfam10/debug.c"
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
{
- return smbus_read_byte(device, address);
+ return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
diff --git a/src/mainboard/gigabyte/ma785gmt/mainboard.c b/src/mainboard/gigabyte/ma785gmt/mainboard.c
index d6c95e0c9f..768c9e1d55 100644
--- a/src/mainboard/gigabyte/ma785gmt/mainboard.c
+++ b/src/mainboard/gigabyte/ma785gmt/mainboard.c
@@ -25,16 +25,13 @@
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
-#include <southbridge/amd/sb700/sb700.h>
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "chip.h"
#define ADT7461_ADDRESS 0x4C
#define ARA_ADDRESS 0x0C /* Alert Response Address */
-extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
-extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
- u8 val);
-
#define ADT7461_read_byte(address) \
do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
#define ARA_read_byte(address) \
@@ -42,8 +39,6 @@ extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
#define ADT7461_write_byte(address, val) \
do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
-#define SMBUS_IO_BASE 0x6000
-
uint64_t uma_memory_base, uma_memory_size;
void set_pcie_dereset(void);
diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index 8f3f55d486..fcf023b105 100644
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -44,14 +44,15 @@
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
-#include "southbridge/amd/sb700/early_setup.c"
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "northbridge/amd/amdfam10/debug.c"
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
{
- return smbus_read_byte(device, address);
+ return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
diff --git a/src/mainboard/gigabyte/ma78gm/mainboard.c b/src/mainboard/gigabyte/ma78gm/mainboard.c
index dcb37992c5..1a00af6a5e 100644
--- a/src/mainboard/gigabyte/ma78gm/mainboard.c
+++ b/src/mainboard/gigabyte/ma78gm/mainboard.c
@@ -26,11 +26,10 @@
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
-#include <southbridge/amd/sb700/sb700.h>
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "chip.h"
-#define SMBUS_IO_BASE 0x6000
-
uint64_t uma_memory_base, uma_memory_size;
void set_pcie_dereset(void);
diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index c34fa5b878..80b8d90508 100644
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -48,14 +48,15 @@
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
-#include "southbridge/amd/sb700/early_setup.c"
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "northbridge/amd/amdfam10/debug.c"
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
{
- return smbus_read_byte(device, address);
+ return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
diff --git a/src/mainboard/iei/kino-780am2-fam10/mainboard.c b/src/mainboard/iei/kino-780am2-fam10/mainboard.c
index 379efe519b..4d0cd0985c 100644
--- a/src/mainboard/iei/kino-780am2-fam10/mainboard.c
+++ b/src/mainboard/iei/kino-780am2-fam10/mainboard.c
@@ -25,11 +25,10 @@
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
-#include <southbridge/amd/sb700/sb700.h>
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "chip.h"
-#define SMBUS_IO_BASE 0x6000
-
uint64_t uma_memory_base, uma_memory_size;
void set_pcie_dereset(void);
diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
index 192b47ab42..58b1845787 100644
--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
@@ -48,7 +48,8 @@
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
-#include "southbridge/amd/sb700/early_setup.c"
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "northbridge/amd/amdfam10/debug.c"
#define SERIAL_DEV PNP_DEV(0x2e, F71859_SP1)
@@ -57,7 +58,7 @@ static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
{
- return smbus_read_byte(device, address);
+ return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
diff --git a/src/mainboard/jetway/pa78vm5/mainboard.c b/src/mainboard/jetway/pa78vm5/mainboard.c
index 188cadf3d5..6d0ceba31e 100644
--- a/src/mainboard/jetway/pa78vm5/mainboard.c
+++ b/src/mainboard/jetway/pa78vm5/mainboard.c
@@ -26,11 +26,10 @@
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
-#include <southbridge/amd/sb700/sb700.h>
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "chip.h"
-#define SMBUS_IO_BASE 0x6000
-
uint64_t uma_memory_base, uma_memory_size;
void set_pcie_dereset(void);
diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index 4ffcadebec..11bda6a600 100644
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -49,7 +49,8 @@
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
-#include "southbridge/amd/sb700/early_setup.c"
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "northbridge/amd/amdfam10/debug.c"
#if CONFIG_TTYS0_BASE == 0x2f8
@@ -62,7 +63,7 @@ static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
{
- return smbus_read_byte(device, address);
+ return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
diff --git a/src/mainboard/supermicro/h8scm_fam10/Kconfig b/src/mainboard/supermicro/h8scm_fam10/Kconfig
index e0547ab5f4..7742133dac 100644..100755
--- a/src/mainboard/supermicro/h8scm_fam10/Kconfig
+++ b/src/mainboard/supermicro/h8scm_fam10/Kconfig
@@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_OPTION_TABLE
select GENERATE_PIRQ_TABLE
select GENERATE_MP_TABLE
- select HAVE_MAINBOARD_RESOURCES
select HAVE_HARD_RESET
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select LIFT_BSP_APIC_ID
@@ -24,7 +23,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select BOARD_ROMSIZE_KB_2048
select RAMINIT_SYSINFO
select ENABLE_APIC_EXT_ID
- select GFXUMA
config MAINBOARD_DIR
string
diff --git a/src/mainboard/supermicro/h8scm_fam10/mainboard.c b/src/mainboard/supermicro/h8scm_fam10/mainboard.c
index e6ed22b1a0..90b53357ad 100644..100755
--- a/src/mainboard/supermicro/h8scm_fam10/mainboard.c
+++ b/src/mainboard/supermicro/h8scm_fam10/mainboard.c
@@ -29,9 +29,6 @@
#include <southbridge/amd/sr5650/cmn.h>
#include "chip.h"
-#define SMBUS_IO_BASE 0x6000
-
-uint64_t uma_memory_base, uma_memory_size;
void set_pcie_reset(void);
void set_pcie_dereset(void);
@@ -95,47 +92,17 @@ static void h8scm_enable(device_t dev)
printk
(BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
__func__, msr2.lo, msr2.hi);
-#if (CONFIG_GFXUMA == 1)
-
- /* refer to UMA Size Consideration in 780 BDG. */
- switch (msr.lo) {
- case 0x10000000: /* 256M system memory */
- uma_memory_size = 0x4000000; /* 64M recommended UMA */
- break;
-
- case 0x20000000: /* 512M system memory */
- uma_memory_size = 0x8000000; /* 128M recommended UMA */
- break;
-
- default: /* 1GB and above system memory */
- uma_memory_size = 0x10000000; /* 256M recommended UMA */
- break;
- }
-#else
- /* TODO: TOP_MEM2 */
- uma_memory_size = 0;//0x8000000; /* 128M recommended UMA */
-#endif
- uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */
- printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
- __func__, uma_memory_size, uma_memory_base);
set_pcie_dereset();
/* get_ide_dma66(); */
}
+#if (CONFIG_HAVE_MAINBOARD_RESOURCES == 1)
int add_mainboard_resources(struct lb_memory *mem)
{
- /* UMA is removed from system memory in the northbridge code, but
- * in some circumstances we want the memory mentioned as reserved.
- */
-#if (CONFIG_GFXUMA == 1)
- printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
- uma_memory_base, uma_memory_size);
- lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
- uma_memory_size);
-#endif
return 0;
}
+#endif
struct chip_operations mainboard_ops = {
CHIP_NAME("AMD H8SCM Mainboard")
diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
index 8101d2fad2..6e6e3940df 100644..100755
--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c
@@ -42,13 +42,14 @@
#include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h>
#include "cpu/x86/bist.h"
-#include "superio/nuvoton/wpcm450/early_init.c"
#include <usbdebug.h>
#include "cpu/x86/mtrr/earlymtrr.c"
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/amd/sb700/early_setup.c"
-#include "southbridge/amd/sr5650/early_setup.c"
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
+#include "southbridge/amd/sr5650/sr5650.h"
+#include "superio/nuvoton/wpcm450/wpcm450.h"
#include "northbridge/amd/amdfam10/debug.c"
static void activate_spd_rom(const struct mem_controller *ctrl)
@@ -57,7 +58,7 @@ static void activate_spd_rom(const struct mem_controller *ctrl)
static int spd_read_byte(u32 device, u32 address)
{
- return smbus_read_byte(device, address);
+ return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
@@ -102,7 +103,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
- disable_pcie_bridge();
+ /* SR56x0 pcie bridges block pci_locate_device() before pcie training.
+ * disable all pcie bridges on SR56x0 to work around it
+ */
+ sr5650_disable_pcie_bridge();
sb7xx_51xx_lpc_port80();
}
@@ -181,7 +185,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* run _early_setup before soft-reset. */
sr5650_early_setup();
- disable_pcie_bridge();
sb7xx_51xx_early_setup();
#if CONFIG_SET_FIDVID