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-rw-r--r--src/mainboard/pcengines/apu1/bootblock.c8
-rw-r--r--src/mainboard/pcengines/apu1/romstage.c5
2 files changed, 6 insertions, 7 deletions
diff --git a/src/mainboard/pcengines/apu1/bootblock.c b/src/mainboard/pcengines/apu1/bootblock.c
index 2d34cba3bf..dc9f87d905 100644
--- a/src/mainboard/pcengines/apu1/bootblock.c
+++ b/src/mainboard/pcengines/apu1/bootblock.c
@@ -17,9 +17,13 @@
#include <superio/nuvoton/nct5104d/nct5104d.h>
#define SIO_PORT 0x2e
-#define SERIAL_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1)
+#define SERIAL1_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1)
+#define SERIAL2_DEV PNP_DEV(SIO_PORT, NCT5104D_SP2)
void bootblock_mainboard_early_init(void)
{
- nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ if (CONFIG_UART_FOR_CONSOLE == 1)
+ nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE);
+ else if (CONFIG_UART_FOR_CONSOLE == 0)
+ nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE);
}
diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c
index 20a6318a46..df91b04c0a 100644
--- a/src/mainboard/pcengines/apu1/romstage.c
+++ b/src/mainboard/pcengines/apu1/romstage.c
@@ -17,15 +17,10 @@
#include <amdblocks/acpimmio.h>
#include <northbridge/amd/agesa/state_machine.h>
-#include <superio/nuvoton/common/nuvoton.h>
-#include <superio/nuvoton/nct5104d/nct5104d.h>
#include "gpio_ftns.h"
#include <SB800.h>
#include <sb_cimx.h>
-#define SIO_PORT 0x2e
-#define SERIAL_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1)
-
static void early_lpc_init(void)
{
u32 mmio_base;