2 files changed, 60 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl
index 87e98ea925..e2959a788a 100644
--- a/src/mainboard/google/hatch/dsdt.asl
+++ b/src/mainboard/google/hatch/dsdt.asl
@@ -41,6 +41,9 @@ DefinitionBlock(
 			#include <soc/intel/cannonlake/acpi/northbridge.asl>
 			#include <soc/intel/cannonlake/acpi/southbridge.asl>
 		}
+
+		/* Mainboard hooks */
+		#include "mainboard.asl"
 	}
 
 #if CONFIG(CHROMEOS)
diff --git a/src/mainboard/google/hatch/mainboard.asl b/src/mainboard/google/hatch/mainboard.asl
new file mode 100644
index 0000000000..dff1a75959
--- /dev/null
+++ b/src/mainboard/google/hatch/mainboard.asl
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <intelblocks/gpio.h>
+
+Method (LOCL, 1, Serialized)
+{
+	For (Local0 = 0, Local0 < 5, Local0++)
+	{
+		\_SB.PCI0.CGPM (Local0, Arg0)
+	}
+}
+
+/*
+ * Method called from _PTS prior to system sleep state entry
+ * Enables dynamic clock gating for all 5 GPIO communities
+ */
+Method (MPTS, 1, Serialized)
+{
+	LOCL (MISCCFG_ENABLE_GPIO_PM_CONFIG)
+}
+
+/*
+ * Method called from _WAK prior to system sleep state wakeup
+ * Disables dynamic clock gating for all 5 GPIO communities
+ */
+Method (MWAK, 1, Serialized)
+{
+	LOCL (0)
+}
+
+/*
+ * S0ix Entry/Exit Notifications
+ * Called from \_SB.LPID._DSM
+ */
+Method (MS0X, 1, Serialized)
+{
+	If (Arg0 == 1) {
+		/* S0ix Entry */
+		LOCL (MISCCFG_ENABLE_GPIO_PM_CONFIG)
+	} Else {
+		/* S0ix Exit */
+		LOCL (0)
+	}
+}