diff options
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/amd/quartet/Config.lb | 35 | ||||
| -rw-r--r-- | src/mainboard/amd/quartet/auto.c | 2 | ||||
| -rw-r--r-- | src/mainboard/amd/quartet/mainboard.c | 2 | ||||
| -rw-r--r-- | src/mainboard/amd/solo/Config.lb | 71 | ||||
| -rw-r--r-- | src/mainboard/amd/solo/mainboard.c | 2 | ||||
| -rw-r--r-- | src/mainboard/arima/hdama/Config.lb | 370 | ||||
| -rw-r--r-- | src/mainboard/arima/hdama/auto.c | 30 | ||||
| -rw-r--r-- | src/mainboard/arima/hdama/mainboard.c | 2 | ||||
| -rw-r--r-- | src/mainboard/newisys/khepri/Config.lb | 28 | ||||
| -rw-r--r-- | src/mainboard/newisys/khepri/auto.c | 2 | ||||
| -rw-r--r-- | src/mainboard/newisys/khepri/mainboard.c | 2 | ||||
| -rw-r--r-- | src/mainboard/tyan/s2880/Config.lb | 29 | ||||
| -rw-r--r-- | src/mainboard/tyan/s2880/mainboard.c | 2 | ||||
| -rw-r--r-- | src/mainboard/tyan/s2882/Config.lb | 29 | ||||
| -rw-r--r-- | src/mainboard/tyan/s2882/mainboard.c | 2 | ||||
| -rw-r--r-- | src/mainboard/tyan/s2885/Config.lb | 29 | ||||
| -rw-r--r-- | src/mainboard/tyan/s2885/mainboard.c | 2 |
17 files changed, 301 insertions, 338 deletions
diff --git a/src/mainboard/amd/quartet/Config.lb b/src/mainboard/amd/quartet/Config.lb index 97634ab25a..b6d65b4cb5 100644 --- a/src/mainboard/amd/quartet/Config.lb +++ b/src/mainboard/amd/quartet/Config.lb @@ -1,8 +1,6 @@ uses HAVE_MP_TABLE uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE -uses USE_NORMAL_IMAGE -uses ENABLE_IOMMU # # ### @@ -34,15 +32,11 @@ ldscript /cpu/i386/entry32.lds ### Build our reset vector (This is where linuxBIOS is entered) ### if USE_FALLBACK_IMAGE - mainboardinit cpu/i386/reset16.inc - ldscript /cpu/i386/reset16.lds + mainboardinit cpu/i386/reset16.inc + ldscript /cpu/i386/reset16.lds else - print "NO FALLBACK USED!" -end - -if USE_NORMAL_IMAGE - mainboardinit cpu/i386/reset32.inc - ldscript /cpu/i386/reset32.lds + mainboardinit cpu/i386/reset32.inc + ldscript /cpu/i386/reset32.lds end # #### Should this be in the northbridge code? @@ -76,15 +70,6 @@ end mainboardinit cpu/k8/earlymtrr.inc # # -### -### Only the bootstrap cpu makes it here. -### Failover if we need to -### -# -if USE_FALLBACK_IMAGE - mainboardinit southbridge/amd/amd8111/cmos_boot_failover.inc -end -# #### #### O.k. We aren't just an intermediary anymore! #### @@ -94,10 +79,6 @@ end ### ##option MAXIMUM_CONSOLE_LOGLEVEL=7 #default MAXIMUM_CONSOLE_LOGLEVEL=7 -#option DISABLE_WATCHDOG= (MAXIMUM_CONSOLE_LOGLEVEL >= 8) -#if DISABLE_WATCHDOG -# mainboardinit southbridgeamd/amd8111/disable_watchdog.inc -#end # if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end # @@ -118,13 +99,6 @@ end mainboardinit ./auto.inc # ### -### Setup RAM -### -mainboardinit ram/ramtest.inc -mainboardinit southbridge/amd/amd8111/smbus.inc -mainboardinit sdram/generic_dump_spd.inc -# -### ### Include the secondary Configuration files ### northbridge amd/amdk8 @@ -142,4 +116,3 @@ cpu p6 end cpu k7 end cpu k8 end -option ENABLE_IOMMU=1 diff --git a/src/mainboard/amd/quartet/auto.c b/src/mainboard/amd/quartet/auto.c index a347f20b70..3166f7ad3c 100644 --- a/src/mainboard/amd/quartet/auto.c +++ b/src/mainboard/amd/quartet/auto.c @@ -17,6 +17,8 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "debug.c" +#define SIO_BASE 0x2e + static void memreset_setup(void) { /* Set the memreset low */ diff --git a/src/mainboard/amd/quartet/mainboard.c b/src/mainboard/amd/quartet/mainboard.c index d93d2ed1d9..0622150d64 100644 --- a/src/mainboard/amd/quartet/mainboard.c +++ b/src/mainboard/amd/quartet/mainboard.c @@ -5,7 +5,7 @@ #include <device/pci_ops.h> -unsigned long initial_apicid[MAX_CPUS] = +unsigned long initial_apicid[CONFIG_MAX_CPUS] = { 0, 1, 2, 3 }; diff --git a/src/mainboard/amd/solo/Config.lb b/src/mainboard/amd/solo/Config.lb index f237a5cbea..12c59fdb38 100644 --- a/src/mainboard/amd/solo/Config.lb +++ b/src/mainboard/amd/solo/Config.lb @@ -24,8 +24,6 @@ default CONFIG_UDELAY_TSC=0 ### ### Customize our winbond superio chip for this motherboard ### -option SIO_BASE=0x2e -option SIO_SYSTEM_CLK_INPUT=0 option CONFIG_CONSOLE_SERIAL8250=0 # ### @@ -51,16 +49,11 @@ option IRQ_SLOT_COUNT=7 ##option HAVE_MP_TABLE=1 # ### -### Do not build special code for the keyboard -### -default NO_KEYBOARD=1 -# -### ### Build code for SMP support ### Only worry about 2 micro processors ### ##option CONFIG_SMP=1 -option MAX_CPUS=1 +option CONFIG_MAX_CPUS=1 # ### ### Build code to setup a generic IOAPIC @@ -79,37 +72,17 @@ option CONFIG_IOAPIC=1 option MEMORY_HOLE=0 # ### -### Enable both fixed and variable MTRRS -### When we setup MTRRs in mtrr.c -### -### We must setup the fixed mtrrs or we confuse SMP secondary -### processor identification -### -option ENABLE_FIXED_AND_VARIABLE_MTRRS=1 -# -### ### Clean up the motherboard id strings ### option MAINBOARD_PART_NUMBER="Solo7" option MAINBOARD_VENDOR="AMD" # ### -### Let Assembly code know where on the pci bus the AMD southbridge is -### -option AMD8111_DEV=0x3800 -# -### -### Call the final_mainboard_fixup function -### -option FINAL_MAINBOARD_FIXUP=1 -# -### ### Figure out which type of linuxBIOS image to build ### If we aren't a fallback image we must be a normal image ### This is useful for optional includes ### default USE_FALLBACK_IMAGE=0 -option USE_NORMAL_IMAGE=(! USE_FALLBACK_IMAGE) # #### #### LinuxBIOS layout values @@ -144,8 +117,7 @@ default FALLBACK_SIZE=65536 if USE_FALLBACK_IMAGE option ROM_SECTION_SIZE = FALLBACK_SIZE option ROM_SECTION_OFFSET= (ROM_SIZE - FALLBACK_SIZE) -end -if USE_NORMAL_IMAGE +else option ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) option ROM_SECTION_OFFSET= 0 end @@ -177,13 +149,6 @@ option _ROMBASE = (CONFIG_ROM_STREAM_START + PAYLOAD_SIZE) ##option XIP_ROM_BASE=0xffff8000 # ### -### Compute where the SMP startup code needs to live -### FIXME I don't see how to make this work for the normal image.... -### -option START_CPU_SEG=0xf0000 -# -# -### ### Set all of the defaults for an x86 architecture ### # @@ -217,13 +182,11 @@ ldscript /cpu/i386/entry32.lds ### Build our reset vector (This is where linuxBIOS is entered) ### if USE_FALLBACK_IMAGE - mainboardinit cpu/i386/reset16.inc - ldscript /cpu/i386/reset16.lds -end - -if USE_NORMAL_IMAGE - mainboardinit cpu/i386/reset32.inc - ldscript /cpu/i386/reset32.lds + mainboardinit cpu/i386/reset16.inc + ldscript /cpu/i386/reset16.lds +else + mainboardinit cpu/i386/reset32.inc + ldscript /cpu/i386/reset32.lds end # #### Should this be in the northbridge code? @@ -251,15 +214,6 @@ end mainboardinit cpu/k8/earlymtrr.inc # # -### -### Only the bootstrap cpu makes it here. -### Failover if we need to -### -# -if USE_FALLBACK_IMAGE - mainboardinit southbridge/amd/amd8111/cmos_boot_failover.inc -end -# #### #### O.k. We aren't just an intermediary anymore! #### @@ -269,10 +223,6 @@ end ### ##option MAXIMUM_CONSOLE_LOGLEVEL=7 #default MAXIMUM_CONSOLE_LOGLEVEL=7 -#option DISABLE_WATCHDOG= (MAXIMUM_CONSOLE_LOGLEVEL >= 8) -#if DISABLE_WATCHDOG -# mainboardinit southbridgeamd/amd8111/disable_watchdog.inc -#end # ### ### Setup the serial port @@ -293,13 +243,6 @@ makerule ./auto.inc dep "./romcc ./auto.E" act "./romcc -O ./auto.E > auto.inc" mainboardinit ./auto.inc # ### -### Setup RAM -### -mainboardinit ram/ramtest.inc -mainboardinit southbridge/amd/amd8111/smbus.inc -mainboardinit sdram/generic_dump_spd.inc -# -### ### Include the secondary Configuration files ### northbridge amd/amdk8 diff --git a/src/mainboard/amd/solo/mainboard.c b/src/mainboard/amd/solo/mainboard.c index 5690bd5afd..75a77d6adb 100644 --- a/src/mainboard/amd/solo/mainboard.c +++ b/src/mainboard/amd/solo/mainboard.c @@ -5,7 +5,7 @@ #include <device/pci_ops.h> -unsigned long initial_apicid[MAX_CPUS] = +unsigned long initial_apicid[CONFIG_MAX_CPUS] = { 0 }; diff --git a/src/mainboard/arima/hdama/Config.lb b/src/mainboard/arima/hdama/Config.lb index db31552135..4947698590 100644 --- a/src/mainboard/arima/hdama/Config.lb +++ b/src/mainboard/arima/hdama/Config.lb @@ -1,168 +1,286 @@ uses HAVE_MP_TABLE uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE -uses USE_NORMAL_IMAGE -uses AMD8111_DEV uses MAINBOARD uses ARCH -uses ENABLE_IOMMU -# -# +uses FALLBACK_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_STREAM_START +uses PAYLOAD_SIZE +uses _ROMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE + ### -### Set all of the defaults for an x86 architecture +### Build options ### -# -# + +## +## Build code for the fallback boot +## +option HAVE_FALLBACK_BOOT=1 + +## +## Build code to reset the motherboard from linuxBIOS +## +option HAVE_HARD_RESET=1 + +## +## Build code to export a programmable irq routing table +## +option HAVE_PIRQ_TABLE=1 +option IRQ_SLOT_COUNT=7 + +## +## Build code to export an x86 MP table +## Useful for specifying IRQ routing values +## +option HAVE_MP_TABLE=1 + +## +## Build code to export a CMOS option table +## +option HAVE_OPTION_TABLE=1 + +## +## Build code for SMP support +## Only worry about 2 micro processors +## +option CONFIG_SMP=1 +option CONFIG_MAX_CPUS=2 + +## +## Build code to setup a generic IOAPIC +## +option CONFIG_IOAPIC=1 + +## +## Clean up the motherboard id strings +## +option MAINBOARD_PART_NUMBER="HDAMA" +option MAINBOARD_VENDOR="ARIMA" + ### -### Build the objects we have code for in this directory. +### LinuxBIOS layout values ### -##object mainboard.o + +## ROM_SIZE is the size of boot ROM that this board will use. +option ROM_SIZE = 524288 + +## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +option ROM_IMAGE_SIZE = 65536 + +## +## Use a small 8K stack +## +option STACK_SIZE=0x2000 + +## +## Use a small 16K heap +## +option HEAP_SIZE=0x4000 + +## +## Only use the option table in a normal image +## +option USE_OPTION_TABLE = !USE_FALLBACK_IMAGE + +## +## Compute the location and size of where this firmware image +## (linuxBIOS plus bootloader) will live in the boot rom chip. +## +if USE_FALLBACK_IMAGE + option ROM_SECTION_SIZE = FALLBACK_SIZE + option ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) +else + option ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) + option ROM_SECTION_OFFSET = 0 +end + +## +## Compute the start location and size size of +## The linuxBIOS bootloader. +## +option PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) +option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) +option CONFIG_ROM_STREAM = 1 + +## +## Compute where this copy of linuxBIOS will start in the boot rom +## +option _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE ) + +## +## Compute a range of ROM that can cached to speed up linuxBIOS, +## execution speed. +## +## XIP_ROM_SIZE must be a power of 2. +## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +## +option XIP_ROM_SIZE=65536 +option XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) + +## +## Set all of the defaults for an x86 architecture +## + +arch i386 end +#cpu k8 end + +## +## Build the objects we have code for in this directory. +## + +#object mainboard.o driver mainboard.o -object static_devices.o +#object static_devices.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -# -arch i386 end -#cpu k8 end -# -### -### Build our 16 bit and 32 bit linuxBIOS entry code -### +object reset.o + +## +## Romcc output +## +makerule ./failover.E + depends "$(MAINBOARD)/failover.c" + action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E" +end + +makerule ./failover.inc + depends "./failover.E ./romcc" + action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E" +end + +makerule ./auto.E + depends "$(MAINBOARD)/auto.c" + action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E" +end +makerule ./auto.inc + depends "./auto.E ./romcc" + action "./romcc -mcpu=k8 -O ./auto.E > auto.inc" +end + +## +## Build our 16 bit and 32 bit linuxBIOS entry code +## mainboardinit cpu/i386/entry16.inc mainboardinit cpu/i386/entry32.inc ldscript /cpu/i386/entry16.lds ldscript /cpu/i386/entry32.lds -# -### -### Build our reset vector (This is where linuxBIOS is entered) -### + +## +## Build our reset vector (This is where linuxBIOS is entered) +## if USE_FALLBACK_IMAGE - mainboardinit cpu/i386/reset16.inc - ldscript /cpu/i386/reset16.lds + mainboardinit cpu/i386/reset16.inc + ldscript /cpu/i386/reset16.lds else - print "NO FALLBACK USED!" + mainboardinit cpu/i386/reset32.inc + ldscript /cpu/i386/reset32.lds end -if USE_NORMAL_IMAGE - mainboardinit cpu/i386/reset32.inc - ldscript /cpu/i386/reset32.lds -end -# -#### Should this be in the northbridge code? +### Should this be in the northbridge code? mainboardinit arch/i386/lib/cpu_reset.inc -# -### -### Include an id string (For safe flashing) -### + +## +## Include an id string (For safe flashing) +## mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -# -#### -#### This is the early phase of linuxBIOS startup -#### Things are delicate and we test to see if we should -#### failover to another image. -#### -#option MAX_REBOOT_CNT=2 -if USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -end -# -### -### Setup our mtrrs -### + +## +## Setup our mtrrs +## mainboardinit cpu/k8/earlymtrr.inc + ### -### Only the bootstrap cpu makes it here. -### Failover if we need to +### This is the early phase of linuxBIOS startup +### Things are delicate and we test to see if we should +### failover to another image. ### -# if USE_FALLBACK_IMAGE - mainboardinit ./failover.inc -# mainboardinit southbridge/amd/amd8111/cmos_boot_failover.inc + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc end -# -# -### -### Setup the serial port -### -#mainboardinit superiowinbond/w83627hf/setup_serial.inc -mainboardinit pc80/serial.inc -mainboardinit arch/i386/lib/console.inc -# -#### -#### O.k. We aren't just an intermediary anymore! -#### -# -### -### When debugging disable the watchdog timer ### -##option MAXIMUM_CONSOLE_LOGLEVEL=7 -#default MAXIMUM_CONSOLE_LOGLEVEL=7 -#option DISABLE_WATCHDOG= (MAXIMUM_CONSOLE_LOGLEVEL >= 8) -#if DISABLE_WATCHDOG -# mainboardinit southbridgeamd/amd8111/disable_watchdog.inc -#end -# -#if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end -# +### O.k. We aren't just an intermediary anymore! ### -### Romcc output -### -#makerule ./failover.E dep "$(MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failever.E" -#makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc" -#mainboardinit .failover.inc - -makerule ./failover.E - depends "$(MAINBOARD)/failover.c" - action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E" -end -makerule ./failover.inc - depends "./romcc ./failover.E" - action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"end - -makerule ./auto.E - depends "$(MAINBOARD)/auto.c" - action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E" -end -makerule ./auto.inc - depends "./romcc ./auto.E" - action "./romcc -mcpu=k8 -O ./auto.E > auto.inc" -end +## +## Setup RAM +## mainboardinit cpu/k8/enable_mmx_sse.inc mainboardinit ./auto.inc mainboardinit cpu/k8/disable_mmx_sse.inc -# -### -### Setup RAM -### -#mainboardinit ram/ramtest.inc -#mainboardinit southbridge/amd/amd8111/smbus.inc -#mainboardinit sdram/generic_dump_spd.inc -# -### -### Include the secondary Configuration files -### -northbridge amd/amdk8 -end -southbridge amd/amd8111 "amd8111" -end -southbridge amd/amd8131 "amd8131" + +## +## Include the secondary Configuration files +## +dir /pc80 + +northbridge amd/amdk8 "mc0" + #pci 0:18.0 + #pci 0:18.0 + #pci 0:18.0 + #pci 0:18.1 + #pci 0:18.2 + #pci 0:18.3 + southbridge amd/amd8131 "amd8131" + #pci 0:0.0 + #pci 0:0.1 + #pci 0:1.0 + #pci 0:1.1 + end + southbridge amd/amd8111 "amd8111" + #pci 0:0.0 + #pci 0:1.0 + #pci 0:1.1 + #pci 0:1.2 + #pci 0:1.3 + #pci 0:1.5 off + #pci 0:1.6 off + superio NSC/pc87360 + #pnp 1:2e.0 + #pnp 1:2e.1 + #pnp 1:2e.2 + #pnp 1:2e.3 + #pnp 1:2e.4 + #pnp 1:2e.5 + #pnp 1:2e.6 + #pnp 1:2e.7 + #pnp 1:2e.8 + #pnp 1:2e.9 + #pnp 1:2e.a + register "com1" = "{1, 0, 0x3f8, 4}" + register "lpt" = "{1}" + end + end end -#mainboardinit archi386/smp/secondary.inc -superio NSC/pc87360 - register "com1" = "{1}" - register "lpt" = "{1}" + +northbridge amd/amdk8 "mc1" + #pci 0:19.0 + #pci 0:19.0 + #pci 0:19.0 + #pci 0:19.1 + #pci 0:19.2 + #pci 0:19.3 end -dir /pc80 -##dir /src/superio/winbond/w83627hf -#dir /cpu/k8 -cpu k8 "cpu0" - register "up" = "{.chip = &amd8111, .ht_width=8, .ht_speed=200}" + +cpu k8 "cpu0" + register "up" = "{ .chip = &amd8131, .ht_width=16, .ht_speed=600 }" end cpu k8 "cpu1" end -option ENABLE_IOMMU=1 +## +## Include the old serial code for those few places that still need it. +## +mainboardinit pc80/serial.inc +mainboardinit arch/i386/lib/console.inc + diff --git a/src/mainboard/arima/hdama/auto.c b/src/mainboard/arima/hdama/auto.c index ca19245293..f977496a7b 100644 --- a/src/mainboard/arima/hdama/auto.c +++ b/src/mainboard/arima/hdama/auto.c @@ -1,6 +1,4 @@ #define ASSEMBLY 1 -#define MAXIMUM_CONSOLE_LOGLEVEL 9 -#define DEFAULT_CONSOLE_LOGLEVEL 9 #include <stdint.h> #include <device/pci_def.h> @@ -20,6 +18,8 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "debug.c" +#define SIO_BASE 0x2e + static void memreset_setup(void) { /* Set the memreset low */ @@ -151,7 +151,7 @@ static void pc87360_enable_serial(void) } #define FIRST_CPU 1 -#define SECOND_CPU 0 +#define SECOND_CPU 1 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU) static void main(void) { @@ -209,7 +209,7 @@ static void main(void) memreset_setup(); sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); -#if 1 +#if 0 dump_pci_devices(); #endif #if 0 @@ -227,13 +227,21 @@ static void main(void) #endif #if 0 ram_check(0x00000000, msr.lo); -#else -#if TOTAL_CPUS < 2 - /* Check 16MB of memory @ 0*/ - ram_check(0x00000000, 0x01000); -#else - /* Check 16MB of memory @ 2GB */ - ram_check(0x80000000, 0x81000000); #endif +#if 0 + static const struct { + unsigned long lo, hi; + } check_addrs[] = { + /* Check 16MB of memory @ 0*/ + { 0x00000000, 0x01000000 }, +#if TOTAL_CPUS > 1 + /* Check 16MB of memory @ 2GB */ + { 0x80000000, 0x81000000 }, +#endif + }; + int i; + for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) { + ram_check(check_addrs[i].lo, check_addrs[i].hi); + } #endif } diff --git a/src/mainboard/arima/hdama/mainboard.c b/src/mainboard/arima/hdama/mainboard.c index 61092b799b..4f40e393b2 100644 --- a/src/mainboard/arima/hdama/mainboard.c +++ b/src/mainboard/arima/hdama/mainboard.c @@ -9,7 +9,7 @@ #include "chip.h" -unsigned long initial_apicid[MAX_CPUS] = +unsigned long initial_apicid[CONFIG_MAX_CPUS] = { 0, 1, }; diff --git a/src/mainboard/newisys/khepri/Config.lb b/src/mainboard/newisys/khepri/Config.lb index db31552135..2050b01367 100644 --- a/src/mainboard/newisys/khepri/Config.lb +++ b/src/mainboard/newisys/khepri/Config.lb @@ -1,11 +1,8 @@ uses HAVE_MP_TABLE uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE -uses USE_NORMAL_IMAGE -uses AMD8111_DEV uses MAINBOARD uses ARCH -uses ENABLE_IOMMU # # ### @@ -37,15 +34,11 @@ ldscript /cpu/i386/entry32.lds ### Build our reset vector (This is where linuxBIOS is entered) ### if USE_FALLBACK_IMAGE - mainboardinit cpu/i386/reset16.inc - ldscript /cpu/i386/reset16.lds + mainboardinit cpu/i386/reset16.inc + ldscript /cpu/i386/reset16.lds else - print "NO FALLBACK USED!" -end - -if USE_NORMAL_IMAGE - mainboardinit cpu/i386/reset32.inc - ldscript /cpu/i386/reset32.lds + mainboardinit cpu/i386/reset32.inc + ldscript /cpu/i386/reset32.lds end # #### Should this be in the northbridge code? @@ -78,7 +71,6 @@ mainboardinit cpu/k8/earlymtrr.inc # if USE_FALLBACK_IMAGE mainboardinit ./failover.inc -# mainboardinit southbridge/amd/amd8111/cmos_boot_failover.inc end # @@ -99,10 +91,6 @@ mainboardinit arch/i386/lib/console.inc ### ##option MAXIMUM_CONSOLE_LOGLEVEL=7 #default MAXIMUM_CONSOLE_LOGLEVEL=7 -#option DISABLE_WATCHDOG= (MAXIMUM_CONSOLE_LOGLEVEL >= 8) -#if DISABLE_WATCHDOG -# mainboardinit southbridgeamd/amd8111/disable_watchdog.inc -#end # #if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end # @@ -135,13 +123,6 @@ mainboardinit ./auto.inc mainboardinit cpu/k8/disable_mmx_sse.inc # ### -### Setup RAM -### -#mainboardinit ram/ramtest.inc -#mainboardinit southbridge/amd/amd8111/smbus.inc -#mainboardinit sdram/generic_dump_spd.inc -# -### ### Include the secondary Configuration files ### northbridge amd/amdk8 @@ -165,4 +146,3 @@ end cpu k8 "cpu1" end -option ENABLE_IOMMU=1 diff --git a/src/mainboard/newisys/khepri/auto.c b/src/mainboard/newisys/khepri/auto.c index ca19245293..29da7aa5e3 100644 --- a/src/mainboard/newisys/khepri/auto.c +++ b/src/mainboard/newisys/khepri/auto.c @@ -20,6 +20,8 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "debug.c" +#define SIO_BASE 0x2e + static void memreset_setup(void) { /* Set the memreset low */ diff --git a/src/mainboard/newisys/khepri/mainboard.c b/src/mainboard/newisys/khepri/mainboard.c index 9e5c0acc89..88c5977cbb 100644 --- a/src/mainboard/newisys/khepri/mainboard.c +++ b/src/mainboard/newisys/khepri/mainboard.c @@ -9,7 +9,7 @@ #include "chip.h" -unsigned long initial_apicid[MAX_CPUS] = +unsigned long initial_apicid[CONFIG_MAX_CPUS] = { 0, 1, }; diff --git a/src/mainboard/tyan/s2880/Config.lb b/src/mainboard/tyan/s2880/Config.lb index 9c9953e927..1661015535 100644 --- a/src/mainboard/tyan/s2880/Config.lb +++ b/src/mainboard/tyan/s2880/Config.lb @@ -1,11 +1,8 @@ uses HAVE_MP_TABLE uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE -uses USE_NORMAL_IMAGE -uses AMD8111_DEV uses MAINBOARD uses ARCH -uses ENABLE_IOMMU # # ### @@ -46,15 +43,11 @@ ldscript /cpu/i386/entry32.lds ### Build our reset vector (This is where linuxBIOS is entered) ### if USE_FALLBACK_IMAGE - mainboardinit cpu/i386/reset16.inc - ldscript /cpu/i386/reset16.lds + mainboardinit cpu/i386/reset16.inc + ldscript /cpu/i386/reset16.lds else -# print "NO FALLBACK USED!" -end - -if USE_NORMAL_IMAGE - mainboardinit cpu/i386/reset32.inc - ldscript /cpu/i386/reset32.lds + mainboardinit cpu/i386/reset32.inc + ldscript /cpu/i386/reset32.lds end # #### Should this be in the northbridge code? @@ -87,7 +80,6 @@ mainboardinit cpu/k8/earlymtrr.inc # if USE_FALLBACK_IMAGE mainboardinit ./failover.inc -# mainboardinit southbridge/amd/amd8111/cmos_boot_failover.inc end # @@ -108,10 +100,6 @@ mainboardinit arch/i386/lib/console.inc ### ##option MAXIMUM_CONSOLE_LOGLEVEL=7 #default MAXIMUM_CONSOLE_LOGLEVEL=7 -#option DISABLE_WATCHDOG= (MAXIMUM_CONSOLE_LOGLEVEL >= 8) -#if DISABLE_WATCHDOG -# mainboardinit southbridgeamd/amd8111/disable_watchdog.inc -#end # #if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end # @@ -145,13 +133,6 @@ mainboardinit ./auto.inc mainboardinit cpu/k8/disable_mmx_sse.inc # ### -### Setup RAM -### -#mainboardinit ram/ramtest.inc -#mainboardinit southbridge/amd/amd8111/smbus.inc -#mainboardinit sdram/generic_dump_spd.inc -# -### ### Include the secondary Configuration files ### northbridge amd/amdk8 @@ -175,5 +156,3 @@ end cpu k8 "cpu1" end - -option ENABLE_IOMMU=1 diff --git a/src/mainboard/tyan/s2880/mainboard.c b/src/mainboard/tyan/s2880/mainboard.c index 8efc0a5d1b..f6daa781eb 100644 --- a/src/mainboard/tyan/s2880/mainboard.c +++ b/src/mainboard/tyan/s2880/mainboard.c @@ -7,7 +7,7 @@ #include "chip.h" //#include <part/mainboard.h> //#include "lsi_scsi.c" -unsigned long initial_apicid[MAX_CPUS] = +unsigned long initial_apicid[CONFIG_MAX_CPUS] = { 0,1 }; diff --git a/src/mainboard/tyan/s2882/Config.lb b/src/mainboard/tyan/s2882/Config.lb index 8297ecff7d..013e968656 100644 --- a/src/mainboard/tyan/s2882/Config.lb +++ b/src/mainboard/tyan/s2882/Config.lb @@ -1,11 +1,8 @@ uses HAVE_MP_TABLE uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE -uses USE_NORMAL_IMAGE -uses AMD8111_DEV uses MAINBOARD uses ARCH -uses ENABLE_IOMMU # # ### @@ -45,15 +42,11 @@ ldscript /cpu/i386/entry32.lds ### Build our reset vector (This is where linuxBIOS is entered) ### if USE_FALLBACK_IMAGE - mainboardinit cpu/i386/reset16.inc - ldscript /cpu/i386/reset16.lds + mainboardinit cpu/i386/reset16.inc + ldscript /cpu/i386/reset16.lds else -# print "NO FALLBACK USED!" -end - -if USE_NORMAL_IMAGE - mainboardinit cpu/i386/reset32.inc - ldscript /cpu/i386/reset32.lds + mainboardinit cpu/i386/reset32.inc + ldscript /cpu/i386/reset32.lds end # #### Should this be in the northbridge code? @@ -86,7 +79,6 @@ mainboardinit cpu/k8/earlymtrr.inc # if USE_FALLBACK_IMAGE mainboardinit ./failover.inc -# mainboardinit southbridge/amd/amd8111/cmos_boot_failover.inc end # @@ -107,10 +99,6 @@ mainboardinit arch/i386/lib/console.inc ### ##option MAXIMUM_CONSOLE_LOGLEVEL=7 #default MAXIMUM_CONSOLE_LOGLEVEL=7 -#option DISABLE_WATCHDOG= (MAXIMUM_CONSOLE_LOGLEVEL >= 8) -#if DISABLE_WATCHDOG -# mainboardinit southbridgeamd/amd8111/disable_watchdog.inc -#end # #if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end # @@ -144,13 +132,6 @@ mainboardinit ./auto.inc mainboardinit cpu/k8/disable_mmx_sse.inc # ### -### Setup RAM -### -#mainboardinit ram/ramtest.inc -#mainboardinit southbridge/amd/amd8111/smbus.inc -#mainboardinit sdram/generic_dump_spd.inc -# -### ### Include the secondary Configuration files ### northbridge amd/amdk8 @@ -174,5 +155,3 @@ end cpu k8 "cpu1" end - -option ENABLE_IOMMU=1 diff --git a/src/mainboard/tyan/s2882/mainboard.c b/src/mainboard/tyan/s2882/mainboard.c index 0862c87ac0..d9acaf2384 100644 --- a/src/mainboard/tyan/s2882/mainboard.c +++ b/src/mainboard/tyan/s2882/mainboard.c @@ -7,7 +7,7 @@ #include "chip.h" //#include <part/mainboard.h> //#include "lsi_scsi.c" -unsigned long initial_apicid[MAX_CPUS] = +unsigned long initial_apicid[CONFIG_MAX_CPUS] = { 0,1 }; diff --git a/src/mainboard/tyan/s2885/Config.lb b/src/mainboard/tyan/s2885/Config.lb index 81a72f728f..f3f3081591 100644 --- a/src/mainboard/tyan/s2885/Config.lb +++ b/src/mainboard/tyan/s2885/Config.lb @@ -1,11 +1,8 @@ uses HAVE_MP_TABLE uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE -uses USE_NORMAL_IMAGE -uses AMD8111_DEV uses MAINBOARD uses ARCH -uses ENABLE_IOMMU # # ### @@ -46,15 +43,11 @@ ldscript /cpu/i386/entry32.lds ### Build our reset vector (This is where linuxBIOS is entered) ### if USE_FALLBACK_IMAGE - mainboardinit cpu/i386/reset16.inc - ldscript /cpu/i386/reset16.lds + mainboardinit cpu/i386/reset16.inc + ldscript /cpu/i386/reset16.lds else -# print "NO FALLBACK USED!" -end - -if USE_NORMAL_IMAGE - mainboardinit cpu/i386/reset32.inc - ldscript /cpu/i386/reset32.lds + mainboardinit cpu/i386/reset32.inc + ldscript /cpu/i386/reset32.lds end # #### Should this be in the northbridge code? @@ -87,7 +80,6 @@ mainboardinit cpu/k8/earlymtrr.inc # if USE_FALLBACK_IMAGE mainboardinit ./failover.inc -# mainboardinit southbridge/amd/amd8111/cmos_boot_failover.inc end # @@ -108,10 +100,6 @@ mainboardinit arch/i386/lib/console.inc ### ##option MAXIMUM_CONSOLE_LOGLEVEL=7 #default MAXIMUM_CONSOLE_LOGLEVEL=7 -#option DISABLE_WATCHDOG= (MAXIMUM_CONSOLE_LOGLEVEL >= 8) -#if DISABLE_WATCHDOG -# mainboardinit southbridgeamd/amd8111/disable_watchdog.inc -#end # #if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end # @@ -145,13 +133,6 @@ mainboardinit ./auto.inc mainboardinit cpu/k8/disable_mmx_sse.inc # ### -### Setup RAM -### -#mainboardinit ram/ramtest.inc -#mainboardinit southbridge/amd/amd8111/smbus.inc -#mainboardinit sdram/generic_dump_spd.inc -# -### ### Include the secondary Configuration files ### northbridge amd/amdk8 @@ -178,5 +159,3 @@ end cpu k8 "cpu1" end -option ENABLE_IOMMU=0 - diff --git a/src/mainboard/tyan/s2885/mainboard.c b/src/mainboard/tyan/s2885/mainboard.c index af8c1ad479..524cb80ab2 100644 --- a/src/mainboard/tyan/s2885/mainboard.c +++ b/src/mainboard/tyan/s2885/mainboard.c @@ -7,7 +7,7 @@ #include "chip.h" //#include <part/mainboard.h> //#include "lsi_scsi.c" -unsigned long initial_apicid[MAX_CPUS] = +unsigned long initial_apicid[CONFIG_MAX_CPUS] = { 0,1 }; |