diff options
Diffstat (limited to 'src/mainboard')
32 files changed, 105 insertions, 358 deletions
diff --git a/src/mainboard/agami/aruma/cache_as_ram_auto.c b/src/mainboard/agami/aruma/cache_as_ram_auto.c index b820c52aef..8d9e13cb45 100644 --- a/src/mainboard/agami/aruma/cache_as_ram_auto.c +++ b/src/mainboard/agami/aruma/cache_as_ram_auto.c @@ -204,7 +204,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) }; int needs_reset; - unsigned cpu_reset = 0; unsigned bsp_apicid = 0; struct mem_controller ctrl[8]; unsigned nodes; @@ -253,6 +252,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) memreset_setup(); sdram_initialize(nodes, ctrl); - post_cache_as_ram(cpu_reset); + post_cache_as_ram(); } diff --git a/src/mainboard/amd/serengeti_leopard/Config.lb b/src/mainboard/amd/serengeti_leopard/Config.lb index b6ee7180ec..ea92f8e201 100644 --- a/src/mainboard/amd/serengeti_leopard/Config.lb +++ b/src/mainboard/amd/serengeti_leopard/Config.lb @@ -117,8 +117,6 @@ if HAVE_ACPI_TABLES end end -object reset.o - if USE_DCACHE_RAM if CONFIG_USE_INIT diff --git a/src/mainboard/amd/serengeti_leopard/cache_as_ram_auto.c b/src/mainboard/amd/serengeti_leopard/cache_as_ram_auto.c index b81caf0406..965e439f49 100644 --- a/src/mainboard/amd/serengeti_leopard/cache_as_ram_auto.c +++ b/src/mainboard/amd/serengeti_leopard/cache_as_ram_auto.c @@ -10,21 +10,13 @@ //use by raminit #define K8_4RANK_DIMM_SUPPORT 1 -//use bu init_cpus -#if 0 - #define ENABLE_APIC_EXT_ID 1 - #define APIC_ID_OFFSET 0x10 - #define LIFT_BSP_APIC_ID 0 -#else - #define ENABLE_APIC_EXT_ID 0 -#endif - //used by incoherent_ht //#define K8_SCAN_PCI_BUS 1 //#define K8_ALLOCATE_IO_RANGE 1 #include <stdint.h> #include <device/pci_def.h> +#include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> #include <arch/romcc_io.h> @@ -33,7 +25,6 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" #if 0 static void post_code(uint8_t value) { @@ -47,7 +38,6 @@ static void post_code(uint8_t value) { #endif #include <cpu/amd/model_fxx_rev.h> -#include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" @@ -66,43 +56,11 @@ static void post_code(uint8_t value) { #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" +#include "northbridge/amd/amdk8/incoherent_ht.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -static void hard_reset(void) -{ - device_t dev; - unsigned sblnk = get_sblnk(); - - /* Find the device */ -#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE - dev = PCI_DEV(node_link_to_bus(0, sblnk), 2 + HT_CHAIN_END_UNITID_BASE - 1, 3); -#else - dev = PCI_DEV(node_link_to_bus(0, sblnk), 4 + HT_CHAIN_UNITID_BASE - 1, 3); -#endif - - set_bios_reset(); - - /* enable cf9 */ - pci_write_config8(dev, 0x41, 0xf1); - /* reset */ - outb(0x0e, 0x0cf9); -} -static void soft_reset(void) -{ - device_t dev; - unsigned sblnk = get_sblnk(); - - /* Find the device */ -#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE - dev = PCI_DEV(node_link_to_bus(0, sblnk), 2 + HT_CHAIN_END_UNITID_BASE - 1, 0); -#else - dev = PCI_DEV(node_link_to_bus(0, sblnk), 4 + HT_CHAIN_UNITID_BASE - 1, 0); -#endif - - set_bios_reset(); - pci_write_config8(dev, 0x47, 1); -} +#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" static void memreset_setup(void) { @@ -254,7 +212,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) }; int needs_reset; - unsigned cpu_reset = 0; unsigned bsp_apicid = 0; struct mem_controller ctrl[8]; @@ -296,7 +253,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) if (needs_reset) { print_info("ht reset -\r\n"); - soft_reset(); + soft_reset(); } allow_all_aps_stop(bsp_apicid); @@ -327,6 +284,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) dump_pci_devices(); #endif - post_cache_as_ram(cpu_reset); + post_cache_as_ram(); } diff --git a/src/mainboard/arima/hdama/Config.lb b/src/mainboard/arima/hdama/Config.lb index 8b38b0a95b..3f709dff8c 100644 --- a/src/mainboard/arima/hdama/Config.lb +++ b/src/mainboard/arima/hdama/Config.lb @@ -45,7 +45,6 @@ arch i386 end driver mainboard.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -object reset.o ## ## Romcc output diff --git a/src/mainboard/broadcom/blast/cache_as_ram_auto.c b/src/mainboard/broadcom/blast/cache_as_ram_auto.c index 37c1fd79dc..3ed4001a9f 100644 --- a/src/mainboard/broadcom/blast/cache_as_ram_auto.c +++ b/src/mainboard/broadcom/blast/cache_as_ram_auto.c @@ -190,7 +190,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) }; int needs_reset; - unsigned cpu_reset = 0; unsigned bsp_apicid = 0; struct mem_controller ctrl[8]; @@ -269,6 +268,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) dump_pci_devices(); #endif - post_cache_as_ram(cpu_reset); + post_cache_as_ram(); } diff --git a/src/mainboard/tyan/s2850/Config.lb b/src/mainboard/tyan/s2850/Config.lb index 1916fa70c3..e227bc1542 100644 --- a/src/mainboard/tyan/s2850/Config.lb +++ b/src/mainboard/tyan/s2850/Config.lb @@ -44,7 +44,6 @@ driver mainboard.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -object reset.o if USE_DCACHE_RAM diff --git a/src/mainboard/tyan/s2850/cache_as_ram_auto.c b/src/mainboard/tyan/s2850/cache_as_ram_auto.c index ba01699c07..5ca8561ea7 100644 --- a/src/mainboard/tyan/s2850/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2850/cache_as_ram_auto.c @@ -47,31 +47,7 @@ static void post_code(uint8_t value) { #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -static void hard_reset(void) -{ - device_t dev; - - /* Find the device */ - dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3); - - set_bios_reset(); - - /* enable cf9 */ - pci_write_config8(dev, 0x41, 0xf1); - /* reset */ - outb(0x0e, 0x0cf9); -} - -static void soft_reset(void) -{ - device_t dev; - - /* Find the device */ - dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0); - - set_bios_reset(); - pci_write_config8(dev, 0x47, 1); -} +#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" static void memreset_setup(void) { @@ -200,7 +176,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) }; int needs_reset; - unsigned cpu_reset = 0; if (bist == 0) { init_cpus(cpu_init_detectedx); @@ -235,5 +210,5 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) memreset_setup(); sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); - post_cache_as_ram(cpu_reset); + post_cache_as_ram(); } diff --git a/src/mainboard/tyan/s2875/Config.lb b/src/mainboard/tyan/s2875/Config.lb index b1052752fb..13596a2bec 100644 --- a/src/mainboard/tyan/s2875/Config.lb +++ b/src/mainboard/tyan/s2875/Config.lb @@ -44,7 +44,6 @@ driver mainboard.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -object reset.o if USE_DCACHE_RAM diff --git a/src/mainboard/tyan/s2875/cache_as_ram_auto.c b/src/mainboard/tyan/s2875/cache_as_ram_auto.c index 43ccb2702e..4126f49448 100644 --- a/src/mainboard/tyan/s2875/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2875/cache_as_ram_auto.c @@ -36,32 +36,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) - -static void hard_reset(void) -{ - device_t dev; - - /* Find the device */ - dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3); - - set_bios_reset(); - - /* enable cf9 */ - pci_write_config8(dev, 0x41, 0xf1); - /* reset */ - outb(0x0e, 0x0cf9); -} - -static void soft_reset(void) -{ - device_t dev; - - /* Find the device */ - dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0); - - set_bios_reset(); - pci_write_config8(dev, 0x47, 1); -} +#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" static void memreset_setup(void) { @@ -198,7 +173,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) }; int needs_reset; - unsigned cpu_reset = 0; if (bist == 0) { init_cpus(cpu_init_detectedx); @@ -231,6 +205,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) memreset_setup(); sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); - post_cache_as_ram(cpu_reset); + post_cache_as_ram(); } diff --git a/src/mainboard/tyan/s2880/Config.lb b/src/mainboard/tyan/s2880/Config.lb index 9d7e015b32..d6f907f387 100644 --- a/src/mainboard/tyan/s2880/Config.lb +++ b/src/mainboard/tyan/s2880/Config.lb @@ -44,7 +44,6 @@ driver mainboard.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -object reset.o if USE_DCACHE_RAM diff --git a/src/mainboard/tyan/s2880/cache_as_ram_auto.c b/src/mainboard/tyan/s2880/cache_as_ram_auto.c index 3808e83bbf..ab73876184 100644 --- a/src/mainboard/tyan/s2880/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2880/cache_as_ram_auto.c @@ -37,31 +37,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -static void hard_reset(void) -{ - device_t dev; - - /* Find the device */ - dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3); - - set_bios_reset(); - - /* enable cf9 */ - pci_write_config8(dev, 0x41, 0xf1); - /* reset */ - outb(0x0e, 0x0cf9); -} - -static void soft_reset(void) -{ - device_t dev; - - /* Find the device */ - dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0); - - set_bios_reset(); - pci_write_config8(dev, 0x47, 1); -} +#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" static void memreset_setup(void) { @@ -197,7 +173,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) }; int needs_reset; - unsigned cpu_reset = 0; if (bist == 0) { init_cpus(cpu_init_detectedx); @@ -232,5 +207,5 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) memreset_setup(); sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); - post_cache_as_ram(cpu_reset); + post_cache_as_ram(); } diff --git a/src/mainboard/tyan/s2881/Config.lb b/src/mainboard/tyan/s2881/Config.lb index 3b0cd33dd7..598f9b4a36 100644 --- a/src/mainboard/tyan/s2881/Config.lb +++ b/src/mainboard/tyan/s2881/Config.lb @@ -44,7 +44,6 @@ driver mainboard.o object get_bus_conf.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -object reset.o if USE_DCACHE_RAM if CONFIG_USE_INIT diff --git a/src/mainboard/tyan/s2881/cache_as_ram_auto.c b/src/mainboard/tyan/s2881/cache_as_ram_auto.c index 77dd978856..67a32140ad 100644 --- a/src/mainboard/tyan/s2881/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2881/cache_as_ram_auto.c @@ -42,31 +42,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -static void hard_reset(void) -{ - device_t dev; - - /* Find the device */ - dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 3); - - set_bios_reset(); - - /* enable cf9 */ - pci_write_config8(dev, 0x41, 0xf1); - /* reset */ - outb(0x0e, 0x0cf9); -} - -static void soft_reset(void) -{ - device_t dev; - - /* Find the device */ - dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 0); - - set_bios_reset(); - pci_write_config8(dev, 0x47, 1); -} +#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" static void memreset_setup(void) { @@ -185,7 +161,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) }; int needs_reset; - unsigned cpu_reset = 0; unsigned bsp_apicid = 0; struct mem_controller ctrl[8]; @@ -234,5 +209,5 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) sdram_initialize(nodes, ctrl); - post_cache_as_ram(cpu_reset); + post_cache_as_ram(); } diff --git a/src/mainboard/tyan/s2882/Config.lb b/src/mainboard/tyan/s2882/Config.lb index 8b173bd6d6..42c193be58 100644 --- a/src/mainboard/tyan/s2882/Config.lb +++ b/src/mainboard/tyan/s2882/Config.lb @@ -44,7 +44,6 @@ driver mainboard.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -object reset.o if USE_DCACHE_RAM diff --git a/src/mainboard/tyan/s2882/cache_as_ram_auto.c b/src/mainboard/tyan/s2882/cache_as_ram_auto.c index 967f068d51..c31181a8e2 100644 --- a/src/mainboard/tyan/s2882/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2882/cache_as_ram_auto.c @@ -36,31 +36,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -static void hard_reset(void) -{ - device_t dev; - - /* Find the device */ - dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3); - - set_bios_reset(); - - /* enable cf9 */ - pci_write_config8(dev, 0x41, 0xf1); - /* reset */ - outb(0x0e, 0x0cf9); -} - -static void soft_reset(void) -{ - device_t dev; - - /* Find the device */ - dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0); - - set_bios_reset(); - pci_write_config8(dev, 0x47, 1); -} +#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" static void memreset_setup(void) { @@ -200,7 +176,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) }; int needs_reset; - unsigned cpu_reset = 0; if (bist == 0) { init_cpus(cpu_init_detectedx); @@ -235,6 +210,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) memreset_setup(); sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); - post_cache_as_ram(cpu_reset); + post_cache_as_ram(); } diff --git a/src/mainboard/tyan/s2885/Config.lb b/src/mainboard/tyan/s2885/Config.lb index 37b0d90522..2a035a35ab 100644 --- a/src/mainboard/tyan/s2885/Config.lb +++ b/src/mainboard/tyan/s2885/Config.lb @@ -44,7 +44,6 @@ driver mainboard.o object get_bus_conf.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -object reset.o if USE_DCACHE_RAM diff --git a/src/mainboard/tyan/s2885/cache_as_ram_auto.c b/src/mainboard/tyan/s2885/cache_as_ram_auto.c index 7b2ccfaa14..0c5792565c 100644 --- a/src/mainboard/tyan/s2885/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2885/cache_as_ram_auto.c @@ -36,31 +36,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -static void hard_reset(void) -{ - device_t dev; - - /* Find the device */ - dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 3); - - set_bios_reset(); - - /* enable cf9 */ - pci_write_config8(dev, 0x41, 0xf1); - /* reset */ - outb(0x0e, 0x0cf9); -} - -static void soft_reset(void) -{ - device_t dev; - - /* Find the device */ - dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 0); - - set_bios_reset(); - pci_write_config8(dev, 0x47, 1); -} +#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" static void memreset_setup(void) { @@ -185,7 +161,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) }; int needs_reset; - unsigned cpu_reset = 0; unsigned bsp_apicid = 0; struct mem_controller ctrl[8]; @@ -234,6 +209,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) memreset_setup(); sdram_initialize(nodes, ctrl); - post_cache_as_ram(cpu_reset); + post_cache_as_ram(); } diff --git a/src/mainboard/tyan/s2891/Config.lb b/src/mainboard/tyan/s2891/Config.lb index 9c460066c9..67c7b3c8a9 100644 --- a/src/mainboard/tyan/s2891/Config.lb +++ b/src/mainboard/tyan/s2891/Config.lb @@ -237,7 +237,7 @@ chip northbridge/amd/amdk8/root_complex io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 off # Keyboard + device pnp 2e.5 on # Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 @@ -314,7 +314,7 @@ chip northbridge/amd/amdk8/root_complex # chip drivers/ati/ragexl chip drivers/pci/onboard device pci 7.0 on end - # register "rom_address" = "0xfff80000" #for 512K + # register "rom_address" = "0xfff80000" #for 512K register "rom_address" = "0xfff00000" #for 1M end end diff --git a/src/mainboard/tyan/s2891/Options.lb b/src/mainboard/tyan/s2891/Options.lb index e87a4df341..9018364663 100644 --- a/src/mainboard/tyan/s2891/Options.lb +++ b/src/mainboard/tyan/s2891/Options.lb @@ -54,6 +54,7 @@ uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses K8_HW_MEM_HOLE_SIZEK +uses K8_HT_FREQ_1G_SUPPORT uses USE_DCACHE_RAM uses DCACHE_RAM_BASE @@ -66,6 +67,13 @@ uses LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM +uses HT_CHAIN_UNITID_BASE +uses HT_CHAIN_END_UNITID_BASE +uses K8_SB_HT_CHAIN_ON_BUS0 +uses SB_HT_CHAIN_UNITID_OFFSET_ONLY + +uses CONFIG_LB_MEM_TOPK + ## ROM_SIZE is the size of boot ROM that this board will use. #512K bytes #default ROM_SIZE=524288 @@ -131,6 +139,22 @@ default CONFIG_LOGICAL_CPUS=1 #1G memory hole default K8_HW_MEM_HOLE_SIZEK=0x100000 +#Opteron K8 1G HT Support +default K8_HT_FREQ_1G_SUPPORT=1 + +##HT Unit ID offset, default is 1, the typical one +default HT_CHAIN_UNITID_BASE=0x0 + +##real SB Unit ID, default is 0x20, mean dont touch it at last +#default HT_CHAIN_END_UNITID_BASE=0x0 + +#make the SB HT chain on bus 0, default is not (0) +default K8_SB_HT_CHAIN_ON_BUS0=2 + +##only offset for SB chain?, default is yes(1) +default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 + + #BTEXT Console #default CONFIG_CONSOLE_BTEXT=1 @@ -144,9 +168,9 @@ default CONFIG_PCI_ROM_RUN=1 default USE_DCACHE_RAM=1 default DCACHE_RAM_BASE=0xcf000 default DCACHE_RAM_SIZE=0x1000 -default CONFIG_USE_INIT=1 +default CONFIG_USE_INIT=0 -default ENABLE_APIC_EXT_ID=1 +default ENABLE_APIC_EXT_ID=0 default APIC_ID_OFFSET=0x10 default LIFT_BSP_APIC_ID=0 diff --git a/src/mainboard/tyan/s2891/cache_as_ram_auto.c b/src/mainboard/tyan/s2891/cache_as_ram_auto.c index 61edc58cd2..1bc29d9304 100644 --- a/src/mainboard/tyan/s2891/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2891/cache_as_ram_auto.c @@ -42,25 +42,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -static void hard_reset(void) -{ - set_bios_reset(); - - /* full reset */ - outb(0x0a, 0x0cf9); - outb(0x0e, 0x0cf9); -} - -static void soft_reset(void) -{ - set_bios_reset(); -#if 1 - /* link reset */ - outb(0x02, 0x0cf9); - outb(0x06, 0x0cf9); -#endif -} - static void memreset_setup(void) { } @@ -197,7 +178,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) }; int needs_reset; - unsigned cpu_reset = 0; unsigned bsp_apicid = 0; struct mem_controller ctrl[8]; @@ -246,5 +226,5 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) memreset_setup(); sdram_initialize(nodes, ctrl); - post_cache_as_ram(cpu_reset); + post_cache_as_ram(); } diff --git a/src/mainboard/tyan/s2891/get_bus_conf.c b/src/mainboard/tyan/s2891/get_bus_conf.c index 92fefa6a0c..3462a5f557 100644 --- a/src/mainboard/tyan/s2891/get_bus_conf.c +++ b/src/mainboard/tyan/s2891/get_bus_conf.c @@ -152,9 +152,10 @@ void get_bus_conf(void) else { printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn+ 0x0e); - bus_8131_0 = bus_ck804_5+1; } + bus_8131_0 = (pci1234[1] >> 16) & 0xff; + /* 8131-1 */ dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0)); if (dev) { diff --git a/src/mainboard/tyan/s2891/resourcemap.c b/src/mainboard/tyan/s2891/resourcemap.c index c55d95bb99..625e19f11c 100644 --- a/src/mainboard/tyan/s2891/resourcemap.c +++ b/src/mainboard/tyan/s2891/resourcemap.c @@ -186,7 +186,7 @@ static void setup_s2891_resource_map(void) * This field defines the end of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000, +// PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000, PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, @@ -216,7 +216,7 @@ static void setup_s2891_resource_map(void) * This field defines the start of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033, +// PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033, PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000, diff --git a/src/mainboard/tyan/s2892/Config.lb b/src/mainboard/tyan/s2892/Config.lb index dcb0c45abf..6fa8e5d44a 100644 --- a/src/mainboard/tyan/s2892/Config.lb +++ b/src/mainboard/tyan/s2892/Config.lb @@ -313,7 +313,8 @@ chip northbridge/amd/amdk8/root_complex # chip drivers/ati/ragexl chip drivers/pci/onboard device pci 6.0 on end - register "rom_address" = "0xfff80000" + # register "rom_address" = "0xfff80000" #for 512K + register "rom_address" = "0xfff00000" #for 1M end chip drivers/pci/onboard device pci 8.0 on end diff --git a/src/mainboard/tyan/s2892/Options.lb b/src/mainboard/tyan/s2892/Options.lb index a8bac76536..7000126a5d 100644 --- a/src/mainboard/tyan/s2892/Options.lb +++ b/src/mainboard/tyan/s2892/Options.lb @@ -54,18 +54,24 @@ uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses K8_HW_MEM_HOLE_SIZEK +uses K8_HT_FREQ_1G_SUPPORT uses USE_DCACHE_RAM uses DCACHE_RAM_BASE uses DCACHE_RAM_SIZE uses CONFIG_USE_INIT +uses HT_CHAIN_UNITID_BASE +uses HT_CHAIN_END_UNITID_BASE +uses K8_SB_HT_CHAIN_ON_BUS0 +uses SB_HT_CHAIN_UNITID_OFFSET_ONLY + ## ROM_SIZE is the size of boot ROM that this board will use. #512K bytes -default ROM_SIZE=524288 +#default ROM_SIZE=524288 #1M bytes -#default ROM_SIZE=1048576 +default ROM_SIZE=1048576 ## @@ -125,6 +131,21 @@ default CONFIG_LOGICAL_CPUS=1 #1G memory hole default K8_HW_MEM_HOLE_SIZEK=0x100000 +#Opteron K8 1G HT Support +default K8_HT_FREQ_1G_SUPPORT=1 + +##HT Unit ID offset, default is 1, the typical one +default HT_CHAIN_UNITID_BASE=0x0 + +##real SB Unit ID, default is 0x20, mean dont touch it at last +#default HT_CHAIN_END_UNITID_BASE=0x0 + +#make the SB HT chain on bus 0, default is not (0) +default K8_SB_HT_CHAIN_ON_BUS0=2 + +##only offset for SB chain?, default is yes(1) +default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 + #BTEXT Console #default CONFIG_CONSOLE_BTEXT=1 @@ -138,8 +159,7 @@ default CONFIG_PCI_ROM_RUN=1 default USE_DCACHE_RAM=1 default DCACHE_RAM_BASE=0xcf000 default DCACHE_RAM_SIZE=0x1000 -default CONFIG_USE_INIT=1 - +default CONFIG_USE_INIT=0 ## ## Build code to setup a generic IOAPIC diff --git a/src/mainboard/tyan/s2892/cache_as_ram_auto.c b/src/mainboard/tyan/s2892/cache_as_ram_auto.c index 3bb7fb3d83..1936563518 100644 --- a/src/mainboard/tyan/s2892/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2892/cache_as_ram_auto.c @@ -36,25 +36,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -static void hard_reset(void) -{ - set_bios_reset(); - - /* full reset */ - outb(0x0a, 0x0cf9); - outb(0x0e, 0x0cf9); -} - -static void soft_reset(void) -{ - set_bios_reset(); -#if 1 - /* link reset */ - outb(0x02, 0x0cf9); - outb(0x06, 0x0cf9); -#endif -} - static void memreset_setup(void) { } @@ -210,7 +191,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) }; int needs_reset; - unsigned cpu_reset = 0; if (bist == 0) { init_cpus(cpu_init_detectedx); @@ -246,5 +226,5 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) memreset_setup(); sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); - post_cache_as_ram(cpu_reset); + post_cache_as_ram(); } diff --git a/src/mainboard/tyan/s2892/get_bus_conf.c b/src/mainboard/tyan/s2892/get_bus_conf.c index 92fefa6a0c..6086aa5ff5 100644 --- a/src/mainboard/tyan/s2892/get_bus_conf.c +++ b/src/mainboard/tyan/s2892/get_bus_conf.c @@ -152,9 +152,9 @@ void get_bus_conf(void) else { printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn+ 0x0e); - bus_8131_0 = bus_ck804_5+1; } + bus_8131_0 = (pci1234[1] >> 16) & 0xff; /* 8131-1 */ dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0)); if (dev) { diff --git a/src/mainboard/tyan/s2895/Options.lb b/src/mainboard/tyan/s2895/Options.lb index 49b0e0b0de..c3f8ba3f8c 100644 --- a/src/mainboard/tyan/s2895/Options.lb +++ b/src/mainboard/tyan/s2895/Options.lb @@ -64,12 +64,17 @@ uses ENABLE_APIC_EXT_ID uses APIC_ID_OFFSET uses LIFT_BSP_APIC_ID +uses HT_CHAIN_UNITID_BASE +uses HT_CHAIN_END_UNITID_BASE +uses K8_SB_HT_CHAIN_ON_BUS0 +uses SB_HT_CHAIN_UNITID_OFFSET_ONLY + ## ROM_SIZE is the size of boot ROM that this board will use. #512K bytes -default ROM_SIZE=524288 +#default ROM_SIZE=524288 #1M bytes -#default ROM_SIZE=1048576 +default ROM_SIZE=1048576 ## ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use @@ -134,6 +139,18 @@ default K8_HW_MEM_HOLE_SIZEK=0x100000 #Opteron K8 1G HT Support default K8_HT_FREQ_1G_SUPPORT=1 +##HT Unit ID offset, default is 1, the typical one +default HT_CHAIN_UNITID_BASE=0x0 + +##real SB Unit ID, default is 0x20, mean dont touch it at last +#default HT_CHAIN_END_UNITID_BASE=0x0 + +#make the SB HT chain on bus 0, default is not (0) +default K8_SB_HT_CHAIN_ON_BUS0=2 + +##only offset for SB chain?, default is yes(1) +default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 + #VGA default CONFIG_CONSOLE_VGA=1 default CONFIG_PCI_ROM_RUN=1 @@ -144,7 +161,7 @@ default CONFIG_PCI_ROM_RUN=1 default USE_DCACHE_RAM=1 default DCACHE_RAM_BASE=0xcf000 default DCACHE_RAM_SIZE=0x1000 -default CONFIG_USE_INIT=1 +default CONFIG_USE_INIT=0 default ENABLE_APIC_EXT_ID=1 default APIC_ID_OFFSET=0x10 diff --git a/src/mainboard/tyan/s2895/cache_as_ram_auto.c b/src/mainboard/tyan/s2895/cache_as_ram_auto.c index 1ae0c9e5d1..00bf1a6c23 100644 --- a/src/mainboard/tyan/s2895/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2895/cache_as_ram_auto.c @@ -50,25 +50,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1) -static void hard_reset(void) -{ - set_bios_reset(); - - /* full reset */ - outb(0x0a, 0x0cf9); - outb(0x0e, 0x0cf9); -} - -static void soft_reset(void) -{ - set_bios_reset(); -#if 1 - /* link reset */ - outb(0x02, 0x0cf9); - outb(0x06, 0x0cf9); -#endif -} - static void memreset_setup(void) { } @@ -239,7 +220,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) }; int needs_reset; - unsigned cpu_reset = 0; unsigned bsp_apicid = 0; struct mem_controller ctrl[8]; @@ -288,5 +268,5 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) memreset_setup(); sdram_initialize(nodes, ctrl); - post_cache_as_ram(cpu_reset); + post_cache_as_ram(); } diff --git a/src/mainboard/tyan/s4880/Config.lb b/src/mainboard/tyan/s4880/Config.lb index 74c5542f87..54fc432d72 100644 --- a/src/mainboard/tyan/s4880/Config.lb +++ b/src/mainboard/tyan/s4880/Config.lb @@ -43,7 +43,6 @@ arch i386 end driver mainboard.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -object reset.o if USE_DCACHE_RAM if CONFIG_USE_INIT diff --git a/src/mainboard/tyan/s4880/cache_as_ram_auto.c b/src/mainboard/tyan/s4880/cache_as_ram_auto.c index 0165a1f8c2..1a16eff09f 100644 --- a/src/mainboard/tyan/s4880/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s4880/cache_as_ram_auto.c @@ -36,31 +36,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -static void hard_reset(void) -{ - device_t dev; - - /* Find the device */ - dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 3); - - set_bios_reset(); - - /* enable cf9 */ - pci_write_config8(dev, 0x41, 0xf1); - /* reset */ - outb(0x0e, 0x0cf9); -} - -static void soft_reset(void) -{ - device_t dev; - - /* Find the device */ - dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 0); - - set_bios_reset(); - pci_write_config8(dev, 0x47, 1); -} +#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" static void memreset_setup(void) { @@ -247,7 +223,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) }; int needs_reset; - unsigned cpu_reset = 0; if (bist == 0) { init_cpus(cpu_init_detectedx); @@ -281,5 +256,5 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) memreset_setup(); sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); - post_cache_as_ram(cpu_reset); + post_cache_as_ram(); } diff --git a/src/mainboard/tyan/s4882/Config.lb b/src/mainboard/tyan/s4882/Config.lb index 1913120393..05e898814e 100644 --- a/src/mainboard/tyan/s4882/Config.lb +++ b/src/mainboard/tyan/s4882/Config.lb @@ -43,7 +43,6 @@ arch i386 end driver mainboard.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -object reset.o if USE_DCACHE_RAM if CONFIG_USE_INIT diff --git a/src/mainboard/tyan/s4882/cache_as_ram_auto.c b/src/mainboard/tyan/s4882/cache_as_ram_auto.c index 6f1ac8d098..2b463d4d27 100644 --- a/src/mainboard/tyan/s4882/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s4882/cache_as_ram_auto.c @@ -36,31 +36,8 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -static void hard_reset(void) -{ - device_t dev; - - /* Find the device */ - dev = PCI_DEV(node_link_to_bus(0, 1), 0x04, 3); - - set_bios_reset(); - - /* enable cf9 */ - pci_write_config8(dev, 0x41, 0xf1); - /* reset */ - outb(0x0e, 0x0cf9); -} -static void soft_reset(void) -{ - device_t dev; - - /* Find the device */ - dev = PCI_DEV(node_link_to_bus(0, 1), 0x04, 0); - - set_bios_reset(); - pci_write_config8(dev, 0x47, 1); -} +#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" static void memreset_setup(void) { @@ -222,7 +199,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) }; int needs_reset; - unsigned cpu_reset = 0; unsigned bsp_apicid = 0; struct mem_controller ctrl[8]; @@ -271,6 +247,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) memreset_setup(); sdram_initialize(nodes, ctrl); - post_cache_as_ram(cpu_reset); + post_cache_as_ram(); } |