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-rw-r--r--src/mainboard/amd/dinar/BiosCallOuts.c12
-rw-r--r--src/mainboard/amd/dinar/Makefile.inc3
-rw-r--r--src/mainboard/amd/dinar/OemCustomize.c52
-rw-r--r--src/mainboard/amd/dinar/buildOpts.c72
-rw-r--r--src/mainboard/amd/torpedo/OemCustomize.c18
-rw-r--r--src/mainboard/amd/torpedo/buildOpts.c78
-rw-r--r--src/mainboard/supermicro/h8qgi/BiosCallOuts.c3
-rw-r--r--src/mainboard/supermicro/h8qgi/Makefile.inc2
-rw-r--r--src/mainboard/supermicro/h8qgi/OemCustomize.c69
-rw-r--r--src/mainboard/supermicro/h8qgi/buildOpts.c120
-rw-r--r--src/mainboard/supermicro/h8scm/BiosCallOuts.c3
-rw-r--r--src/mainboard/supermicro/h8scm/Makefile.inc2
-rw-r--r--src/mainboard/supermicro/h8scm/OemCustomize.c70
-rw-r--r--src/mainboard/supermicro/h8scm/buildOpts.c121
-rw-r--r--src/mainboard/tyan/s8226/BiosCallOuts.c3
-rw-r--r--src/mainboard/tyan/s8226/Makefile.inc2
-rw-r--r--src/mainboard/tyan/s8226/OemCustomize.c70
-rw-r--r--src/mainboard/tyan/s8226/buildOpts.c120
18 files changed, 287 insertions, 533 deletions
diff --git a/src/mainboard/amd/dinar/BiosCallOuts.c b/src/mainboard/amd/dinar/BiosCallOuts.c
index 210dc468f2..0b43f723e1 100644
--- a/src/mainboard/amd/dinar/BiosCallOuts.c
+++ b/src/mainboard/amd/dinar/BiosCallOuts.c
@@ -108,15 +108,3 @@ static AGESA_STATUS board_ReadSpd (UINT32 Func, UINTN Data, VOID *ConfigPtr)
return Status;
}
-
-static AGESA_STATUS OemInitPost(AMD_POST_PARAMS *InitPost)
-{
- InitPost->MemConfig.UmaMode = UMA_AUTO;
- InitPost->MemConfig.BottomIo = 0xE0;
- InitPost->MemConfig.UmaSize = 0xE0-0xC0;
- return AGESA_SUCCESS;
-}
-
-const struct OEM_HOOK OemCustomize = {
- .InitPost = OemInitPost,
-};
diff --git a/src/mainboard/amd/dinar/Makefile.inc b/src/mainboard/amd/dinar/Makefile.inc
index 9f27a84755..d7a5da6a59 100644
--- a/src/mainboard/amd/dinar/Makefile.inc
+++ b/src/mainboard/amd/dinar/Makefile.inc
@@ -17,12 +17,13 @@ romstage-y += buildOpts.c
romstage-y += BiosCallOuts.c
romstage-y += sb700_cfg.c
romstage-y += rd890_cfg.c
+romstage-y += OemCustomize.c
ramstage-y += buildOpts.c
ramstage-y += BiosCallOuts.c
ramstage-y += sb700_cfg.c
ramstage-y += rd890_cfg.c
-
+ramstage-y += OemCustomize.c
AGESA_PREFIX ?= $(src)/vendorcode/amd/agesa
AGESA_ROOT ?= $(AGESA_PREFIX)/$(if $(CONFIG_CPU_AMD_AGESA_FAMILY15),f15,\
diff --git a/src/mainboard/amd/dinar/OemCustomize.c b/src/mainboard/amd/dinar/OemCustomize.c
new file mode 100644
index 0000000000..84866dea5a
--- /dev/null
+++ b/src/mainboard/amd/dinar/OemCustomize.c
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <northbridge/amd/agesa/agesawrapper.h>
+#include <PlatformMemoryConfiguration.h>
+
+/*----------------------------------------------------------------------------------------
+ * CUSTOMER OVERIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+/*
+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ * use its default conservative settings.
+ */
+CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+ // Dinar has the following routing:
+ // CS0 M[B,A]_CLK_H/L[0]
+ // CS1 M[B,A]_CLK_H/L[2]
+ // CS2 M[B,A]_CLK_H/L[1]
+ // CS3 M[B,A]_CLK_H/L[3]
+ MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x01, 0x04, 0x02, 0x08, 0x00, 0x00),
+ NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
+ PSO_END
+};
+
+
+static AGESA_STATUS OemInitPost(AMD_POST_PARAMS *InitPost)
+{
+ InitPost->MemConfig.UmaMode = UMA_AUTO;
+ InitPost->MemConfig.BottomIo = 0xE0;
+ InitPost->MemConfig.UmaSize = 0xE0-0xC0;
+ return AGESA_SUCCESS;
+}
+
+const struct OEM_HOOK OemCustomize = {
+ .InitPost = OemInitPost,
+};
diff --git a/src/mainboard/amd/dinar/buildOpts.c b/src/mainboard/amd/dinar/buildOpts.c
index f69f005391..6ac5ed826c 100644
--- a/src/mainboard/amd/dinar/buildOpts.c
+++ b/src/mainboard/amd/dinar/buildOpts.c
@@ -400,75 +400,3 @@ CONST DEVICE_CAP_OVERRIDE ROMDATA MaranelloOverrideDevCap[2] =
#include "cpuLateInit.h"
#include "GnbInterfaceStub.h"
#include "PlatformInstall.h"
-
-/*----------------------------------------------------------------------------------------
- * CUSTOMER OVERIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-/*
- * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- * use its default conservative settings.
- */
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
- //
- // The following macros are supported (use comma to separate macros):
- //
- // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
- // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
- // AGESA will base on this value to disable unused MemClk to save power.
- // Example:
- // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
- // Bit AM3/S1g3 pin name
- // 0 M[B,A]_CLK_H/L[0]
- // 1 M[B,A]_CLK_H/L[1]
- // 2 M[B,A]_CLK_H/L[2]
- // 3 M[B,A]_CLK_H/L[3]
- // 4 M[B,A]_CLK_H/L[4]
- // 5 M[B,A]_CLK_H/L[5]
- // 6 M[B,A]_CLK_H/L[6]
- // 7 M[B,A]_CLK_H/L[7]
- // And platform has the following routing:
- // CS0 M[B,A]_CLK_H/L[4]
- // CS1 M[B,A]_CLK_H/L[2]
- // CS2 M[B,A]_CLK_H/L[3]
- // CS3 M[B,A]_CLK_H/L[5]
- // Then platform can specify the following macro:
- // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
- //
- // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
- // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
- // AGESA will base on this value to tristate unused CKE to save power.
- //
- // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
- // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
- // AGESA will base on this value to tristate unused ODT pins to save power.
- //
- // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
- // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
- // AGESA will base on this value to tristate unused Chip select to save power.
- //
- // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
- // Specifies the number of DIMM slots per channel.
- //
- // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
- // Specifies the number of channels per socket.
- //
-
- // Dinar has the following routing:
- // CS0 M[B,A]_CLK_H/L[0]
- // CS1 M[B,A]_CLK_H/L[2]
- // CS2 M[B,A]_CLK_H/L[1]
- // CS3 M[B,A]_CLK_H/L[3]
- MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x01, 0x04, 0x02, 0x08, 0x00, 0x00),
- NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
- PSO_END
-};
-
-/*
- * These tables are optional and may be used to adjust memory timing settings
- */
-#include "mm.h"
-#include "mn.h"
diff --git a/src/mainboard/amd/torpedo/OemCustomize.c b/src/mainboard/amd/torpedo/OemCustomize.c
index 19717b1dd4..2293039c25 100644
--- a/src/mainboard/amd/torpedo/OemCustomize.c
+++ b/src/mainboard/amd/torpedo/OemCustomize.c
@@ -18,6 +18,7 @@
#include <string.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <vendorcode/amd/agesa/f12/Proc/CPU/heapManager.h>
+#include <PlatformMemoryConfiguration.h>
#define FILECODE PROC_GNB_PCIE_FAMILY_0X12_F12PCIECOMPLEXCONFIG_FILECODE
@@ -161,6 +162,23 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
return AGESA_SUCCESS;
}
+/*----------------------------------------------------------------------------------------
+ * CUSTOMER OVERIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+/*
+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ * use its default conservative settings.
+ */
+CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+ NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
+ NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
+ PSO_END
+};
+
const struct OEM_HOOK OemCustomize = {
.InitEarly = OemInitEarly,
};
diff --git a/src/mainboard/amd/torpedo/buildOpts.c b/src/mainboard/amd/torpedo/buildOpts.c
index b42d9a1a45..9abc6512fd 100644
--- a/src/mainboard/amd/torpedo/buildOpts.c
+++ b/src/mainboard/amd/torpedo/buildOpts.c
@@ -236,81 +236,3 @@ CONST AP_MTRR_SETTINGS ROMDATA LlanoApMtrrSettingsList[] =
#include "GnbInterface.h"
#include "PlatformInstall.h"
-/*----------------------------------------------------------------------------------------
- * CUSTOMER OVERIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-/*
- * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- * use its default conservative settings.
- */
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
- //
- // The following macros are supported (use comma to separate macros):
- //
- // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
- // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
- // AGESA will base on this value to disable unused MemClk to save power.
- // Example:
- // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
- // Bit AM3/S1g3 pin name
- // 0 M[B,A]_CLK_H/L[0]
- // 1 M[B,A]_CLK_H/L[1]
- // 2 M[B,A]_CLK_H/L[2]
- // 3 M[B,A]_CLK_H/L[3]
- // 4 M[B,A]_CLK_H/L[4]
- // 5 M[B,A]_CLK_H/L[5]
- // 6 M[B,A]_CLK_H/L[6]
- // 7 M[B,A]_CLK_H/L[7]
- // And platform has the following routing:
- // CS0 M[B,A]_CLK_H/L[4]
- // CS1 M[B,A]_CLK_H/L[2]
- // CS2 M[B,A]_CLK_H/L[3]
- // CS3 M[B,A]_CLK_H/L[5]
- // Then platform can specify the following macro:
- // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
- //
- // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
- // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
- // AGESA will base on this value to tristate unused CKE to save power.
- //
- // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
- // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
- // AGESA will base on this value to tristate unused ODT pins to save power.
- //
- // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
- // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
- // AGESA will base on this value to tristate unused Chip select to save power.
- //
- // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
- // Specifies the number of DIMM slots per channel.
- //
- // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
- // Specifies the number of Chip selects per channel.
- //
- // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
- // Specifies the number of channels per socket.
- //
- // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
- // Specifies DDR bus speed of channel ChannelID on socket SocketID.
- //
- // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
- // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
- //
- // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
- // Byte6Seed, Byte7Seed, ByteEccSeed)
- // Specifies the write leveling seed for a channel of a socket.
- //
- NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
- NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
- PSO_END
-};
-
-/*
- * These tables are optional and may be used to adjust memory timing settings
- */
-#include "mm.h"
-#include "mn.h"
diff --git a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c
index ebd1307cf0..c56833420e 100644
--- a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c
+++ b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c
@@ -102,6 +102,3 @@ static AGESA_STATUS board_ReadSpd (UINT32 Func, UINTN Data, VOID *ConfigPtr)
return Status;
}
-
-const struct OEM_HOOK OemCustomize = {
-};
diff --git a/src/mainboard/supermicro/h8qgi/Makefile.inc b/src/mainboard/supermicro/h8qgi/Makefile.inc
index 91ade34dbf..0868bc22d0 100644
--- a/src/mainboard/supermicro/h8qgi/Makefile.inc
+++ b/src/mainboard/supermicro/h8qgi/Makefile.inc
@@ -17,11 +17,13 @@ romstage-y += rd890_cfg.c
romstage-y += sb700_cfg.c
romstage-y += buildOpts.c
romstage-y += BiosCallOuts.c
+romstage-y += OemCustomize.c
ramstage-y += rd890_cfg.c
ramstage-y += sb700_cfg.c
ramstage-y += buildOpts.c
ramstage-y += BiosCallOuts.c
+ramstage-y += OemCustomize.c
AGESA_PREFIX ?= $(src)/vendorcode/amd/agesa
CIMX_PREFIX ?= $(src)/vendorcode/amd/cimx
diff --git a/src/mainboard/supermicro/h8qgi/OemCustomize.c b/src/mainboard/supermicro/h8qgi/OemCustomize.c
new file mode 100644
index 0000000000..9f340c639d
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/OemCustomize.c
@@ -0,0 +1,69 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <northbridge/amd/agesa/agesawrapper.h>
+#include <PlatformMemoryConfiguration.h>
+
+/*----------------------------------------------------------------------------------------
+ * CUSTOMER OVERIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+//reference BKDG Table87: works
+#define F15_WL_SEED 0x3B //family15 BKDG recommand 3B RDIMM, 1A UDIMM.
+#define SEED_A 0x54
+#define SEED_B 0x4D
+#define SEED_C 0x45
+#define SEED_D 0x40
+
+#define F10_WL_SEED 0x3B //family10 BKDG recommand 3B RDIMM, 1A UDIMM.
+//4B 41 51
+
+/*
+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ * use its default conservative settings.
+ */
+CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+ WRITE_LEVELING_SEED(
+ ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS,
+ F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED,
+ F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED,
+ F15_WL_SEED),
+
+ HW_RXEN_SEED(
+ ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
+ SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
+ SEED_A),
+ HW_RXEN_SEED(
+ ANY_SOCKET, CHANNEL_B, ALL_DIMMS,
+ SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B,
+ SEED_B),
+ HW_RXEN_SEED(
+ ANY_SOCKET, CHANNEL_C, ALL_DIMMS,
+ SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C,
+ SEED_C),
+ HW_RXEN_SEED(
+ ANY_SOCKET, CHANNEL_D, ALL_DIMMS,
+ SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D,
+ SEED_D),
+
+ NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), //max 3
+ PSO_END
+};
+
+const struct OEM_HOOK OemCustomize = {
+};
diff --git a/src/mainboard/supermicro/h8qgi/buildOpts.c b/src/mainboard/supermicro/h8qgi/buildOpts.c
index f6e654a233..14ca2f7107 100644
--- a/src/mainboard/supermicro/h8qgi/buildOpts.c
+++ b/src/mainboard/supermicro/h8qgi/buildOpts.c
@@ -18,7 +18,6 @@
#include "AGESA.h"
#include "CommonReturns.h"
#include "AdvancedApi.h"
-#include <PlatformMemoryConfiguration.h>
#include "Filecode.h"
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
@@ -449,122 +448,3 @@ CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] =
#include "MaranelloInstall.h"
-/*----------------------------------------------------------------------------------------
- * CUSTOMER OVERIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-//reference BKDG Table87: works
-#define F15_WL_SEED 0x3B //family15 BKDG recommand 3B RDIMM, 1A UDIMM.
-#define SEED_A 0x54
-#define SEED_B 0x4D
-#define SEED_C 0x45
-#define SEED_D 0x40
-
-#define F10_WL_SEED 0x3B //family10 BKDG recommand 3B RDIMM, 1A UDIMM.
-//4B 41 51
-
-/*
- * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- * use its default conservative settings.
- */
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
- //
- // The following macros are supported (use comma to separate macros):
- //
- // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
- // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
- // AGESA will base on this value to disable unused MemClk to save power.
- // Example:
- // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
- // Bit AM3/S1g3 pin name
- // 0 M[B,A]_CLK_H/L[0]
- // 1 M[B,A]_CLK_H/L[1]
- // 2 M[B,A]_CLK_H/L[2]
- // 3 M[B,A]_CLK_H/L[3]
- // 4 M[B,A]_CLK_H/L[4]
- // 5 M[B,A]_CLK_H/L[5]
- // 6 M[B,A]_CLK_H/L[6]
- // 7 M[B,A]_CLK_H/L[7]
- // And platform has the following routing:
- // CS0 M[B,A]_CLK_H/L[4]
- // CS1 M[B,A]_CLK_H/L[2]
- // CS2 M[B,A]_CLK_H/L[3]
- // CS3 M[B,A]_CLK_H/L[5]
- // Then platform can specify the following macro:
- // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
- //
- // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
- // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
- // AGESA will base on this value to tristate unused CKE to save power.
- //
- // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
- // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
- // AGESA will base on this value to tristate unused ODT pins to save power.
- //
- // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
- // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
- // AGESA will base on this value to tristate unused Chip select to save power.
- //
- // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
- // Specifies the number of DIMM slots per channel.
- //
- // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
- // Specifies the number of Chip selects per channel.
- //
- // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
- // Specifies the number of channels per socket.
- //
- // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
- // Specifies DDR bus speed of channel ChannelID on socket SocketID.
- //
- // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
- // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
- //
- // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
- // Byte6Seed, Byte7Seed, ByteEccSeed)
- // Specifies the write leveling seed for a channel of a socket.
- //
-
- /* Specifies the write leveling seed for a channel of a socket.
- * WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID,
- * Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed,
- * Byte4Seed, Byte5Seed, Byte6Seed, Byte7Seed,
- * ByteEccSeed)
- */
- WRITE_LEVELING_SEED(
- ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS,
- F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED,
- F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED,
- F15_WL_SEED),
-
- /* HW_RXEN_SEED(SocketID, ChannelID, DimmID,
- * Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed,
- * Byte4Seed, Byte5Seed, Byte6Seed, Byte7Seed, ByteEccSeed)
- */
- HW_RXEN_SEED(
- ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
- SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
- SEED_A),
- HW_RXEN_SEED(
- ANY_SOCKET, CHANNEL_B, ALL_DIMMS,
- SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B,
- SEED_B),
- HW_RXEN_SEED(
- ANY_SOCKET, CHANNEL_C, ALL_DIMMS,
- SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C,
- SEED_C),
- HW_RXEN_SEED(
- ANY_SOCKET, CHANNEL_D, ALL_DIMMS,
- SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D,
- SEED_D),
-
- NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), //max 3
- PSO_END
-};
-
-/*
- * These tables are optional and may be used to adjust memory timing settings
- */
diff --git a/src/mainboard/supermicro/h8scm/BiosCallOuts.c b/src/mainboard/supermicro/h8scm/BiosCallOuts.c
index d8696e6c35..2449b6c0e3 100644
--- a/src/mainboard/supermicro/h8scm/BiosCallOuts.c
+++ b/src/mainboard/supermicro/h8scm/BiosCallOuts.c
@@ -33,6 +33,3 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] =
{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
};
const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
-
-const struct OEM_HOOK OemCustomize = {
-};
diff --git a/src/mainboard/supermicro/h8scm/Makefile.inc b/src/mainboard/supermicro/h8scm/Makefile.inc
index 91ade34dbf..0868bc22d0 100644
--- a/src/mainboard/supermicro/h8scm/Makefile.inc
+++ b/src/mainboard/supermicro/h8scm/Makefile.inc
@@ -17,11 +17,13 @@ romstage-y += rd890_cfg.c
romstage-y += sb700_cfg.c
romstage-y += buildOpts.c
romstage-y += BiosCallOuts.c
+romstage-y += OemCustomize.c
ramstage-y += rd890_cfg.c
ramstage-y += sb700_cfg.c
ramstage-y += buildOpts.c
ramstage-y += BiosCallOuts.c
+ramstage-y += OemCustomize.c
AGESA_PREFIX ?= $(src)/vendorcode/amd/agesa
CIMX_PREFIX ?= $(src)/vendorcode/amd/cimx
diff --git a/src/mainboard/supermicro/h8scm/OemCustomize.c b/src/mainboard/supermicro/h8scm/OemCustomize.c
new file mode 100644
index 0000000000..634d06bf8b
--- /dev/null
+++ b/src/mainboard/supermicro/h8scm/OemCustomize.c
@@ -0,0 +1,70 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <northbridge/amd/agesa/agesawrapper.h>
+#include <PlatformMemoryConfiguration.h>
+
+/*----------------------------------------------------------------------------------------
+ * CUSTOMER OVERIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+//reference BKDG Table87: works
+#define F15_WL_SEED 0x3B //family15 BKDG recommand 3B RDIMM, 1A UDIMM.
+#define SEED_A 0x54
+#define SEED_B 0x4D
+#define SEED_C 0x45
+#define SEED_D 0x40
+
+#define F10_WL_SEED 0x3B //family10 BKDG recommand 3B RDIMM, 1A UDIMM.
+
+/*
+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ * use its default conservative settings.
+ * I am not sure whether DefaultPlatformMemoryConfiguration is necessary.
+ * If I comment out these code, H8SCM will still pass mem training.
+ */
+CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+ WRITE_LEVELING_SEED(
+ ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS,
+ F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED,
+ F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED,
+ F15_WL_SEED),
+
+ HW_RXEN_SEED(
+ ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
+ SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
+ SEED_A),
+ HW_RXEN_SEED(
+ ANY_SOCKET, CHANNEL_B, ALL_DIMMS,
+ SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B,
+ SEED_B),
+ HW_RXEN_SEED(
+ ANY_SOCKET, CHANNEL_C, ALL_DIMMS,
+ SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C,
+ SEED_C),
+ HW_RXEN_SEED(
+ ANY_SOCKET, CHANNEL_D, ALL_DIMMS,
+ SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D,
+ SEED_D),
+
+ NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), //max 3
+ PSO_END
+};
+
+const struct OEM_HOOK OemCustomize = {
+};
diff --git a/src/mainboard/supermicro/h8scm/buildOpts.c b/src/mainboard/supermicro/h8scm/buildOpts.c
index 140399922d..27166893ec 100644
--- a/src/mainboard/supermicro/h8scm/buildOpts.c
+++ b/src/mainboard/supermicro/h8scm/buildOpts.c
@@ -18,7 +18,6 @@
#include "AGESA.h"
#include "CommonReturns.h"
#include "AdvancedApi.h"
-#include <PlatformMemoryConfiguration.h>
#include "Filecode.h"
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
//#define OPTION_HW_DQS_REC_EN_TRAINING TRUE
@@ -353,123 +352,3 @@ CONST AP_MTRR_SETTINGS ROMDATA h8scm_ap_mtrr_list[] =
#include "SanMarinoInstall.h"
-/*----------------------------------------------------------------------------------------
- * CUSTOMER OVERIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-//reference BKDG Table87: works
-#define F15_WL_SEED 0x3B //family15 BKDG recommand 3B RDIMM, 1A UDIMM.
-#define SEED_A 0x54
-#define SEED_B 0x4D
-#define SEED_C 0x45
-#define SEED_D 0x40
-
-#define F10_WL_SEED 0x3B //family10 BKDG recommand 3B RDIMM, 1A UDIMM.
-
-/*
- * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- * use its default conservative settings.
- * I am not sure whether DefaultPlatformMemoryConfiguration is necessary.
- * If I comment out these code, H8SCM will still pass mem training.
- */
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
- //
- // The following macros are supported (use comma to separate macros):
- //
- // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
- // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
- // AGESA will base on this value to disable unused MemClk to save power.
- // Example:
- // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
- // Bit AM3/S1g3 pin name
- // 0 M[B,A]_CLK_H/L[0]
- // 1 M[B,A]_CLK_H/L[1]
- // 2 M[B,A]_CLK_H/L[2]
- // 3 M[B,A]_CLK_H/L[3]
- // 4 M[B,A]_CLK_H/L[4]
- // 5 M[B,A]_CLK_H/L[5]
- // 6 M[B,A]_CLK_H/L[6]
- // 7 M[B,A]_CLK_H/L[7]
- // And platform has the following routing:
- // CS0 M[B,A]_CLK_H/L[4]
- // CS1 M[B,A]_CLK_H/L[2]
- // CS2 M[B,A]_CLK_H/L[3]
- // CS3 M[B,A]_CLK_H/L[5]
- // Then platform can specify the following macro:
- // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
- //
- // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
- // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
- // AGESA will base on this value to tristate unused CKE to save power.
- //
- // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
- // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
- // AGESA will base on this value to tristate unused ODT pins to save power.
- //
- // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
- // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
- // AGESA will base on this value to tristate unused Chip select to save power.
- //
- // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
- // Specifies the number of DIMM slots per channel.
- //
- // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
- // Specifies the number of Chip selects per channel.
- //
- // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
- // Specifies the number of channels per socket.
- //
- // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
- // Specifies DDR bus speed of channel ChannelID on socket SocketID.
- //
- // DRAM_TECHNOLOGY(ANY_SOCKET, DDR3_TECHNOLOGY),
- // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
- //
- // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
- // Byte6Seed, Byte7Seed, ByteEccSeed)
- // Specifies the write leveling seed for a channel of a socket.
- //
-
- /* Specifies the write leveling seed for a channel of a socket.
- * WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID,
- * Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed,
- * Byte4Seed, Byte5Seed, Byte6Seed, Byte7Seed,
- * ByteEccSeed)
- */
- WRITE_LEVELING_SEED(
- ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS,
- F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED,
- F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED,
- F15_WL_SEED),
-
- /* HW_RXEN_SEED(SocketID, ChannelID, DimmID,
- * Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed,
- * Byte4Seed, Byte5Seed, Byte6Seed, Byte7Seed, ByteEccSeed)
- */
- HW_RXEN_SEED(
- ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
- SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
- SEED_A),
- HW_RXEN_SEED(
- ANY_SOCKET, CHANNEL_B, ALL_DIMMS,
- SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B,
- SEED_B),
- HW_RXEN_SEED(
- ANY_SOCKET, CHANNEL_C, ALL_DIMMS,
- SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C,
- SEED_C),
- HW_RXEN_SEED(
- ANY_SOCKET, CHANNEL_D, ALL_DIMMS,
- SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D,
- SEED_D),
-
- NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), //max 3
- PSO_END
-};
-
-/*
- * These tables are optional and may be used to adjust memory timing settings
- */
diff --git a/src/mainboard/tyan/s8226/BiosCallOuts.c b/src/mainboard/tyan/s8226/BiosCallOuts.c
index ef3849e714..0fa9742fc0 100644
--- a/src/mainboard/tyan/s8226/BiosCallOuts.c
+++ b/src/mainboard/tyan/s8226/BiosCallOuts.c
@@ -110,6 +110,3 @@ static AGESA_STATUS board_ReadSpd (UINT32 Func, UINTN Data, VOID *ConfigPtr)
return Status;
}
-
-const struct OEM_HOOK OemCustomize = {
-};
diff --git a/src/mainboard/tyan/s8226/Makefile.inc b/src/mainboard/tyan/s8226/Makefile.inc
index 91ade34dbf..0868bc22d0 100644
--- a/src/mainboard/tyan/s8226/Makefile.inc
+++ b/src/mainboard/tyan/s8226/Makefile.inc
@@ -17,11 +17,13 @@ romstage-y += rd890_cfg.c
romstage-y += sb700_cfg.c
romstage-y += buildOpts.c
romstage-y += BiosCallOuts.c
+romstage-y += OemCustomize.c
ramstage-y += rd890_cfg.c
ramstage-y += sb700_cfg.c
ramstage-y += buildOpts.c
ramstage-y += BiosCallOuts.c
+ramstage-y += OemCustomize.c
AGESA_PREFIX ?= $(src)/vendorcode/amd/agesa
CIMX_PREFIX ?= $(src)/vendorcode/amd/cimx
diff --git a/src/mainboard/tyan/s8226/OemCustomize.c b/src/mainboard/tyan/s8226/OemCustomize.c
new file mode 100644
index 0000000000..d3a8f4ba40
--- /dev/null
+++ b/src/mainboard/tyan/s8226/OemCustomize.c
@@ -0,0 +1,70 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <northbridge/amd/agesa/agesawrapper.h>
+#include <PlatformMemoryConfiguration.h>
+
+/*----------------------------------------------------------------------------------------
+ * CUSTOMER OVERIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+//reference BKDG Table87: works
+#define F15_WL_SEED 0x3B //family15 BKDG recommand 3B RDIMM, 1A UDIMM.
+#define SEED_A 0x54
+#define SEED_B 0x4D
+#define SEED_C 0x45
+#define SEED_D 0x40
+
+#define F10_WL_SEED 0x3B //family10 BKDG recommand 3B RDIMM, 1A UDIMM.
+//4B 41 51
+
+/*
+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ * use its default conservative settings.
+ */
+CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+
+ WRITE_LEVELING_SEED(
+ ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS,
+ F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED,
+ F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED,
+ F15_WL_SEED),
+
+ HW_RXEN_SEED(
+ ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
+ SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
+ SEED_A),
+ HW_RXEN_SEED(
+ ANY_SOCKET, CHANNEL_B, ALL_DIMMS,
+ SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B,
+ SEED_B),
+ HW_RXEN_SEED(
+ ANY_SOCKET, CHANNEL_C, ALL_DIMMS,
+ SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C,
+ SEED_C),
+ HW_RXEN_SEED(
+ ANY_SOCKET, CHANNEL_D, ALL_DIMMS,
+ SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D,
+ SEED_D),
+
+ NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 3), //max 3
+ PSO_END
+};
+
+const struct OEM_HOOK OemCustomize = {
+};
diff --git a/src/mainboard/tyan/s8226/buildOpts.c b/src/mainboard/tyan/s8226/buildOpts.c
index 4a3d808e6e..b4622109f6 100644
--- a/src/mainboard/tyan/s8226/buildOpts.c
+++ b/src/mainboard/tyan/s8226/buildOpts.c
@@ -18,7 +18,6 @@
#include "AGESA.h"
#include "CommonReturns.h"
#include "AdvancedApi.h"
-#include <PlatformMemoryConfiguration.h>
#include "Filecode.h"
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
@@ -449,122 +448,3 @@ CONST AP_MTRR_SETTINGS ROMDATA s8226_ap_mtrr_list[] =
#include "SanMarinoInstall.h"
-/*----------------------------------------------------------------------------------------
- * CUSTOMER OVERIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-//reference BKDG Table87: works
-#define F15_WL_SEED 0x3B //family15 BKDG recommand 3B RDIMM, 1A UDIMM.
-#define SEED_A 0x54
-#define SEED_B 0x4D
-#define SEED_C 0x45
-#define SEED_D 0x40
-
-#define F10_WL_SEED 0x3B //family10 BKDG recommand 3B RDIMM, 1A UDIMM.
-//4B 41 51
-
-/*
- * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- * use its default conservative settings.
- */
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
- //
- // The following macros are supported (use comma to separate macros):
- //
- // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
- // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
- // AGESA will base on this value to disable unused MemClk to save power.
- // Example:
- // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
- // Bit AM3/S1g3 pin name
- // 0 M[B,A]_CLK_H/L[0]
- // 1 M[B,A]_CLK_H/L[1]
- // 2 M[B,A]_CLK_H/L[2]
- // 3 M[B,A]_CLK_H/L[3]
- // 4 M[B,A]_CLK_H/L[4]
- // 5 M[B,A]_CLK_H/L[5]
- // 6 M[B,A]_CLK_H/L[6]
- // 7 M[B,A]_CLK_H/L[7]
- // And platform has the following routing:
- // CS0 M[B,A]_CLK_H/L[4]
- // CS1 M[B,A]_CLK_H/L[2]
- // CS2 M[B,A]_CLK_H/L[3]
- // CS3 M[B,A]_CLK_H/L[5]
- // Then platform can specify the following macro:
- // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
- //
- // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
- // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
- // AGESA will base on this value to tristate unused CKE to save power.
- //
- // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
- // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
- // AGESA will base on this value to tristate unused ODT pins to save power.
- //
- // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
- // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
- // AGESA will base on this value to tristate unused Chip select to save power.
- //
- // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
- // Specifies the number of DIMM slots per channel.
- //
- // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
- // Specifies the number of Chip selects per channel.
- //
- // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
- // Specifies the number of channels per socket.
- //
- // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
- // Specifies DDR bus speed of channel ChannelID on socket SocketID.
- //
- // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
- // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
- //
- // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
- // Byte6Seed, Byte7Seed, ByteEccSeed)
- // Specifies the write leveling seed for a channel of a socket.
- //
-
- /* Specifies the write leveling seed for a channel of a socket.
- * WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID,
- * Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed,
- * Byte4Seed, Byte5Seed, Byte6Seed, Byte7Seed,
- * ByteEccSeed)
- */
- WRITE_LEVELING_SEED(
- ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS,
- F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED,
- F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED,
- F15_WL_SEED),
-
- /* HW_RXEN_SEED(SocketID, ChannelID, DimmID,
- * Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed,
- * Byte4Seed, Byte5Seed, Byte6Seed, Byte7Seed, ByteEccSeed)
- */
- HW_RXEN_SEED(
- ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
- SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
- SEED_A),
- HW_RXEN_SEED(
- ANY_SOCKET, CHANNEL_B, ALL_DIMMS,
- SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B,
- SEED_B),
- HW_RXEN_SEED(
- ANY_SOCKET, CHANNEL_C, ALL_DIMMS,
- SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C,
- SEED_C),
- HW_RXEN_SEED(
- ANY_SOCKET, CHANNEL_D, ALL_DIMMS,
- SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D,
- SEED_D),
-
- NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 3), //max 3
- PSO_END
-};
-
-/*
- * These tables are optional and may be used to adjust memory timing settings
- */
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-23 21:46:05 +0000