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-rw-r--r--src/mainboard/emulation/qemu-riscv/memlayout.ld1
-rw-r--r--src/mainboard/emulation/spike-riscv/memlayout.ld2
-rw-r--r--src/mainboard/lowrisc/nexys4ddr/memlayout.ld2
3 files changed, 2 insertions, 3 deletions
diff --git a/src/mainboard/emulation/qemu-riscv/memlayout.ld b/src/mainboard/emulation/qemu-riscv/memlayout.ld
index 8cc6d4126b..615d1f2b72 100644
--- a/src/mainboard/emulation/qemu-riscv/memlayout.ld
+++ b/src/mainboard/emulation/qemu-riscv/memlayout.ld
@@ -24,6 +24,5 @@ SECTIONS
ROMSTAGE(0x20000, 128K)
STACK(0x40000, 0x3ff00)
PRERAM_CBMEM_CONSOLE(0x80000, 8K)
- PAGETABLES(0x80000+8K, 60K)
RAMSTAGE(0x100000, 16M)
}
diff --git a/src/mainboard/emulation/spike-riscv/memlayout.ld b/src/mainboard/emulation/spike-riscv/memlayout.ld
index 8596723796..bae414ffd5 100644
--- a/src/mainboard/emulation/spike-riscv/memlayout.ld
+++ b/src/mainboard/emulation/spike-riscv/memlayout.ld
@@ -24,7 +24,7 @@ SECTIONS
DRAM_START(START)
BOOTBLOCK(START, 64K)
STACK(START + 8M, 4K)
- PAGETABLES(START + 8M + 4K, 60K)
+ /* hole at (START + 8M + 4K, 60K) */
ROMSTAGE(START + 8M + 64K, 128K)
PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K)
RAMSTAGE(START + 8M + 200K, 256K)
diff --git a/src/mainboard/lowrisc/nexys4ddr/memlayout.ld b/src/mainboard/lowrisc/nexys4ddr/memlayout.ld
index 0348c47366..86f3667556 100644
--- a/src/mainboard/lowrisc/nexys4ddr/memlayout.ld
+++ b/src/mainboard/lowrisc/nexys4ddr/memlayout.ld
@@ -26,6 +26,6 @@ SECTIONS
STACK(START + 8M, 64K)
ROMSTAGE(START + 8M + 64K, 128K)
PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K)
- PAGETABLES(START + 8M + 200K, 56K)
+ /* hole at (START + 8M + 200K, 56K) */
RAMSTAGE(START + 8M + 256K, 256K)
}