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-rw-r--r--src/mainboard/google/rambi/devicetree.cb3
-rw-r--r--src/mainboard/google/rambi/irqroute.h28
2 files changed, 16 insertions, 15 deletions
diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb
index c7bc0b66f2..1ebf1e8e3d 100644
--- a/src/mainboard/google/rambi/devicetree.cb
+++ b/src/mainboard/google/rambi/devicetree.cb
@@ -59,12 +59,13 @@ chip soc/intel/baytrail
device domain 0 on
device pci 00.0 on end # SoC router
device pci 02.0 on end # GFX
+ device pci 10.0 off end # MMC
device pci 11.0 off end # SDIO
device pci 12.0 on end # SD
device pci 13.0 on end # SATA
device pci 14.0 on end # XHCI
device pci 15.0 on end # LPE
- device pci 17.0 on end # MMC
+ device pci 17.0 on end # MMC45
device pci 18.0 on end # SIO_DMA1
device pci 18.1 on end # I2C1
device pci 18.2 on end # I2C2
diff --git a/src/mainboard/google/rambi/irqroute.h b/src/mainboard/google/rambi/irqroute.h
index b5c4f731ff..a4ec620174 100644
--- a/src/mainboard/google/rambi/irqroute.h
+++ b/src/mainboard/google/rambi/irqroute.h
@@ -5,20 +5,20 @@
#include <soc/pm.h>
#define PCI_DEV_PIRQ_ROUTES \
- PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, B, C, D), \
- PCI_DEV_PIRQ_ROUTE(SDIO_DEV, A, B, C, D), \
- PCI_DEV_PIRQ_ROUTE(SD_DEV, C, D, E, F), \
- PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \
- PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \
- PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, B, C, D), \
- PCI_DEV_PIRQ_ROUTE(MMC_DEV, D, E, F, G), \
- PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \
- PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, B, C, D), \
- PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, B, C, D), \
- PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \
- PCI_DEV_PIRQ_ROUTE(EHCI_DEV, A, B, C, D), \
- PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, C, D, E), \
- PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D)
+ PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(SDIO_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(SD_DEV, C, D, E, F), \
+ PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(MMC45_DEV, D, E, F, G), \
+ PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(EHCI_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, C, D, E), \
+ PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D)
#define PIRQ_PIC_ROUTES \
PIRQ_PIC(A, DISABLE), \