diff options
Diffstat (limited to 'src/mainboard')
383 files changed, 2209 insertions, 2209 deletions
diff --git a/src/mainboard/a-trend/Kconfig b/src/mainboard/a-trend/Kconfig index f5a379f84d..7cb53924dd 100644 --- a/src/mainboard/a-trend/Kconfig +++ b/src/mainboard/a-trend/Kconfig @@ -21,7 +21,7 @@ choice prompt "Mainboard model" depends on VENDOR_A_TREND - + source "src/mainboard/a-trend/atc-6220/Kconfig" source "src/mainboard/a-trend/atc-6240/Kconfig" diff --git a/src/mainboard/abit/Kconfig b/src/mainboard/abit/Kconfig index 982cc9eee7..1f704b84c3 100644 --- a/src/mainboard/abit/Kconfig +++ b/src/mainboard/abit/Kconfig @@ -21,7 +21,7 @@ choice prompt "Mainboard model" depends on VENDOR_ABIT - + source "src/mainboard/abit/be6-ii_v2_0/Kconfig" endchoice diff --git a/src/mainboard/amd/rumba/devicetree.cb b/src/mainboard/amd/rumba/devicetree.cb index 0c0c8f0c31..bc84dc0373 100644 --- a/src/mainboard/amd/rumba/devicetree.cb +++ b/src/mainboard/amd/rumba/devicetree.cb @@ -6,7 +6,7 @@ chip northbridge/amd/gx2 device apic 0 on end end end - device pci_domain 0 on + device pci_domain 0 on device pci 1.0 on end device pci 1.1 on end chip southbridge/amd/cs5536 diff --git a/src/mainboard/amd/rumba/irq_tables.c b/src/mainboard/amd/rumba/irq_tables.c index 598350b4b8..f751b481ca 100644 --- a/src/mainboard/amd/rumba/irq_tables.c +++ b/src/mainboard/amd/rumba/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up * diff --git a/src/mainboard/amd/rumba/mainboard.c b/src/mainboard/amd/rumba/mainboard.c index adb1786678..0e7bbb66e7 100644 --- a/src/mainboard/amd/rumba/mainboard.c +++ b/src/mainboard/amd/rumba/mainboard.c @@ -19,7 +19,7 @@ static void init(struct device *dev) { printk(BIOS_DEBUG, "AMD RUMBA ENTER %s\n", __func__); if (nicirq) { - printk(BIOS_DEBUG, "%s (%x,%x)SET PCI interrupt line to %d\n", + printk(BIOS_DEBUG, "%s (%x,%x)SET PCI interrupt line to %d\n", __func__, bus, devfn, nicirq); nic = dev_find_slot(bus, devfn); if (! nic){ diff --git a/src/mainboard/amd/rumba/romstage.c b/src/mainboard/amd/rumba/romstage.c index 813b009471..958cf3196c 100644 --- a/src/mainboard/amd/rumba/romstage.c +++ b/src/mainboard/amd/rumba/romstage.c @@ -35,7 +35,7 @@ static inline unsigned int fls(unsigned int x) return r; } -static void sdram_set_spd_registers(const struct mem_controller *ctrl) +static void sdram_set_spd_registers(const struct mem_controller *ctrl) { /* Total size of DIMM = 2^row address (byte 3) * 2^col address (byte 4) * * component Banks (byte 17) * module banks, side (byte 5) * @@ -86,7 +86,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) msr = rdmsr(0x20000019); msr.hi = 0x18000108; msr.lo = 0x696332a3; - wrmsr(0x20000019, msr); + wrmsr(0x20000019, msr); } @@ -122,7 +122,7 @@ static void main(unsigned long bist) }; SystemPreInit(); - + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); @@ -134,7 +134,7 @@ static void main(unsigned long bist) cpuRegInit(); print_err("done cpuRegInit\n"); - + sdram_initialize(1, memctrl); msr_init(); diff --git a/src/mainboard/amd/serengeti_cheetah/acpi/amd8111.asl b/src/mainboard/amd/serengeti_cheetah/acpi/amd8111.asl index b2474e2a20..77958b2063 100644 --- a/src/mainboard/amd/serengeti_cheetah/acpi/amd8111.asl +++ b/src/mainboard/amd/serengeti_cheetah/acpi/amd8111.asl @@ -4,17 +4,17 @@ //AMD8111 Name (APIC, Package (0x04) { - Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10},// 0x0004ffff : assusme 8131 is present - Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11}, - Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12}, + Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10},// 0x0004ffff : assusme 8131 is present + Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11}, + Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12}, Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13} }) Name (PICM, Package (0x04) { - Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00}, - Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00}, - Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00}, + Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00}, + Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00}, + Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00}, Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00} }) @@ -34,16 +34,16 @@ Store(Local0, Index (DeRefOf (Index (APIC, 1)), 0)) Store(Local0, Index (DeRefOf (Index (APIC, 2)), 0)) Store(Local0, Index (DeRefOf (Index (APIC, 3)), 0)) - + Store (0x00, ^DNCG) - + } - If (LNot (PICF)) { - Return (PICM) + If (LNot (PICF)) { + Return (PICM) } Else { - Return (APIC) + Return (APIC) } } @@ -57,7 +57,7 @@ OperationRegion (PIRQ, PCI_Config, 0x56, 0x02) Field (PIRQ, ByteAcc, Lock, Preserve) { - PIBA, 8, + PIBA, 8, PIDC, 8 } /* @@ -144,7 +144,7 @@ Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x13 }, Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x10 } }) - + Name (PICM, Package (0x0C) { Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //USB diff --git a/src/mainboard/amd/serengeti_cheetah/acpi/amd8111_isa.asl b/src/mainboard/amd/serengeti_cheetah/acpi/amd8111_isa.asl index 9d93e34e92..9e952c80bd 100644 --- a/src/mainboard/amd/serengeti_cheetah/acpi/amd8111_isa.asl +++ b/src/mainboard/amd/serengeti_cheetah/acpi/amd8111_isa.asl @@ -5,7 +5,7 @@ Device (ISA) { - /* lpc 0x00040000 */ + /* lpc 0x00040000 */ Method (_ADR, 0, NotSerialized) { Return (DADD(\_SB.PCI0.SBDN, 0x00010000)) @@ -15,11 +15,11 @@ Field (PIRY, ByteAcc, NoLock, Preserve) { Z000, 2, // Parallel Port Range - , 1, + , 1, ECP, 1, // ECP Enable FDC1, 1, // Floppy Drive Controller 1 FDC2, 1, // Floppy Drive Controller 2 - Offset (0x01), + Offset (0x01), Z001, 3, // Serial Port A Range SAEN, 1, // Serial Post A Enabled Z002, 3, // Serial Port B Range @@ -106,7 +106,7 @@ IO (Decode16, 0x0090, 0x0090, 0x01, 0x10) IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E) IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10) - IO (Decode16, 0x0B78, 0x0B78, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error + IO (Decode16, 0x0B78, 0x0B78, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error IO (Decode16, 0x0190, 0x0190, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error }) Method (_CRS, 0, NotSerialized) @@ -134,7 +134,7 @@ Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS }) - // Read the Video Memory length + // Read the Video Memory length CreateDWordField (BUF0, 0x14, CLEN) CreateDWordField (BUF0, 0x10, CBAS) diff --git a/src/mainboard/amd/serengeti_cheetah/acpi/amd8131.asl b/src/mainboard/amd/serengeti_cheetah/acpi/amd8131.asl index e209665e48..172f0bf9d1 100644 --- a/src/mainboard/amd/serengeti_cheetah/acpi/amd8131.asl +++ b/src/mainboard/amd/serengeti_cheetah/acpi/amd8131.asl @@ -1,7 +1,7 @@ /* * Copyright 2005 AMD */ - + Device (PG0A) { /* 8132 pcix bridge*/ @@ -19,60 +19,60 @@ Name (APIC, Package (0x14) { // Slot A - PIRQ BCDA - Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x19 }, //Slot 2 - Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1A }, - Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x1B }, + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x19 }, //Slot 2 + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1A }, + Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x1B }, Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x18 }, - + //Cypress Slot A - PIRQ BCDA Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x19 }, //? - Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x1A }, - Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x1B }, - Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x18 }, + Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x1A }, + Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x1B }, + Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x18 }, //Cypress Slot B - PIRQ CDAB Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x1A }, //? - Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x1B }, - Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x18 }, - Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x19 }, + Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x1B }, + Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x18 }, + Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x19 }, //Cypress Slot C - PIRQ DABC Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x1B }, //? - Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x18 }, - Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x19 }, - Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x1A }, + Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x18 }, + Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x19 }, + Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x1A }, //Cypress Slot D - PIRQ ABCD Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x18 }, //? - Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x19 }, - Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x1A }, + Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x19 }, + Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x1A }, Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x1B } }) Name (PICM, Package (0x14) { - Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 2 - Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 2 + Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0006FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0006FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0006FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0006FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0006FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0006FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, Package (0x04) { 0x0006FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 } }) Method (_PRT, 0, NotSerialized) @@ -100,15 +100,15 @@ { // Slot A - PIRQ ABCD Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x1F },// Slot 1 - Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x20 }, - Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x21 }, + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x20 }, + Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x21 }, Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x22 } }) Name (PICM, Package (0x04) { - Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1 - Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1 + Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 } }) Method (_PRT, 0, NotSerialized) diff --git a/src/mainboard/amd/serengeti_cheetah/acpi/amd8131_2.asl b/src/mainboard/amd/serengeti_cheetah/acpi/amd8131_2.asl index 163c0f6061..8b8bc9fab9 100644 --- a/src/mainboard/amd/serengeti_cheetah/acpi/amd8131_2.asl +++ b/src/mainboard/amd/serengeti_cheetah/acpi/amd8131_2.asl @@ -1,7 +1,7 @@ /* * Copyright 2005 AMD */ - + Device (PG0A) { /* 8132 pcix bridge*/ @@ -19,18 +19,18 @@ Name (APIC, Package (0x04) { // Slot A - PIRQ BCDA - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2 - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A }, + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2 + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A }, Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x001B }, - + }) Name (PICM, Package (0x04) { - Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2 - Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2 + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, }) Name (DNCG, Ones) @@ -40,7 +40,7 @@ If (LEqual (^DNCG, Ones)) { Multiply (HCIN, 0x0008, Local2) // GSI for 8132 is 4 so we get 8 Store (0x00, Local1) - While (LLess (Local1, 0x04)) + While (LLess (Local1, 0x04)) { // Update the GSI according to HCIN Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0) @@ -76,15 +76,15 @@ { // Slot A - PIRQ ABCD Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x001F },// Slot 1 - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 }, + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 }, Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x0022 } }) Name (PICM, Package (0x04) { - Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1 - Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1 + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 } }) diff --git a/src/mainboard/amd/serengeti_cheetah/acpi/amd8132_2.asl b/src/mainboard/amd/serengeti_cheetah/acpi/amd8132_2.asl index 75ef72343a..e5cfe3c951 100644 --- a/src/mainboard/amd/serengeti_cheetah/acpi/amd8132_2.asl +++ b/src/mainboard/amd/serengeti_cheetah/acpi/amd8132_2.asl @@ -1,7 +1,7 @@ /* * Copyright 2005 AMD */ - + Device (PG0A) { /* 8132 pcix bridge*/ @@ -19,18 +19,18 @@ Name (APIC, Package (0x04) { // Slot A - PIRQ BCDA - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2 - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A }, + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2 + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A }, Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x001B }, - + }) Name (PICM, Package (0x04) { - Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2 - Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2 + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, }) Name (DNCG, Ones) @@ -40,7 +40,7 @@ If (LEqual (^DNCG, Ones)) { Multiply (HCIN, 0x000e, Local2) // GSI for 8132 is 7 so we get 14 Store (0x00, Local1) - While (LLess (Local1, 0x04)) + While (LLess (Local1, 0x04)) { // Update the GSI according to HCIN Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0) @@ -76,15 +76,15 @@ { // Slot A - PIRQ ABCD Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x001F },// Slot 1 - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 }, + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 }, Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x0022 } }) Name (PICM, Package (0x04) { - Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1 - Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1 + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 } }) diff --git a/src/mainboard/amd/serengeti_cheetah/acpi/amd8151.asl b/src/mainboard/amd/serengeti_cheetah/acpi/amd8151.asl index 001d45b0fe..ce85502296 100644 --- a/src/mainboard/amd/serengeti_cheetah/acpi/amd8151.asl +++ b/src/mainboard/amd/serengeti_cheetah/acpi/amd8151.asl @@ -1,4 +1,4 @@ -// AMD8151 +// AMD8151 Device (AGPB) { Method (_ADR, 0, NotSerialized) @@ -8,16 +8,16 @@ Name (APIC, Package (0x04) { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 }, Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 } }) Name (PICM, Package (0x04) { - Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 } }) Method (_PRT, 0, NotSerialized) diff --git a/src/mainboard/amd/serengeti_cheetah/ap_romstage.c b/src/mainboard/amd/serengeti_cheetah/ap_romstage.c index c2b8e8c7b3..f132ec727c 100644 --- a/src/mainboard/amd/serengeti_cheetah/ap_romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/ap_romstage.c @@ -4,7 +4,7 @@ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 -#define SET_NB_CFG_54 1 +#define SET_NB_CFG_54 1 //used by raminit #define QRANK_DIMM_SUPPORT 1 diff --git a/src/mainboard/amd/serengeti_cheetah/devicetree.cb b/src/mainboard/amd/serengeti_cheetah/devicetree.cb index b9742b4a46..c1748697f4 100644 --- a/src/mainboard/amd/serengeti_cheetah/devicetree.cb +++ b/src/mainboard/amd/serengeti_cheetah/devicetree.cb @@ -6,7 +6,7 @@ chip northbridge/amd/amdk8/root_complex end device pci_domain 0 on chip northbridge/amd/amdk8 - device pci 18.0 on # northbridge + device pci 18.0 on # northbridge # devices on link 0, link 0 == LDT 0 chip southbridge/amd/amd8132 # the on/off keyword is mandatory @@ -56,7 +56,7 @@ chip northbridge/amd/amdk8/root_complex io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 - end + end device pnp 2e.8 off end # GPIO2 device pnp 2e.9 off end # GPIO3 device pnp 2e.a off end # ACPI @@ -120,7 +120,7 @@ chip northbridge/amd/amdk8/root_complex end # device pci 18.0 device pci 18.0 on end - device pci 18.0 on end + device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end diff --git a/src/mainboard/amd/serengeti_cheetah/dsdt.asl b/src/mainboard/amd/serengeti_cheetah/dsdt.asl index ee87023ff8..a549d70297 100644 --- a/src/mainboard/amd/serengeti_cheetah/dsdt.asl +++ b/src/mainboard/amd/serengeti_cheetah/dsdt.asl @@ -100,11 +100,11 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-K8", "AMDACPI", 100925440) Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) - Return (Local3) + Return (Local3) } #include "acpi/pci0_hc.asl" - + } Device (PCI1) { @@ -138,7 +138,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-K8", "AMDACPI", 100925440) Notify (\_SB.PCI0.PG0B, 0x02) } - Method (_L29, 0, NotSerialized) // GPIO25 (Suspend) - Pogo 0 Bridge A + Method (_L29, 0, NotSerialized) // GPIO25 (Suspend) - Pogo 0 Bridge A { Notify (\_SB.PCI0.PG0A, 0x02) } @@ -183,14 +183,14 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-K8", "AMDACPI", 100925440) OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100) Field (GRAM, ByteAcc, Lock, Preserve) { - Offset (0x10), + Offset (0x10), FLG0, 8 } OperationRegion (GSTS, SystemIO, 0xC028, 0x02) Field (GSTS, ByteAcc, NoLock, Preserve) { - , 4, + , 4, IRQR, 1 } diff --git a/src/mainboard/amd/serengeti_cheetah/fadt.c b/src/mainboard/amd/serengeti_cheetah/fadt.c index d4c6622847..6b6107070b 100644 --- a/src/mainboard/amd/serengeti_cheetah/fadt.c +++ b/src/mainboard/amd/serengeti_cheetah/fadt.c @@ -30,7 +30,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ // 3=Workstation,4=Enterprise Server, 7=Performance Server fadt->preferred_pm_profile=0x03; fadt->sci_int=9; - // disable system management mode by setting to 0: + // disable system management mode by setting to 0: fadt->smi_cmd = 0;//pm_base+0x2f; fadt->acpi_enable = 0xf0; fadt->acpi_disable = 0xf1; @@ -53,7 +53,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->gpe0_blk_len = 4; fadt->gpe1_blk_len = 8; fadt->gpe1_base = 16; - + fadt->cst_cnt = 0xe3; fadt->p_lvl2_lat = 101; fadt->p_lvl3_lat = 1001; @@ -66,7 +66,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->century = 0; // 0x7f to make rtc alrm work fadt->iapc_boot_arch = 0x3; // See table 5-11 fadt->flags = 0x25; - + fadt->res2 = 0; fadt->reset_reg.space_id = 1; diff --git a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c index 436044e69a..3674ff0076 100644 --- a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c +++ b/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c @@ -15,7 +15,7 @@ // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables struct mb_sysconf_t mb_sysconf; -static unsigned pci1234x[] = +static unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail 0x0000ff0, @@ -27,7 +27,7 @@ static unsigned pci1234x[] = // 0x0000ff0, // 0x0000ff0 }; -static unsigned hcdnx[] = +static unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, 0x20202020, @@ -88,17 +88,17 @@ void get_bus_conf(void) get_bus_conf_done = 1; sysconf.mb = &mb_sysconf; - + m = sysconf.mb; - sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for(i=0;i<sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; } - + get_sblk_pci1234(); - + sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff; m->sbdn3 = sysconf.hcdn[0] & 0xff; @@ -209,8 +209,8 @@ void get_bus_conf(void) /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS==1 apicid_base = get_apicid_base(3); -#else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; +#else + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif m->apicid_8111 = apicid_base+0; m->apicid_8132_1 = apicid_base+1; diff --git a/src/mainboard/amd/serengeti_cheetah/irq_tables.c b/src/mainboard/amd/serengeti_cheetah/irq_tables.c index d872b0a0db..637f980055 100644 --- a/src/mainboard/amd/serengeti_cheetah/irq_tables.c +++ b/src/mainboard/amd/serengeti_cheetah/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up @@ -13,11 +13,11 @@ #include "mb_sysconf.h" -static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, +static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; + pirq_info->bus = bus; pirq_info->devfn = devfn; pirq_info->irq[0].link = link0; @@ -50,7 +50,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) struct mb_sysconf_t *m; get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c - + m = sysconf.mb; /* Align the table to be 16 byte aligned. */ @@ -62,25 +62,25 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq = (void *)(addr); v = (uint8_t *)(addr); - + pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - + pirq->rtr_bus = m->bus_8111_0; pirq->rtr_devfn = ((sysconf.sbdn+1)<<3)|0; pirq->exclusive_irqs = 0; - + pirq->rtr_vendor = 0x1022; pirq->rtr_device = 0x746b; pirq->miniport_data = 0; memset(pirq->rfu, 0, sizeof(pirq->rfu)); - + pirq_info = (void *) ( &pirq->checksum + 1); slot_num = 0; - + { device_t dev; dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn+1,3)); @@ -126,11 +126,11 @@ unsigned long write_pirq_routing_table(unsigned long addr) j++; } - - pirq->size = 32 + 16 * slot_num; + + pirq->size = 32 + 16 * slot_num; for (i = 0; i < pirq->size; i++) - sum += v[i]; + sum += v[i]; sum = pirq->checksum - sum; diff --git a/src/mainboard/amd/serengeti_cheetah/mptable.c b/src/mainboard/amd/serengeti_cheetah/mptable.c index 2b2f65c39b..fe2f9440e2 100644 --- a/src/mainboard/amd/serengeti_cheetah/mptable.c +++ b/src/mainboard/amd/serengeti_cheetah/mptable.c @@ -101,8 +101,8 @@ static void *smp_write_config_table(void *v) } } - -/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + +/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_8111, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x1, m->apicid_8111, 0x1); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_8111, 0x2); diff --git a/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt b/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt index 41988c8ede..685cd7a2ce 100644 --- a/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt +++ b/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt @@ -6,7 +6,7 @@ At this time, For acpi support We got The developers need to change for different MB -Change dsdt.asl, according to MB layout +Change dsdt.asl, according to MB layout pci1, pci2, pci3, pci4, ...., pci8 if there is HT-IO board, may use pci2.asl.... to create ssdt2.c, and ssdt3,c and ssdt4.c, ....ssdt8.c @@ -17,7 +17,7 @@ Change acpi_tables.c Regarding pci bridge apic and pic need to modify entries amd8111.asl and amd8131.asl and amd8151.asl.... acording to your MB laybout, it is like that in mptable.c -About other chipsets, need to develop their special asl such as +About other chipsets, need to develop their special asl such as ck804.asl --- NB ck804 bcm5785.asl or bcm5780.asl ---- Serverworks HT1000/HT2000 @@ -27,4 +27,4 @@ use c to delele hex file yhlu 09/18/2005 - + diff --git a/src/mainboard/amd/serengeti_cheetah/resourcemap.c b/src/mainboard/amd/serengeti_cheetah/resourcemap.c index 9b19503360..be11b689da 100644 --- a/src/mainboard/amd/serengeti_cheetah/resourcemap.c +++ b/src/mainboard/amd/serengeti_cheetah/resourcemap.c @@ -143,7 +143,7 @@ static void setup_mb_resource_map(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, @@ -199,7 +199,7 @@ static void setup_mb_resource_map(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -207,7 +207,7 @@ static void setup_mb_resource_map(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003, diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index 00d4b3b21a..6fcaa90875 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -1,7 +1,7 @@ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 -#define SET_NB_CFG_54 1 +#define SET_NB_CFG_54 1 //used by raminit #define QRANK_DIMM_SUPPORT 1 @@ -107,7 +107,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" /* tyan does not want the default */ -#include "resourcemap.c" +#include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" @@ -186,7 +186,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) console_init(); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - + /* Halt if there was a built in self test failure */ report_bist_failure(bist); @@ -201,21 +201,21 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); #if CONFIG_MEM_TRAIN_SEQ == 1 - set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram + set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS==1 // It is said that we should start core1 after all core0 launched - /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, + /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, - * (there may be apic id conflicts in that case) + * (there may be apic id conflicts in that case) */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif - + /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn @@ -249,7 +249,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); + print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } diff --git a/src/mainboard/amd/serengeti_cheetah/ssdt2.asl b/src/mainboard/amd/serengeti_cheetah/ssdt2.asl index 582ef97621..791454c190 100644 --- a/src/mainboard/amd/serengeti_cheetah/ssdt2.asl +++ b/src/mainboard/amd/serengeti_cheetah/ssdt2.asl @@ -28,16 +28,16 @@ DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) // BUS ? Second HT Chain Name (HCIN, 0xcc) // HC2 0x01 - + Name (_UID, 0xdd) // HC 0x03 - Name (_HID, "PNP0A03") + Name (_HID, "PNP0A03") Method (_ADR, 0, NotSerialized) //Fake bus should be 0 { Return (DADD(GHCN(HCIN), 0x00000000)) } - + Method (_BBN, 0, NotSerialized) { Return (GBUS (GHCN(HCIN), GHCL(HCIN))) @@ -45,7 +45,7 @@ DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) Method (_STA, 0, NotSerialized) { - Return (\_SB.GHCE(HCIN)) + Return (\_SB.GHCE(HCIN)) } Method (_CRS, 0, NotSerialized) diff --git a/src/mainboard/amd/serengeti_cheetah/ssdt3.asl b/src/mainboard/amd/serengeti_cheetah/ssdt3.asl index 583e945740..28fe5f45a3 100644 --- a/src/mainboard/amd/serengeti_cheetah/ssdt3.asl +++ b/src/mainboard/amd/serengeti_cheetah/ssdt3.asl @@ -28,16 +28,16 @@ DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) // BUS ? Second HT Chain Name (HCIN, 0xcc) // HC2 0x01 - + Name (_UID, 0xdd) // HC 0x03 - Name (_HID, "PNP0A03") + Name (_HID, "PNP0A03") Method (_ADR, 0, NotSerialized) //Fake bus should be 0 { Return (DADD(GHCN(HCIN), 0x00000000)) } - + Method (_BBN, 0, NotSerialized) { Return (GBUS (GHCN(HCIN), GHCL(HCIN))) @@ -45,7 +45,7 @@ DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) Method (_STA, 0, NotSerialized) { - Return (\_SB.GHCE(HCIN)) + Return (\_SB.GHCE(HCIN)) } Method (_CRS, 0, NotSerialized) diff --git a/src/mainboard/amd/serengeti_cheetah/ssdt4.asl b/src/mainboard/amd/serengeti_cheetah/ssdt4.asl index fd7224d17a..93abb7f520 100644 --- a/src/mainboard/amd/serengeti_cheetah/ssdt4.asl +++ b/src/mainboard/amd/serengeti_cheetah/ssdt4.asl @@ -28,16 +28,16 @@ DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) // BUS ? Second HT Chain Name (HCIN, 0xcc) // HC2 0x01 - + Name (_UID, 0xdd) // HC 0x03 - Name (_HID, "PNP0A03") + Name (_HID, "PNP0A03") Method (_ADR, 0, NotSerialized) //Fake bus should be 0 { Return (DADD(GHCN(HCIN), 0x00000000)) } - + Method (_BBN, 0, NotSerialized) { Return (GBUS (GHCN(HCIN), GHCL(HCIN))) @@ -45,7 +45,7 @@ DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) Method (_STA, 0, NotSerialized) { - Return (\_SB.GHCE(HCIN)) + Return (\_SB.GHCE(HCIN)) } Method (_CRS, 0, NotSerialized) diff --git a/src/mainboard/arima/Kconfig b/src/mainboard/arima/Kconfig index d1979b00a2..8895433a55 100644 --- a/src/mainboard/arima/Kconfig +++ b/src/mainboard/arima/Kconfig @@ -1,7 +1,7 @@ choice prompt "Mainboard model" depends on VENDOR_ARIMA - + source "src/mainboard/arima/hdama/Kconfig" endchoice diff --git a/src/mainboard/arima/hdama/debug.c b/src/mainboard/arima/hdama/debug.c index 0db327c5c6..a6f0d558a8 100644 --- a/src/mainboard/arima/hdama/debug.c +++ b/src/mainboard/arima/hdama/debug.c @@ -12,8 +12,8 @@ static void print_debug_pci_dev(unsigned dev) static void print_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -32,7 +32,7 @@ static void dump_pci_device(unsigned dev) int i; print_debug_pci_dev(dev); print_debug("\n"); - + for(i = 0; i <= 255; i++) { unsigned char val; if ((i & 0x0f) == 0) { @@ -51,8 +51,8 @@ static void dump_pci_device(unsigned dev) static void dump_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -77,10 +77,10 @@ static void dump_spd_registers(int controllers, const struct mem_controller *ctr device = ctrl[n].channel0[i]; if (device) { int j; - print_debug("dimm: "); + print_debug("dimm: "); print_debug_hex8(n); print_debug_char('.'); - print_debug_hex8(i); + print_debug_hex8(i); print_debug(".0: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { @@ -109,10 +109,10 @@ static void dump_spd_registers(int controllers, const struct mem_controller *ctr device = ctrl[n].channel1[i]; if (device) { int j; - print_debug("dimm: "); + print_debug("dimm: "); print_debug_hex8(n); print_debug_char('.'); - print_debug_hex8(i); + print_debug_hex8(i); print_debug(".1: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { diff --git a/src/mainboard/arima/hdama/devicetree.cb b/src/mainboard/arima/hdama/devicetree.cb index a812814782..0ab47a4f0b 100644 --- a/src/mainboard/arima/hdama/devicetree.cb +++ b/src/mainboard/arima/hdama/devicetree.cb @@ -6,14 +6,14 @@ chip northbridge/amd/amdk8/root_complex end device pci_domain 0 on chip northbridge/amd/amdk8 - device pci 18.0 on # northbridge - # devices on link 0, link 0 == LDT 0 + device pci 18.0 on # northbridge + # devices on link 0, link 0 == LDT 0 chip southbridge/amd/amd8131 # the on/off keyword is mandatory device pci 0.0 on # PCIX bridge ## On board NIC A #chip drivers/generic/generic - # device pci 3.0 on + # device pci 3.0 on # irq 0 = 0x13 # end #end @@ -31,7 +31,7 @@ chip northbridge/amd/amdk8/root_complex # irq 2 = 0x13 # irq 3 = 0x10 # end - #end + #end ## PCI Slot 4 #chip drivers/generic/generic # device pci 2.0 on @@ -40,7 +40,7 @@ chip northbridge/amd/amdk8/root_complex # irq 2 = 0x10 # irq 3 = 0x11 # end - #end + #end end device pci 0.1 on end # IOAPIC device pci 1.0 on # PCIX bridge @@ -61,7 +61,7 @@ chip northbridge/amd/amdk8/root_complex # irq 2 = 0x10 # irq 3 = 0x11 # end - #end + #end end device pci 1.1 on end # IOAPIC end @@ -82,7 +82,7 @@ chip northbridge/amd/amdk8/root_complex # irq 2 = 0x13 # irq 3 = 0x10 # end - #end + #end ## PCI Slot 6 (correct?) #chip drivers/generic/generic # device pci 4.0 on @@ -91,13 +91,13 @@ chip northbridge/amd/amdk8/root_complex # irq 2 = 0x12 # irq 3 = 0x13 # end - #end + #end end # LPC bridge device pci 1.0 on chip superio/nsc/pc87360 - device pnp 2e.0 off # Floppy + device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 @@ -124,7 +124,7 @@ chip northbridge/amd/amdk8/root_complex device pnp 2e.7 off end # GPIO device pnp 2e.8 off end # ACB device pnp 2e.9 off end # FSCM - device pnp 2e.a off end # WDT + device pnp 2e.a off end # WDT end end device pci 1.1 on end # IDE @@ -132,8 +132,8 @@ chip northbridge/amd/amdk8/root_complex device pci 1.3 on # System Management chip drivers/generic/generic #phillips pca9545 smbus mux - device i2c 70 on - # analog_devices adm1026 + device i2c 70 on + # analog_devices adm1026 chip drivers/generic/generic device i2c 2c on end end @@ -147,33 +147,33 @@ chip northbridge/amd/amdk8/root_complex end chip drivers/generic/generic #dimm 0-0-1 device i2c 51 on end - end + end chip drivers/generic/generic #dimm 0-1-0 device i2c 52 on end - end + end chip drivers/generic/generic #dimm 0-1-1 device i2c 53 on end - end + end chip drivers/generic/generic #dimm 1-0-0 - device i2c 54 on end + device i2c 54 on end end chip drivers/generic/generic #dimm 1-0-1 device i2c 55 on end - end + end chip drivers/generic/generic #dimm 1-1-0 device i2c 56 on end - end + end chip drivers/generic/generic #dimm 1-1-1 device i2c 57 on end - end + end end device pci 1.5 off end # AC97 Audio device pci 1.6 on end # AC97 Modem register "ide0_enable" = "1" register "ide1_enable" = "1" end - end # device pci 18.0 - + end # device pci 18.0 + device pci 18.0 on end # LDT1 device pci 18.0 on end # LDT2 device pci 18.1 on end @@ -188,6 +188,6 @@ chip northbridge/amd/amdk8/root_complex device pci 19.2 on end device pci 19.3 on end end - end + end end diff --git a/src/mainboard/arima/hdama/irq_tables.c b/src/mainboard/arima/hdama/irq_tables.c index 2ca98066d0..ba516f88e2 100644 --- a/src/mainboard/arima/hdama/irq_tables.c +++ b/src/mainboard/arima/hdama/irq_tables.c @@ -12,7 +12,7 @@ {linkc, AVAILABLE_IRQS}, {linkd, AVAILABLE_IRQS}}, slot, 0} /* Each IRQ_SLOT entry consists of: - * bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu + * bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ const struct irq_routing_table intel_irq_routing_table = { diff --git a/src/mainboard/arima/hdama/mptable.c b/src/mainboard/arima/hdama/mptable.c index 643dfabd5d..11b8063f95 100644 --- a/src/mainboard/arima/hdama/mptable.c +++ b/src/mainboard/arima/hdama/mptable.c @@ -4,7 +4,7 @@ #include <string.h> #include <stdint.h> #include <cpu/x86/lapic.h> -#include <arch/cpu.h> +#include <arch/cpu.h> #include <arch/io.h> #define HT_INIT_CONTROL 0x6c @@ -26,7 +26,7 @@ static void smp_write_processors_inorder(struct mp_config_table *mc) unsigned cpu_feature_flags; struct cpuid_result result; device_t cpu; - + boot_apic_id = lapicid(); apic_version = lapic_read(LAPIC_LVR) & 0xff; result = cpuid(1); @@ -57,7 +57,7 @@ static void smp_write_processors_inorder(struct mp_config_table *mc) } } } - + static unsigned node_link_to_bus(unsigned node, unsigned link) { device_t dev; @@ -79,12 +79,12 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) dst_node = (config_map >> 4) & 7; dst_link = (config_map >> 8) & 3; bus_base = (config_map >> 16) & 0xff; -#if 0 +#if 0 printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", dst_node, dst_link, bus_base, reg, config_map); #endif - if ((dst_node == node) && (dst_link == link)) + if ((dst_node == node) && (dst_link == link)) { return bus_base; } diff --git a/src/mainboard/artecgroup/Kconfig b/src/mainboard/artecgroup/Kconfig index 5f1a6e906f..e95e56a055 100644 --- a/src/mainboard/artecgroup/Kconfig +++ b/src/mainboard/artecgroup/Kconfig @@ -1,7 +1,7 @@ choice prompt "Mainboard model" depends on VENDOR_ARTEC_GROUP - + source "src/mainboard/artecgroup/dbe61/Kconfig" endchoice diff --git a/src/mainboard/artecgroup/dbe61/spd_table.h b/src/mainboard/artecgroup/dbe61/spd_table.h index 33c9237836..73c777c9c4 100644 --- a/src/mainboard/artecgroup/dbe61/spd_table.h +++ b/src/mainboard/artecgroup/dbe61/spd_table.h @@ -27,7 +27,7 @@ struct spd_entry { /* Save space by using a short list of SPD values used by Geode LX Memory init */ /* 128MB */ -const struct spd_entry spd_table [] = +const struct spd_entry spd_table [] = { {SPD_MEMORY_TYPE, 0x07}, /* (Fundamental) memory type */ {SPD_NUM_ROWS, 0x0D}, /* Number of row address bits */ diff --git a/src/mainboard/asus/a8n_e/irq_tables.c b/src/mainboard/asus/a8n_e/irq_tables.c index 0c0d3467a2..ce15efd1a8 100644 --- a/src/mainboard/asus/a8n_e/irq_tables.c +++ b/src/mainboard/asus/a8n_e/irq_tables.c @@ -67,7 +67,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) uint8_t *v, sum = 0; int i; - /* get_bus_conf() will find out all bus num and APIC that share with + /* get_bus_conf() will find out all bus num and APIC that share with * mptable.c and mptable.c. */ get_bus_conf(); diff --git a/src/mainboard/asus/a8v-e_se/acpi_tables.c b/src/mainboard/asus/a8v-e_se/acpi_tables.c index de957a8f78..e7e6bb40f7 100644 --- a/src/mainboard/asus/a8v-e_se/acpi_tables.c +++ b/src/mainboard/asus/a8v-e_se/acpi_tables.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Written by Stefan Reinauer <stepan@openbios.org>. - * ACPI FADT, FACS, and DSDT table support added by + * ACPI FADT, FACS, and DSDT table support added by * * Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org> * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com> @@ -71,7 +71,7 @@ unsigned long acpi_fill_madt(unsigned long current) /* IRQ0 -> APIC IRQ2. */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0x0); + current, 0, 0, 2, 0x0); /* Create all subtables for processors. */ current = acpi_create_madt_lapic_nmis(current, diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index 3ec90f8010..f571bae472 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -5,7 +5,7 @@ * (Written by Yinghai Lu <yinghailu@amd.com> for AMD) * Copyright (C) 2006 MSI * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI) - * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> + * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -180,7 +180,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) }; unsigned bsp_apicid = 0; int needs_reset = 0; - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); sio_init(); diff --git a/src/mainboard/asus/m2v-mx_se/acpi_tables.c b/src/mainboard/asus/m2v-mx_se/acpi_tables.c index 46a6c1f6a4..1862bc993f 100644 --- a/src/mainboard/asus/m2v-mx_se/acpi_tables.c +++ b/src/mainboard/asus/m2v-mx_se/acpi_tables.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Written by Stefan Reinauer <stepan@openbios.org>. - * ACPI FADT, FACS, and DSDT table support added by + * ACPI FADT, FACS, and DSDT table support added by * * Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org> * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com> @@ -73,7 +73,7 @@ unsigned long acpi_fill_madt(unsigned long current) /* IRQ0 -> APIC IRQ2. */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0x0); + current, 0, 0, 2, 0x0); /* Create all subtables for processors. */ current = acpi_create_madt_lapic_nmis(current, diff --git a/src/mainboard/asus/m2v-mx_se/dsdt.asl b/src/mainboard/asus/m2v-mx_se/dsdt.asl index fd4d42d378..493f1d6c8f 100644 --- a/src/mainboard/asus/m2v-mx_se/dsdt.asl +++ b/src/mainboard/asus/m2v-mx_se/dsdt.asl @@ -60,7 +60,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) Name (_ADR, 0x00) Name (_UID, 0x00) Name (_BBN, 0x00) - + External (BUSN) External (MMIO) External (PCIO) @@ -95,7 +95,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) - Return (Local3) + Return (Local3) } /* PCI Routing Table */ @@ -185,7 +185,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) /* two LSB bits are blink rate */ LEDR, 2, } - + /* PS/2 keyboard (seems to be important for WinXP install) */ Device (KBD) { diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index 04a5206437..ea9870798c 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -5,7 +5,7 @@ * (Written by Yinghai Lu <yinghailu@amd.com> for AMD) * Copyright (C) 2006 MSI * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI) - * Copyright (C) 2008 Rudolf Marek <r.marek@assembler.cz> + * Copyright (C) 2008 Rudolf Marek <r.marek@assembler.cz> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/mew-vm/devicetree.cb b/src/mainboard/asus/mew-vm/devicetree.cb index a5415a2bfe..29d706c62a 100644 --- a/src/mainboard/asus/mew-vm/devicetree.cb +++ b/src/mainboard/asus/mew-vm/devicetree.cb @@ -1,5 +1,5 @@ chip northbridge/intel/i82810 - device pci_domain 0 on + device pci_domain 0 on device pci 0.0 on end # Host bridge device pci 1.0 on # Onboard Video # device pci 1.0 on end diff --git a/src/mainboard/asus/mew-vm/irq_tables.c b/src/mainboard/asus/mew-vm/irq_tables.c index 3bd0d7195f..259b0e4938 100644 --- a/src/mainboard/asus/mew-vm/irq_tables.c +++ b/src/mainboard/asus/mew-vm/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! * (but if you do, please run checkpir on it to verify) * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up * @@ -18,7 +18,7 @@ const struct irq_routing_table intel_irq_routing_table = { 0x7120, /* Device */ 0, /* Crap (miniport) */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x89, /* u8 checksum , this has to set to some value + 0x89, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ diff --git a/src/mainboard/azza/Kconfig b/src/mainboard/azza/Kconfig index f7109ecbf7..0c0be97d46 100644 --- a/src/mainboard/azza/Kconfig +++ b/src/mainboard/azza/Kconfig @@ -21,7 +21,7 @@ choice prompt "Mainboard model" depends on VENDOR_AZZA - + source "src/mainboard/azza/pt-6ibd/Kconfig" endchoice diff --git a/src/mainboard/biostar/Kconfig b/src/mainboard/biostar/Kconfig index 73bdfc20d8..85fad0a4f1 100644 --- a/src/mainboard/biostar/Kconfig +++ b/src/mainboard/biostar/Kconfig @@ -21,7 +21,7 @@ choice prompt "Mainboard model" depends on VENDOR_BIOSTAR - + source "src/mainboard/biostar/m6tba/Kconfig" endchoice diff --git a/src/mainboard/broadcom/Kconfig b/src/mainboard/broadcom/Kconfig index bf956ecdb3..d7406c0b45 100644 --- a/src/mainboard/broadcom/Kconfig +++ b/src/mainboard/broadcom/Kconfig @@ -1,7 +1,7 @@ choice prompt "Mainboard model" depends on VENDOR_BROADCOM - + source "src/mainboard/broadcom/blast/Kconfig" endchoice diff --git a/src/mainboard/broadcom/blast/devicetree.cb b/src/mainboard/broadcom/blast/devicetree.cb index a9cabe6bea..d06c590bf8 100644 --- a/src/mainboard/broadcom/blast/devicetree.cb +++ b/src/mainboard/broadcom/blast/devicetree.cb @@ -6,7 +6,7 @@ chip northbridge/amd/amdk8/root_complex end device pci_domain 0 on chip northbridge/amd/amdk8 - device pci 18.0 on # northbridge + device pci 18.0 on # northbridge # devices on link 0 chip southbridge/broadcom/bcm5780 # HT2000 device pci 0.0 on end # PXB 1 0x0130 @@ -95,7 +95,7 @@ chip northbridge/amd/amdk8/root_complex device pnp 2e.10 on #RTC io 0x60 = 0x70 io 0x62 = 0x72 - end + end end end device pci 1.3 on end # WDTimer 0x0238 @@ -110,7 +110,7 @@ chip northbridge/amd/amdk8/root_complex end # device pci 18.0 device pci 18.0 on end - device pci 18.0 on end + device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end diff --git a/src/mainboard/broadcom/blast/get_bus_conf.c b/src/mainboard/broadcom/blast/get_bus_conf.c index 9d1a4b1bf0..06f42f4092 100644 --- a/src/mainboard/broadcom/blast/get_bus_conf.c +++ b/src/mainboard/broadcom/blast/get_bus_conf.c @@ -21,7 +21,7 @@ unsigned char bus_bcm5785_1_1 = 9; unsigned apicid_bcm5785[3]; -unsigned pci1234x[] = +unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail 0x0000ff0, @@ -115,9 +115,9 @@ void get_bus_conf(void) /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS==1 apicid_base = get_apicid_base(3); -#else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; +#else + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif - for(i=0;i<3;i++) + for(i=0;i<3;i++) apicid_bcm5785[i] = apicid_base+i; } diff --git a/src/mainboard/broadcom/blast/irq_tables.c b/src/mainboard/broadcom/blast/irq_tables.c index 3f6f73893e..406419d6d8 100644 --- a/src/mainboard/broadcom/blast/irq_tables.c +++ b/src/mainboard/broadcom/blast/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up @@ -16,7 +16,7 @@ static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t dev uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; + pirq_info->bus = bus; pirq_info->devfn = devfn; pirq_info->irq[0].link = link0; @@ -64,22 +64,22 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq = (void *)(addr); v = (uint8_t *)(addr); - + pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - + pirq->rtr_bus = bus_bcm5785_0; pirq->rtr_devfn = (sysconf.sbdn<<3)|0; pirq->exclusive_irqs = 0; - + pirq->rtr_vendor = 0x1166; pirq->rtr_device = 0x0036; pirq->miniport_data = 0; memset(pirq->rfu, 0, sizeof(pirq->rfu)); - + get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c pirq_info = (void *) ( &pirq->checksum + 1); @@ -87,11 +87,11 @@ unsigned long write_pirq_routing_table(unsigned long addr) //pci bridge write_pirq_info(pirq_info, bus_bcm5785_0, (sysconf.sbdn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; - - pirq->size = 32 + 16 * slot_num; + + pirq->size = 32 + 16 * slot_num; for (i = 0; i < pirq->size; i++) - sum += v[i]; + sum += v[i]; sum = pirq->checksum - sum; diff --git a/src/mainboard/broadcom/blast/mptable.c b/src/mainboard/broadcom/blast/mptable.c index 8a1b133bfb..d24630844e 100644 --- a/src/mainboard/broadcom/blast/mptable.c +++ b/src/mainboard/broadcom/blast/mptable.c @@ -72,12 +72,12 @@ static void *smp_write_config_table(void *v) } } } - + } - + /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_bcm5785[0], 0x0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_bcm5785[0], 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_bcm5785[0], 0x1); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_bcm5785[0], 0x2); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, apicid_bcm5785[0], 0x3); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, apicid_bcm5785[0], 0x4); @@ -89,7 +89,7 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, apicid_bcm5785[0], 0xc); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, apicid_bcm5785[0], 0xd); -//IDE +//IDE outb(0x02, 0xc00); outb(0x0e, 0xc01); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_bcm5785_0, ((1+sysconf.sbdn)<<2)|1, apicid_bcm5785[0], 0xe); // IDE @@ -97,14 +97,14 @@ static void *smp_write_config_table(void *v) //SATA outb(0x07, 0xc00); outb(0x0f, 0xc01); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_1, (0x0e<<2)|0, apicid_bcm5785[0], 0xf); - + //USB outb(0x01, 0xc00); outb(0x0a, 0xc01); for(i=0;i<3;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, ((2+sysconf.sbdn)<<2)|i, apicid_bcm5785[0], 0xa); // } - + /* enable int */ /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/ @@ -127,13 +127,13 @@ static void *smp_write_config_table(void *v) } -//pci slot (on bcm5785) +//pci slot (on bcm5785) for(i=0;i<4;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, (4<<2)|i, apicid_bcm5785[1], i%2); // } -//onboard ati +//onboard ati smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, (5<<2)|0, apicid_bcm5785[1], 0x1); //PCI-X on bcm5780 @@ -157,7 +157,7 @@ static void *smp_write_config_table(void *v) } -// Second PCI-E x8 +// Second PCI-E x8 for(i=0;i<4;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[3], (0<<2)|i, apicid_bcm5785[1], 0xc); // } diff --git a/src/mainboard/broadcom/blast/resourcemap.c b/src/mainboard/broadcom/blast/resourcemap.c index 438605c701..71f0bba010 100644 --- a/src/mainboard/broadcom/blast/resourcemap.c +++ b/src/mainboard/broadcom/blast/resourcemap.c @@ -119,7 +119,7 @@ static void setup_blast_resource_map(void) PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00, + PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -144,7 +144,7 @@ static void setup_blast_resource_map(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, @@ -181,7 +181,7 @@ static void setup_blast_resource_map(void) * This field defines the end of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000, + PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000, PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, @@ -200,7 +200,7 @@ static void setup_blast_resource_map(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -208,7 +208,7 @@ static void setup_blast_resource_map(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003, @@ -252,8 +252,8 @@ static void setup_blast_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ - PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x08000003, - PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x08000003, + PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, }; diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c index 35823bd47c..13f5f97414 100644 --- a/src/mainboard/broadcom/blast/romstage.c +++ b/src/mainboard/broadcom/blast/romstage.c @@ -3,7 +3,7 @@ #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 #endif - + #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -75,7 +75,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" /* tyan does not want the default */ -#include "resourcemap.c" +#include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" @@ -109,7 +109,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) struct mem_controller ctrl[8]; unsigned nodes; - if (!cpu_init_detectedx && boot_cpu()) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ @@ -130,7 +130,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); // post_code(0x33); - + uart_init(); // post_code(0x34); @@ -142,7 +142,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); setup_blast_resource_map(); - + #if 0 dump_pci_device(PCI_DEV(0, 0x18, 0)); dump_pci_device(PCI_DEV(0, 0x19, 0)); @@ -174,7 +174,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_smbus(); -#if 0 +#if 0 int i; for(i=4;i<8;i++) { change_i2c_mux(i); diff --git a/src/mainboard/compaq/Kconfig b/src/mainboard/compaq/Kconfig index 160048f30f..c2bbb57120 100644 --- a/src/mainboard/compaq/Kconfig +++ b/src/mainboard/compaq/Kconfig @@ -21,7 +21,7 @@ choice prompt "Mainboard model" depends on VENDOR_COMPAQ - + source "src/mainboard/compaq/deskpro_en_sff_p600/Kconfig" endchoice diff --git a/src/mainboard/dell/s1850/debug.c b/src/mainboard/dell/s1850/debug.c index 2ea3db32ea..45315618b7 100644 --- a/src/mainboard/dell/s1850/debug.c +++ b/src/mainboard/dell/s1850/debug.c @@ -5,7 +5,7 @@ static void print_reg(unsigned char index) { unsigned char data; - + outb(index, 0x2e); data = inb(0x2f); print_debug("0x"); @@ -15,7 +15,7 @@ static void print_reg(unsigned char index) print_debug("\n"); return; } - + static void xbus_en(void) { /* select the XBUS function in the SIO */ @@ -25,7 +25,7 @@ static void xbus_en(void) outb(0x01, 0x2f); return; } - + static void setup_func(unsigned char func) { /* select the function in the SIO */ @@ -43,27 +43,27 @@ static void setup_func(unsigned char func) print_reg(0x75); return; } - + static void siodump(void) { int i; unsigned char data; - + print_debug("\n*** SERVER I/O REGISTERS ***\n"); for (i=0x10; i<=0x2d; i++) { print_reg((unsigned char)i); } -#if 0 +#if 0 print_debug("\n*** XBUS REGISTERS ***\n"); setup_func(0x0f); for (i=0xf0; i<=0xff; i++) { print_reg((unsigned char)i); } - + print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); setup_func(0x03); print_reg(0xf0); - + print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); setup_func(0x02); print_reg(0xf0); @@ -82,13 +82,13 @@ static void siodump(void) print_debug("\nGPDI 4: 0x"); print_debug_hex8(data); print_debug("\n"); - -#if 0 - + +#if 0 + print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); setup_func(0x0a); print_reg(0xf0); - + print_debug("\n*** FAN CONTROL REGISTERS ***\n"); setup_func(0x09); print_reg(0xf0); @@ -103,11 +103,11 @@ static void siodump(void) print_reg(0xf7); print_reg(0xfe); print_reg(0xff); - + print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); setup_func(0x14); print_reg(0xf0); -#endif +#endif return; } @@ -124,8 +124,8 @@ static void print_debug_pci_dev(unsigned dev) static void print_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -144,7 +144,7 @@ static void dump_pci_device(unsigned dev) int i; print_debug_pci_dev(dev); print_debug("\n"); - + for(i = 0; i <= 255; i++) { unsigned char val; if ((i & 0x0f) == 0) { @@ -164,19 +164,19 @@ static void dump_bar14(unsigned dev) { int i; unsigned long bar; - + print_debug("BAR 14 Dump\n"); - + bar = pci_read_config32(dev, 0x14); for(i = 0; i <= 0x300; i+=4) { -#if 0 +#if 0 unsigned char val; if ((i & 0x0f) == 0) { print_debug_hex8(i); print_debug_char(':'); } val = pci_read_config8(dev, i); -#endif +#endif if((i%4)==0) { print_debug("\n"); print_debug_hex16(i); @@ -191,8 +191,8 @@ static void dump_bar14(unsigned dev) static void dump_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -215,7 +215,7 @@ void dump_spd_registers(void) print_debug("\n"); print_debug("dimm "); print_debug_hex8(device); - + for(i = 0; (i < 256) ; i++) { unsigned char byte; if ((i % 16) == 0) { @@ -228,7 +228,7 @@ void dump_spd_registers(void) print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); @@ -248,7 +248,7 @@ void show_dram_slots(void) print_debug("\n"); print_debug("dimm "); print_debug_hex8(device); - + status = smbus_read_byte(device, 0); if (status < 0) { print_debug("bad device: "); @@ -272,7 +272,7 @@ void dump_ipmi_registers(void) print_debug("\n"); print_debug("ipmi "); print_debug_hex8(device); - + for(i = 0; (i < 8) ; i++) { unsigned char byte; status = smbus_read_byte(device, 2); @@ -280,7 +280,7 @@ void dump_ipmi_registers(void) print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); @@ -288,4 +288,4 @@ void dump_ipmi_registers(void) device += SMBUS_MEM_DEVICE_INC; print_debug("\n"); } -} +} diff --git a/src/mainboard/dell/s1850/devicetree.cb b/src/mainboard/dell/s1850/devicetree.cb index ab95e54a7b..bd7b3a3773 100644 --- a/src/mainboard/dell/s1850/devicetree.cb +++ b/src/mainboard/dell/s1850/devicetree.cb @@ -1,23 +1,23 @@ chip northbridge/intel/e7520 # mch - device pci_domain 0 on + device pci_domain 0 on chip southbridge/intel/i82801ex # i82801er # USB ports device pci 1d.0 on end device pci 1d.1 on end - device pci 1d.2 on end + device pci 1d.2 on end device pci 1d.3 on end device pci 1d.7 on end - + # -> Bridge device pci 1e.0 on end - + # -> ISA - device pci 1f.0 on + device pci 1f.0 on chip superio/nsc/pc8374 device pnp 2e.0 off end device pnp 2e.1 off end device pnp 2e.2 off end - device pnp 2e.3 on + device pnp 2e.3 on io 0x60 = 0x3f8 irq 0x70 = 4 end @@ -30,22 +30,22 @@ chip northbridge/intel/e7520 # mch end # -> IDE device pci 1f.1 on end - # -> SATA + # -> SATA device pci 1f.2 on end device pci 1f.3 on end register "pirq_a_d" = "0x8a07030b" register "pirq_e_h" = "0x85808080" end - device pci 00.0 on end + device pci 00.0 on end device pci 00.1 on end - device pci 01.0 on end - device pci 02.0 on + device pci 01.0 on end + device pci 02.0 on chip southbridge/intel/pxhd # pxhd1 # Bus bridges and ioapics usually bus 1 - device pci 0.0 on + device pci 0.0 on # On board gig e1000 - chip drivers/generic/generic + chip drivers/generic/generic device pci 03.0 on end device pci 03.1 on end end diff --git a/src/mainboard/dell/s1850/irq_tables.c b/src/mainboard/dell/s1850/irq_tables.c index 8b4773df66..1f56ed30b9 100644 --- a/src/mainboard/dell/s1850/irq_tables.c +++ b/src/mainboard/dell/s1850/irq_tables.c @@ -1,8 +1,8 @@ /* * This file is part of the coreboot project. * - * Copyright (C) by the coreboot pirq tool. - * This file was programatically generated. + * Copyright (C) by the coreboot pirq tool. + * This file was programatically generated. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/dell/s1850/mptable.c b/src/mainboard/dell/s1850/mptable.c index c7fd52af3e..4cdd0f1e7b 100644 --- a/src/mainboard/dell/s1850/mptable.c +++ b/src/mainboard/dell/s1850/mptable.c @@ -36,7 +36,7 @@ static void *smp_write_config_table(void *v) mc->reserved = 0; smp_write_processors(mc); - + { device_t dev; @@ -98,9 +98,9 @@ static void *smp_write_config_table(void *v) bus_pxhd_4 = 6; } - + } - + /* define bus and isa numbers */ for(bus_num = 0; bus_num < bus_isa; bus_num++) { smp_write_bus(mc, bus_num, "PCI "); @@ -135,7 +135,7 @@ static void *smp_write_config_table(void *v) else { printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n"); } - } + } /* ISA backward compatibility interrupts */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x00, 0x02, 0x00); diff --git a/src/mainboard/dell/s1850/romstage.c b/src/mainboard/dell/s1850/romstage.c index 199c6ea5d5..07fbef282d 100644 --- a/src/mainboard/dell/s1850/romstage.c +++ b/src/mainboard/dell/s1850/romstage.c @@ -65,7 +65,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) static inline void ibfzero(void) { - while(inb(ipmicsr) & (1<<IBF)) + while(inb(ipmicsr) & (1<<IBF)) ; } static inline void clearobf(void) @@ -75,7 +75,7 @@ static inline void clearobf(void) static inline void waitobf(void) { - while((inb(ipmicsr) & (1<<OBF)) == 0) + while((inb(ipmicsr) & (1<<OBF)) == 0) ; } /* quite possibly the stupidest interface ever designed. */ @@ -162,8 +162,8 @@ static void main(unsigned long bist) u32 l; int do_reset; /* - * - * + * + * */ static const struct mem_controller mch[] = { { @@ -192,9 +192,9 @@ static void main(unsigned long bist) 0, }; - /* using SerialICE, we've seen this basic reset sequence on the dell. + /* using SerialICE, we've seen this basic reset sequence on the dell. * we don't understand it as it uses undocumented registers, but - * we're going to clone it. + * we're going to clone it. */ /* enable a hidden device. */ b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4); @@ -217,11 +217,11 @@ static void main(unsigned long bist) b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4); b &= ~0x8; pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b); - + /* set up LPC bridge bits, some of which reply on undocumented * registers */ - + b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xd8); b |= 4; pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd8, b); @@ -244,9 +244,9 @@ static void main(unsigned long bist) w = inw(0x866); outw(w|2, 0x866); -#if 0 +#if 0 /*seriaice shows - dell does this so leave it here so I don't forget + dell does this so leave it here so I don't forget */ /* SMBUS */ pci_write_config16(PCI_DEV(0, 0x1f, 3), 0x20, 0x08c0); @@ -260,7 +260,7 @@ static void main(unsigned long bist) b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4); b |= 2; pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b); - + /* ?? */ l = pci_read_config32(PCI_DEV(0, 8, 0), 0xc0); do_reset = l & 0x8000000; @@ -334,7 +334,7 @@ static void main(unsigned long bist) #endif disable_watchdogs(); // dump_ipmi_registers(); - mainboard_set_e7520_leds(); + mainboard_set_e7520_leds(); sdram_initialize(ARRAY_SIZE(mch), mch); #if 0 @@ -345,7 +345,7 @@ static void main(unsigned long bist) // dump_bar14(PCI_DEV(0, 0x00, 0)); #endif -#if 1 // temporarily disabled +#if 1 // temporarily disabled /* Check the first 1M */ // ram_check(0x00000000, 0x000100000); // ram_check(0x00000000, 0x000a0000); @@ -357,8 +357,8 @@ static void main(unsigned long bist) #if 0 ram_check(0x00000000, 0x02000000); #endif - -#if 0 + +#if 0 while(1) { hlt(); } diff --git a/src/mainboard/dell/s1850/s1850_fixups.c b/src/mainboard/dell/s1850/s1850_fixups.c index 9827120056..7ef9ce163b 100644 --- a/src/mainboard/dell/s1850/s1850_fixups.c +++ b/src/mainboard/dell/s1850/s1850_fixups.c @@ -9,13 +9,13 @@ static void mch_reset(void) static void mainboard_set_e7520_pll(unsigned bits) { - return; + return; } static void mainboard_set_e7520_leds(void) { - return; + return; } static void mainboard_set_ich5(void) @@ -28,8 +28,8 @@ static void mainboard_set_ich5(void) pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xe3, 0xc0); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xf0, 0x0); /* disable certain devices -- see data sheet -- this is from - * dell settings via lspci - * Note that they leave SMBUS disabled -- 8f6f. + * dell settings via lspci + * Note that they leave SMBUS disabled -- 8f6f. * we leave it enabled and visible in config space -- 8f66 */ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0xf2, 0x8f66); @@ -38,7 +38,7 @@ static void mainboard_set_ich5(void) pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x5c, 0x10); /* now the fun begins ... enable the GPIOs as done on factory */ - /* factory config from IO ports + /* factory config from IO ports * It has a few more things enabled than default! */ outl(0x1ae0f183, 0x880); diff --git a/src/mainboard/dell/s1850/watchdog.c b/src/mainboard/dell/s1850/watchdog.c index 50e9e6e7b0..43f4029b5e 100644 --- a/src/mainboard/dell/s1850/watchdog.c +++ b/src/mainboard/dell/s1850/watchdog.c @@ -31,17 +31,17 @@ static void disable_ich5_watchdog(void) value = pci_read_config16(dev, 0x04); value |= (1 << 10); pci_write_config16(dev, 0x04, value); - + /* Set and enable acpibase */ pci_write_config32(dev, 0x40, ICH5_WDBASE | 1); pci_write_config8(dev, 0x44, 0x10); base = ICH5_WDBASE + 0x60; - + /* Set bit 11 in TCO1_CNT */ value = inw(base + 0x08); value |= 1 << 11; outw(value, base + 0x08); - + /* Clear TCO timeout status */ outw(0x0008, base + 0x04); outw(0x0002, base + 0x06); diff --git a/src/mainboard/digitallogic/Kconfig b/src/mainboard/digitallogic/Kconfig index 7c8fb1164e..7e115fc402 100644 --- a/src/mainboard/digitallogic/Kconfig +++ b/src/mainboard/digitallogic/Kconfig @@ -1,7 +1,7 @@ choice prompt "Mainboard model" depends on VENDOR_DIGITAL_LOGIC - + source "src/mainboard/digitallogic/adl855pc/Kconfig" source "src/mainboard/digitallogic/msm586seg/Kconfig" source "src/mainboard/digitallogic/msm800sev/Kconfig" diff --git a/src/mainboard/digitallogic/adl855pc/devicetree.cb b/src/mainboard/digitallogic/adl855pc/devicetree.cb index 5365b3f538..6b52633382 100644 --- a/src/mainboard/digitallogic/adl855pc/devicetree.cb +++ b/src/mainboard/digitallogic/adl855pc/devicetree.cb @@ -1,5 +1,5 @@ chip northbridge/intel/i855 - device pci_domain 0 on + device pci_domain 0 on device pci 0.0 on end device pci 1.0 on end chip southbridge/intel/i82801dx @@ -51,7 +51,7 @@ chip northbridge/intel/i855 end end end - device apic_cluster 0 on + device apic_cluster 0 on chip cpu/intel/socket_mPGA479M device apic 0 on end end diff --git a/src/mainboard/digitallogic/adl855pc/irq_tables.c b/src/mainboard/digitallogic/adl855pc/irq_tables.c index f3978d5e81..8b4352d25a 100644 --- a/src/mainboard/digitallogic/adl855pc/irq_tables.c +++ b/src/mainboard/digitallogic/adl855pc/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up diff --git a/src/mainboard/digitallogic/adl855pc/romstage.c b/src/mainboard/digitallogic/adl855pc/romstage.c index 731e681253..a137a3fd6f 100644 --- a/src/mainboard/digitallogic/adl855pc/romstage.c +++ b/src/mainboard/digitallogic/adl855pc/romstage.c @@ -15,7 +15,7 @@ #include "southbridge/intel/i82801dx/i82801dx_early_smbus.c" #include "northbridge/intel/i855/raminit.h" #include "northbridge/intel/i855/debug.c" -#include "superio/winbond/w83627hf/w83627hf_early_serial.c" +#include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" @@ -45,7 +45,7 @@ void main(unsigned long bist) init_timer(); #endif } - + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -66,7 +66,7 @@ void main(unsigned long bist) sdram_initialize(ARRAY_SIZE(memctrl), memctrl); - } + } #if 0 dump_pci_devices(); @@ -76,7 +76,7 @@ void main(unsigned long bist) ram_check(0x00000000, msr.lo+(msr.hi<<32)); // Check 16MB of memory @ 0 ram_check(0x00000000, 0x01000000); - // Check 16MB of memory @ 2GB + // Check 16MB of memory @ 2GB ram_check(0x80000000, 0x81000000); #endif } diff --git a/src/mainboard/digitallogic/msm586seg/devicetree.cb b/src/mainboard/digitallogic/msm586seg/devicetree.cb index 05067ca632..1ccf39f5b8 100644 --- a/src/mainboard/digitallogic/msm586seg/devicetree.cb +++ b/src/mainboard/digitallogic/msm586seg/devicetree.cb @@ -1,5 +1,5 @@ chip cpu/amd/sc520 - device pci_domain 0 on + device pci_domain 0 on device pci 0.0 on end device pci 12.0 on end # enet device pci 14.0 on end # 69000 diff --git a/src/mainboard/digitallogic/msm586seg/irq_tables.c b/src/mainboard/digitallogic/msm586seg/irq_tables.c index 9b49747ead..22d5820a62 100644 --- a/src/mainboard/digitallogic/msm586seg/irq_tables.c +++ b/src/mainboard/digitallogic/msm586seg/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up * diff --git a/src/mainboard/digitallogic/msm586seg/mainboard.c b/src/mainboard/digitallogic/msm586seg/mainboard.c index fefe553de3..2361059a7d 100644 --- a/src/mainboard/digitallogic/msm586seg/mainboard.c +++ b/src/mainboard/digitallogic/msm586seg/mainboard.c @@ -14,10 +14,10 @@ static void irqdump(void) int i; int irqlist[] = {0xd00, 0xd02, 0xd03, 0xd04, 0xd08, 0xd0a, 0xd14, 0xd18, 0xd1a, 0xd1b, 0xd1c, - 0xd20, 0xd21, 0xd22, 0xd28, 0xd29, + 0xd20, 0xd21, 0xd22, 0xd28, 0xd29, 0xd30, 0xd31, 0xd32, 0xd33, - 0xd40, 0xd41, 0xd42, 0xd43,0xd44, 0xd45, 0xd46, - 0xd50, 0xd51, 0xd52, 0xd53,0xd54, 0xd55, 0xd56, 0xd57,0xd58, 0xd59, 0xd5a, + 0xd40, 0xd41, 0xd42, 0xd43,0xd44, 0xd45, 0xd46, + 0xd50, 0xd51, 0xd52, 0xd53,0xd54, 0xd55, 0xd56, 0xd57,0xd58, 0xd59, 0xd5a, -1}; mmcr = (void *) 0xfffef000; @@ -37,7 +37,7 @@ static void enable_dev(struct device *dev) //volatile struct mmcrpic *pic = MMCRPIC; volatile struct mmcr *mmcr = MMCRDEFAULT; - /* msm586seg has this register set to a weird value. + /* msm586seg has this register set to a weird value. * follow the board, not the manual! */ @@ -47,7 +47,7 @@ static void enable_dev(struct device *dev) /* from fuctory bios */ /* NOTE: the following interrupt settings made interrupts work - * for hard drive, and serial, but not for ethernet + * for hard drive, and serial, but not for ethernet */ /* just do what they say and nobody gets hurt. */ mmcr->pic.pcicr = 0 ; // M_GINT_MODE | M_S1_MODE | M_S2_MODE; @@ -78,7 +78,7 @@ static void enable_dev(struct device *dev) printk(BIOS_ERR, "0xc22 0x%x\n", *(unsigned short *) 0xfffefc22); /* The following block has NOT proven sufficient to get - * the VGA hardware to talk to us + * the VGA hardware to talk to us */ /* let's set some mmcr stuff per the BIOS settings */ mmcr->dbctl.dbctl = 0x10; @@ -100,20 +100,20 @@ static void enable_dev(struct device *dev) */ mmcr->sysmap.adddecctl = 0x10; - /* VGA now talks to us, so this adddecctl was the trick. - * still no interrupts from enet. - * Let's try fixing the piodata stuff, as there may be + /* VGA now talks to us, so this adddecctl was the trick. + * still no interrupts from enet. + * Let's try fixing the piodata stuff, as there may be * some wire there not documented. */ mmcr->pio.data31_16 = 0xffbf; /* also, our sl?picmode needs to match fuctory bios */ mmcr->pic.sl1picmode = 0x80; mmcr->pic.sl2picmode = 0x0; - /* and, finally, they do set gp5imap and we don't. + /* and, finally, they do set gp5imap and we don't. */ mmcr->pic.gp5imap = 0xd; /* remaining problem: almost certainly, the irq table is bogus - * NO SHOCK as it came from fuctory bios. + * NO SHOCK as it came from fuctory bios. * but let's try these 4 changes for now and see what shakes. */ /* still not interrupts. */ diff --git a/src/mainboard/digitallogic/msm586seg/romstage.c b/src/mainboard/digitallogic/msm586seg/romstage.c index 2035993be8..ae964fea93 100644 --- a/src/mainboard/digitallogic/msm586seg/romstage.c +++ b/src/mainboard/digitallogic/msm586seg/romstage.c @@ -74,7 +74,7 @@ static inline void irqinit(void){ /* these values taken from the msm board itself. * and they cause the board to not even come out of calibrating_delay_loop * if you can believe it. Our problem right now is no IDE or serial interrupts - * So we'll try to put interrupts in, one at a time. IDE first. + * So we'll try to put interrupts in, one at a time. IDE first. */ cp = (volatile unsigned char *) 0xfffefd00; *cp = 0x11; @@ -179,9 +179,9 @@ static void main(unsigned long bist) print_err("HI THERE!\n"); // sizemem(); staticmem(); - print_err("c60 is "); print_err_hex16(*(unsigned short *)0xfffefc60); + print_err("c60 is "); print_err_hex16(*(unsigned short *)0xfffefc60); print_err("\n"); - + // while(1) print_err("STATIC MEM DONE\n"); outb(0xee, 0x80); @@ -198,18 +198,18 @@ static void main(unsigned long bist) "jnz 1b\n\t" : : "a" (0), "D" (0), "c" (1024*1024) - ); - - + ); + + #endif - + #if 0 dump_pci_devices(); #endif #if 0 dump_pci_device(PCI_DEV(0, 0, 0)); #endif - + #if 0 print_err("RAM CHECK!\n"); // Check 16MB of memory @ 0 @@ -223,10 +223,10 @@ static void main(unsigned long bist) #if 1 { volatile unsigned char *src = (unsigned char *) 0x2000000 + 0x60000; - volatile unsigned char *dst = (unsigned char *) 0x4000; + volatile unsigned char *dst = (unsigned char *) 0x4000; for(i = 0; i < 0x20000; i++) { /* - print_err("Set dst "); print_err_hex32((unsigned long) dst); + print_err("Set dst "); print_err_hex32((unsigned long) dst); print_err(" to "); print_err_hex32(*src); print_err("\n"); */ *dst = *src; @@ -244,10 +244,10 @@ static void main(unsigned long bist) "jmp *%%edi\n\t" : : "a" (0x4000) - ); - + ); + print_err("Oh dear, I'm afraid it didn't work...\n"); - + while(1); #endif } diff --git a/src/mainboard/digitallogic/msm800sev/devicetree.cb b/src/mainboard/digitallogic/msm800sev/devicetree.cb index 9636dee678..6890e83327 100644 --- a/src/mainboard/digitallogic/msm800sev/devicetree.cb +++ b/src/mainboard/digitallogic/msm800sev/devicetree.cb @@ -1,5 +1,5 @@ chip northbridge/amd/lx - device pci_domain 0 on + device pci_domain 0 on device pci 1.0 on end device pci 1.1 on end chip southbridge/amd/cs5536 @@ -57,7 +57,7 @@ chip northbridge/amd/lx io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 - end + end device pnp 2e.8 off end # GPIO2 device pnp 2e.9 off end # GPIO3 device pnp 2e.a off end # ACPI diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c index 4598e89ad9..379f5517bc 100644 --- a/src/mainboard/digitallogic/msm800sev/romstage.c +++ b/src/mainboard/digitallogic/msm800sev/romstage.c @@ -93,7 +93,7 @@ void main(unsigned long bist) print_err("POST 02\n"); __asm__("wbinvd\n"); print_err("Past wbinvd\n"); - /* we are finding the return does not work on this board. Explicitly call the label that is + /* we are finding the return does not work on this board. Explicitly call the label that is * after the call to us. This is gross, but sometimes at this level it is the only way out */ void done_cache_as_ram_main(void); diff --git a/src/mainboard/eaglelion/5bcm/devicetree.cb b/src/mainboard/eaglelion/5bcm/devicetree.cb index 2e0c8161fc..7e55bca54d 100644 --- a/src/mainboard/eaglelion/5bcm/devicetree.cb +++ b/src/mainboard/eaglelion/5bcm/devicetree.cb @@ -1,5 +1,5 @@ chip northbridge/amd/gx1 - device pci_domain 0 on + device pci_domain 0 on device pci 0.0 on end chip southbridge/amd/cs5530 device pci 12.0 on diff --git a/src/mainboard/eaglelion/5bcm/irq_tables.c b/src/mainboard/eaglelion/5bcm/irq_tables.c index d58662365d..bcc53b4a26 100644 --- a/src/mainboard/eaglelion/5bcm/irq_tables.c +++ b/src/mainboard/eaglelion/5bcm/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up * diff --git a/src/mainboard/eaglelion/5bcm/romstage.c b/src/mainboard/eaglelion/5bcm/romstage.c index 633c23cd5a..11fe81250a 100644 --- a/src/mainboard/eaglelion/5bcm/romstage.c +++ b/src/mainboard/eaglelion/5bcm/romstage.c @@ -28,11 +28,11 @@ static void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - + cs5530_enable_rom(); sdram_init(); - + /* Check all of memory */ #if 0 ram_check(0x00000000, msr.lo); diff --git a/src/mainboard/emulation/qemu-x86/devicetree.cb b/src/mainboard/emulation/qemu-x86/devicetree.cb index 2e18d790c9..471cc331e1 100644 --- a/src/mainboard/emulation/qemu-x86/devicetree.cb +++ b/src/mainboard/emulation/qemu-x86/devicetree.cb @@ -1,5 +1,5 @@ chip mainboard/emulation/qemu-x86 - device pci_domain 0 on + device pci_domain 0 on device pci 0.0 on end chip southbridge/intel/i82371eb # southbridge diff --git a/src/mainboard/emulation/qemu-x86/irq_tables.c b/src/mainboard/emulation/qemu-x86/irq_tables.c index 8402602abd..27a48ec5ff 100644 --- a/src/mainboard/emulation/qemu-x86/irq_tables.c +++ b/src/mainboard/emulation/qemu-x86/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up * diff --git a/src/mainboard/emulation/qemu-x86/mainboard.c b/src/mainboard/emulation/qemu-x86/mainboard.c index be17698d7d..7ab02d93c4 100644 --- a/src/mainboard/emulation/qemu-x86/mainboard.c +++ b/src/mainboard/emulation/qemu-x86/mainboard.c @@ -25,8 +25,8 @@ static void qemu_init(device_t dev) */ pc_keyboard_init(0); - /* The PIRQ table is not working well for interrupt routing purposes. - * so we'll just set the IRQ directly. + /* The PIRQ table is not working well for interrupt routing purposes. + * so we'll just set the IRQ directly. */ printk(BIOS_INFO, "setting ethernet\n"); pci_assign_irqs(0, 3, enetIrqs); diff --git a/src/mainboard/emulation/qemu-x86/romstage.c b/src/mainboard/emulation/qemu-x86/romstage.c index 1d6eeded11..0543815a6d 100644 --- a/src/mainboard/emulation/qemu-x86/romstage.c +++ b/src/mainboard/emulation/qemu-x86/romstage.c @@ -17,10 +17,10 @@ static void main(void) { /* init_timer();*/ post_code(0x05); - + uart_init(); console_init(); - + //print_pci_devices(); //dump_pci_devices(); } diff --git a/src/mainboard/gigabyte/Kconfig b/src/mainboard/gigabyte/Kconfig index 483e3fc8a6..9323da7dd6 100644 --- a/src/mainboard/gigabyte/Kconfig +++ b/src/mainboard/gigabyte/Kconfig @@ -21,7 +21,7 @@ choice prompt "Mainboard model" depends on VENDOR_GIGABYTE - + source "src/mainboard/gigabyte/ga_2761gxdk/Kconfig" source "src/mainboard/gigabyte/ga-6bxc/Kconfig" source "src/mainboard/gigabyte/m57sli/Kconfig" diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig index d08414f217..728c40caf9 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig +++ b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig @@ -14,7 +14,7 @@ config BOARD_GIGABYTE_GA_2761GXDK select LIFT_BSP_APIC_ID select K8_REV_F_SUPPORT select BOARD_ROMSIZE_KB_512 - + config MAINBOARD_DIR string default gigabyte/ga_2761gxdk @@ -24,7 +24,7 @@ config DCACHE_RAM_BASE hex default 0xc8000 depends on BOARD_GIGABYTE_GA_2761GXDK - + config DCACHE_RAM_SIZE hex default 0x08000 @@ -36,7 +36,7 @@ config DCACHE_RAM_GLOBAL_VAR_SIZE depends on BOARD_GIGABYTE_GA_2761GXDK config APIC_ID_OFFSET - hex + hex default 0x10 depends on BOARD_GIGABYTE_GA_2761GXDK @@ -76,7 +76,7 @@ config MAX_PHYSICAL_CPUS depends on BOARD_GIGABYTE_GA_2761GXDK config HW_MEM_HOLE_SIZE_AUTO_INC - bool + bool default n depends on BOARD_GIGABYTE_GA_2761GXDK @@ -86,12 +86,12 @@ config HT_CHAIN_UNITID_BASE depends on BOARD_GIGABYTE_GA_2761GXDK config HT_CHAIN_END_UNITID_BASE - hex + hex default 0x20 depends on BOARD_GIGABYTE_GA_2761GXDK config SERIAL_CPU_INIT - bool + bool default n depends on BOARD_GIGABYTE_GA_2761GXDK diff --git a/src/mainboard/gigabyte/m57sli/Kconfig b/src/mainboard/gigabyte/m57sli/Kconfig index 2790427080..b36261e533 100644 --- a/src/mainboard/gigabyte/m57sli/Kconfig +++ b/src/mainboard/gigabyte/m57sli/Kconfig @@ -17,17 +17,17 @@ config BOARD_GIGABYTE_M57SLI select HAVE_ACPI_TABLES select K8_REV_F_SUPPORT select BOARD_ROMSIZE_KB_512 - + config MAINBOARD_DIR string - default gigabyte/m57sli + default gigabyte/m57sli depends on BOARD_GIGABYTE_M57SLI config DCACHE_RAM_BASE hex default 0xc8000 depends on BOARD_GIGABYTE_M57SLI - + config DCACHE_RAM_SIZE hex default 0x08000 @@ -39,7 +39,7 @@ config DCACHE_RAM_GLOBAL_VAR_SIZE depends on BOARD_GIGABYTE_M57SLI config APIC_ID_OFFSET - hex + hex default 0x10 depends on BOARD_GIGABYTE_M57SLI @@ -79,7 +79,7 @@ config MAX_PHYSICAL_CPUS depends on BOARD_GIGABYTE_M57SLI config HW_MEM_HOLE_SIZE_AUTO_INC - bool + bool default n depends on BOARD_GIGABYTE_M57SLI @@ -89,12 +89,12 @@ config HT_CHAIN_UNITID_BASE depends on BOARD_GIGABYTE_M57SLI config HT_CHAIN_END_UNITID_BASE - hex + hex default 0x20 depends on BOARD_GIGABYTE_M57SLI config SERIAL_CPU_INIT - bool + bool default n depends on BOARD_GIGABYTE_M57SLI diff --git a/src/mainboard/gigabyte/m57sli/Makefile.inc b/src/mainboard/gigabyte/m57sli/Makefile.inc index 00075834e1..36be8066fa 100644 --- a/src/mainboard/gigabyte/m57sli/Makefile.inc +++ b/src/mainboard/gigabyte/m57sli/Makefile.inc @@ -1,6 +1,6 @@ ## ## This file is part of the coreboot project. -## +## ## Copyright (C) 2007-2008 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify diff --git a/src/mainboard/gigabyte/m57sli/acpi_tables.c b/src/mainboard/gigabyte/m57sli/acpi_tables.c index 1bd302271a..60b041a953 100644 --- a/src/mainboard/gigabyte/m57sli/acpi_tables.c +++ b/src/mainboard/gigabyte/m57sli/acpi_tables.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Written by Stefan Reinauer <stepan@openbios.org>. - * ACPI FADT, FACS, and DSDT table support added by + * ACPI FADT, FACS, and DSDT table support added by * * Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org> * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com> @@ -47,14 +47,14 @@ unsigned long acpi_fill_madt(unsigned long current) unsigned int gsi_base = 0x18; extern unsigned char bus_mcp55[8]; extern unsigned apicid_mcp55; - + unsigned sbdn; struct resource *res; device_t dev; get_bus_conf(); sbdn = sysconf.sbdn; - + /* Create all subtables for processors. */ current = acpi_create_madt_lapics(current); @@ -84,7 +84,7 @@ unsigned long acpi_fill_madt(unsigned long current) /* IRQ0 -> APIC IRQ2. */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0x0); + current, 0, 0, 2, 0x0); /* Create all subtables for processors. */ current = acpi_create_madt_lapic_nmis(current, diff --git a/src/mainboard/gigabyte/m57sli/ap_romstage.c b/src/mainboard/gigabyte/m57sli/ap_romstage.c index 28f47597e9..8429286bc7 100644 --- a/src/mainboard/gigabyte/m57sli/ap_romstage.c +++ b/src/mainboard/gigabyte/m57sli/ap_romstage.c @@ -25,7 +25,7 @@ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 -#define SET_NB_CFG_54 1 +#define SET_NB_CFG_54 1 //used by raminit #define QRANK_DIMM_SUPPORT 1 diff --git a/src/mainboard/gigabyte/m57sli/cmos.layout b/src/mainboard/gigabyte/m57sli/cmos.layout index 9d37e2bba6..518f9458b6 100644 --- a/src/mainboard/gigabyte/m57sli/cmos.layout +++ b/src/mainboard/gigabyte/m57sli/cmos.layout @@ -1,23 +1,23 @@ -## +## ## This file is part of the coreboot project. -## +## ## Copyright (C) 2007 AMD ## Written by Yinghai Lu <yinghailu@amd.com> for AMD. -## +## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or ## (at your option) any later version. -## +## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. -## +## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## +## entries diff --git a/src/mainboard/gigabyte/m57sli/dsdt.asl b/src/mainboard/gigabyte/m57sli/dsdt.asl index c9b969de0e..a8c4242bff 100644 --- a/src/mainboard/gigabyte/m57sli/dsdt.asl +++ b/src/mainboard/gigabyte/m57sli/dsdt.asl @@ -53,7 +53,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) External (HCLK) External (SBDN) External (HCDN) - + Method (_CRS, 0, NotSerialized) { Name (BUF0, ResourceTemplate () @@ -274,7 +274,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) Method (_CRS, 0, NotSerialized) { Name (BUF1, ResourceTemplate () { - IO (Decode16, 0x0378, 0x0378, 0x01, 0x08) + IO (Decode16, 0x0378, 0x0378, 0x01, 0x08) IRQNoFlags () {7} }) Return (BUF1) @@ -291,7 +291,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) Method (_CRS, 0, NotSerialized) { Name (BUF1, ResourceTemplate () { - IO (Decode16, 0x0378, 0x0378, 0x01, 0x04) + IO (Decode16, 0x0378, 0x0378, 0x01, 0x04) IO (Decode16, 0x0778, 0x0778, 0x01, 0x04) IRQNoFlags() {7} DMA (Compatibility, NotBusMaster, Transfer8) {0,1,3} diff --git a/src/mainboard/gigabyte/m57sli/get_bus_conf.c b/src/mainboard/gigabyte/m57sli/get_bus_conf.c index 4d381a6e8e..cad922f16a 100644 --- a/src/mainboard/gigabyte/m57sli/get_bus_conf.c +++ b/src/mainboard/gigabyte/m57sli/get_bus_conf.c @@ -39,7 +39,7 @@ unsigned apicid_mcp55; -unsigned pci1234x[] = +unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail 0x0000ff0, @@ -51,7 +51,7 @@ unsigned pci1234x[] = // 0x0000ff0, // 0x0000ff0 }; -unsigned hcdnx[] = +unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, // 0x20202020, @@ -62,7 +62,7 @@ unsigned hcdnx[] = // 0x20202020, // 0x20202020, }; -unsigned bus_type[256]; +unsigned bus_type[256]; @@ -95,13 +95,13 @@ void get_bus_conf(void) for(i=0; i<8; i++) { bus_mcp55[i] = 0; } - + for(i=0;i<256; i++) { bus_type[i] = 0; } bus_type[0] = 1; //pci - + bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff; bus_type[bus_mcp55[0]] = 1; @@ -139,8 +139,8 @@ void get_bus_conf(void) /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS==1 apicid_base = get_apicid_base(1); -#else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; +#else + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif apicid_mcp55 = apicid_base+0; diff --git a/src/mainboard/gigabyte/m57sli/irq_tables.c b/src/mainboard/gigabyte/m57sli/irq_tables.c index 5cb6d8420c..bc6aded97f 100644 --- a/src/mainboard/gigabyte/m57sli/irq_tables.c +++ b/src/mainboard/gigabyte/m57sli/irq_tables.c @@ -19,7 +19,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up @@ -33,11 +33,11 @@ #include <cpu/amd/amdk8_sysconf.h> -static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, +static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; + pirq_info->bus = bus; pirq_info->devfn = devfn; pirq_info->irq[0].link = link0; pirq_info->irq[0].bitmap = bitmap0; @@ -79,15 +79,15 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq = (void *)(addr); v = (uint8_t *)(addr); - + pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - + pirq->rtr_bus = bus_mcp55[0]; pirq->rtr_devfn = ((sbdn+6)<<3)|0; pirq->exclusive_irqs = 0; - + pirq->rtr_vendor = 0x10de; pirq->rtr_device = 0x0370; @@ -100,11 +100,11 @@ unsigned long write_pirq_routing_table(unsigned long addr) //pci bridge write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; - - pirq->size = 32 + 16 * slot_num; + + pirq->size = 32 + 16 * slot_num; for (i = 0; i < pirq->size; i++) - sum += v[i]; + sum += v[i]; sum = pirq->checksum - sum; diff --git a/src/mainboard/gigabyte/m57sli/mptable.c b/src/mainboard/gigabyte/m57sli/mptable.c index 93e6c274c9..3aad7e281f 100644 --- a/src/mainboard/gigabyte/m57sli/mptable.c +++ b/src/mainboard/gigabyte/m57sli/mptable.c @@ -32,7 +32,7 @@ extern unsigned char bus_mcp55[8]; //1 extern unsigned apicid_mcp55; -extern unsigned bus_type[256]; +extern unsigned bus_type[256]; @@ -94,7 +94,7 @@ static void *smp_write_config_table(void *v) } } - /*I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ + /*I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_mcp55, 0x0); /* ISA ints are edge-triggered, and usually originate from the ISA bus, @@ -122,7 +122,7 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,\ bus_mcp55[bus], (((dev)<<2)|(fn)), apicid_mcp55, (pin)) - PCI_INT(0,sbdn+1,1, 10); /* SMBus */ + PCI_INT(0,sbdn+1,1, 10); /* SMBus */ PCI_INT(0,sbdn+2,0, 22); /* USB */ PCI_INT(0,sbdn+2,1, 23); /* USB */ PCI_INT(0,sbdn+4,0, 21); /* IDE */ @@ -144,8 +144,8 @@ static void *smp_write_config_table(void *v) } /* On bus 1: the PCI bus slots... - pyhsical PCI slots are j = 7,8 - FireWire is j = 10 + pyhsical PCI slots are j = 7,8 + FireWire is j = 10 */ k=2; for(i=0; i<4; i++){ diff --git a/src/mainboard/gigabyte/m57sli/resourcemap.c b/src/mainboard/gigabyte/m57sli/resourcemap.c index 847cd86e65..43ff3ed11a 100644 --- a/src/mainboard/gigabyte/m57sli/resourcemap.c +++ b/src/mainboard/gigabyte/m57sli/resourcemap.c @@ -161,7 +161,7 @@ static void setup_mb_resource_map(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, @@ -199,7 +199,7 @@ static void setup_mb_resource_map(void) * [31:25] Reserved */ // PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000, - PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, @@ -217,7 +217,7 @@ static void setup_mb_resource_map(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -225,7 +225,7 @@ static void setup_mb_resource_map(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033, @@ -270,9 +270,9 @@ static void setup_mb_resource_map(void) * This field defines the highest bus number in configuration region i */ // PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of cpu 0 --> Nvidia MCP55 */ - PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, }; diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index 1e3bee8845..3f2f5e6f53 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -39,7 +39,7 @@ #endif #define DBGP_DEFAULT 7 - + #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -123,7 +123,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" -#include "resourcemap.c" +#include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" @@ -142,13 +142,13 @@ static void sio_setup(void) uint8_t byte; byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); - byte |= 0x20; + byte |= 0x20; pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); - + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); dword |= (1<<0); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); - + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); dword |= (1<<16); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); @@ -165,7 +165,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) (0xa<<3)|5, (0xa<<3)|7, 0, 0, }; - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); int needs_reset = 0; @@ -209,7 +209,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_mb_resource_map(); uart_init(); - + /* Halt if there was a built in self test failure */ report_bist_failure(bist); @@ -281,7 +281,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) //It's the time to set ctrl in sysinfo now; fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); - enable_smbus(); + enable_smbus(); /* all ap stopped? */ diff --git a/src/mainboard/hp/Kconfig b/src/mainboard/hp/Kconfig index f216a7e58d..36857e5f87 100644 --- a/src/mainboard/hp/Kconfig +++ b/src/mainboard/hp/Kconfig @@ -1,7 +1,7 @@ choice prompt "Mainboard model" depends on VENDOR_HP - + source "src/mainboard/hp/dl145_g3/Kconfig" source "src/mainboard/hp/e_vectra_p2706t/Kconfig" diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index 2e4d4109df..799e3fa7e1 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -185,7 +185,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) DIMM5, DIMM7, 0, 0, }; - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); int needs_reset; diff --git a/src/mainboard/ibm/Kconfig b/src/mainboard/ibm/Kconfig index d3d4f292e1..d9d1774532 100644 --- a/src/mainboard/ibm/Kconfig +++ b/src/mainboard/ibm/Kconfig @@ -1,7 +1,7 @@ choice prompt "Mainboard model" depends on VENDOR_IBM - + source "src/mainboard/ibm/e325/Kconfig" source "src/mainboard/ibm/e326/Kconfig" diff --git a/src/mainboard/ibm/e325/devicetree.cb b/src/mainboard/ibm/e325/devicetree.cb index 4db7c0005e..1b63301c09 100644 --- a/src/mainboard/ibm/e325/devicetree.cb +++ b/src/mainboard/ibm/e325/devicetree.cb @@ -18,7 +18,7 @@ chip northbridge/amd/amdk8/root_complex end device pci 1.0 on chip superio/nsc/pc87366 - device pnp 2e.0 off # Floppy + device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 @@ -45,7 +45,7 @@ chip northbridge/amd/amdk8/root_complex device pnp 2e.7 off end # GPIO device pnp 2e.8 off end # ACB device pnp 2e.9 off end # FSCM - device pnp 2e.a off end # WDT + device pnp 2e.a off end # WDT end end device pci 1.1 on end @@ -54,7 +54,7 @@ chip northbridge/amd/amdk8/root_complex device pci 1.5 off end device pci 1.6 off end end - end # device pci 18.0 + end # device pci 18.0 device pci 18.0 on end # LDT2 device pci 18.1 on end device pci 18.2 on end @@ -68,7 +68,7 @@ chip northbridge/amd/amdk8/root_complex device pci 19.2 on end device pci 19.3 on end end - end + end device apic_cluster 0 on chip cpu/amd/socket_940 device apic 0 on end diff --git a/src/mainboard/ibm/e325/irq_tables.c b/src/mainboard/ibm/e325/irq_tables.c index a9e8d07166..e537b65ab1 100644 --- a/src/mainboard/ibm/e325/irq_tables.c +++ b/src/mainboard/ibm/e325/irq_tables.c @@ -12,7 +12,7 @@ {linkc, AVAILABLE_IRQS}, {linkd, AVAILABLE_IRQS}}, slot, 0} /* Each IRQ_SLOT entry consists of: - * bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu + * bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ const struct irq_routing_table intel_irq_routing_table = { diff --git a/src/mainboard/ibm/e325/resourcemap.c b/src/mainboard/ibm/e325/resourcemap.c index b80347eb0c..85aafbf5a7 100644 --- a/src/mainboard/ibm/e325/resourcemap.c +++ b/src/mainboard/ibm/e325/resourcemap.c @@ -134,7 +134,7 @@ static void setup_ibm_e325_resource_map(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ @@ -143,8 +143,8 @@ static void setup_ibm_e325_resource_map(void) //PCI_ADDR(0, 0x18, 1, 0xbc), 0x48, 0x0, // PCI_ADDR(0, 0x18, 1, 0xb8), 0xf0, 0x0, - PCI_ADDR(0, 0x18, 1, 0xb4), 0x48, 0xfec010, - PCI_ADDR(0, 0x18, 1, 0xb0), 0xf0, 0xfec003, + PCI_ADDR(0, 0x18, 1, 0xb4), 0x48, 0xfec010, + PCI_ADDR(0, 0x18, 1, 0xb0), 0xf0, 0xfec003, //PCI_ADDR(0, 0x18, 1, 0xb4), 0x48, 0x0, //PCI_ADDR(0, 0x18, 1, 0xb0), 0xf0, 0x0, @@ -153,19 +153,19 @@ static void setup_ibm_e325_resource_map(void) //PCI_ADDR(0, 0x18, 1, 0xac), 0x48, 0x0, //PCI_ADDR(0, 0x18, 1, 0xa8), 0xf0, 0x0, - PCI_ADDR(0, 0x18, 1, 0xa4), 0x48, 0xfed010, + PCI_ADDR(0, 0x18, 1, 0xa4), 0x48, 0xfed010, PCI_ADDR(0, 0x18, 1, 0xa0), 0xf0, 0xfed003, //PCI_ADDR(0, 0x18, 1, 0xa4), 0x48, 0x0, //PCI_ADDR(0, 0x18, 1, 0xa0), 0xf0, 0x0, - PCI_ADDR(0, 0x18, 1, 0x9c), 0x48, 0x0, - PCI_ADDR(0, 0x18, 1, 0x98), 0xf0, 0x0, - PCI_ADDR(0, 0x18, 1, 0x94), 0x48, 0x0, - PCI_ADDR(0, 0x18, 1, 0x90), 0xf0, 0x0, - PCI_ADDR(0, 0x18, 1, 0x8c), 0x48, 0x0, - PCI_ADDR(0, 0x18, 1, 0x88), 0xf0, 0x0, - PCI_ADDR(0, 0x18, 1, 0x84), 0x48, 0x0, - PCI_ADDR(0, 0x18, 1, 0x80), 0xf0, 0x0, + PCI_ADDR(0, 0x18, 1, 0x9c), 0x48, 0x0, + PCI_ADDR(0, 0x18, 1, 0x98), 0xf0, 0x0, + PCI_ADDR(0, 0x18, 1, 0x94), 0x48, 0x0, + PCI_ADDR(0, 0x18, 1, 0x90), 0xf0, 0x0, + PCI_ADDR(0, 0x18, 1, 0x8c), 0x48, 0x0, + PCI_ADDR(0, 0x18, 1, 0x88), 0xf0, 0x0, + PCI_ADDR(0, 0x18, 1, 0x84), 0x48, 0x0, + PCI_ADDR(0, 0x18, 1, 0x80), 0xf0, 0x0, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 * F1:0xCC i = 1 @@ -205,7 +205,7 @@ static void setup_ibm_e325_resource_map(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -213,17 +213,17 @@ static void setup_ibm_e325_resource_map(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(0, 0x18, 1, 0xdc), 0xFE000FC8, 0x1fff010, - PCI_ADDR(0, 0x18, 1, 0xd8), 0xFE000FCC, 0x33, - PCI_ADDR(0, 0x18, 1, 0xd4), 0xFE000FC8, 0x0, - PCI_ADDR(0, 0x18, 1, 0xd0), 0xFE000FCC, 0x0, - PCI_ADDR(0, 0x18, 1, 0xcc), 0xFE000FC8, 0x0, - PCI_ADDR(0, 0x18, 1, 0xc8), 0xFE000FCC, 0x0, - PCI_ADDR(0, 0x18, 1, 0xc4), 0xFE000FC8, 0x0, - PCI_ADDR(0, 0x18, 1, 0xc0), 0xFE000FCC, 0x0, + PCI_ADDR(0, 0x18, 1, 0xdc), 0xFE000FC8, 0x1fff010, + PCI_ADDR(0, 0x18, 1, 0xd8), 0xFE000FCC, 0x33, + PCI_ADDR(0, 0x18, 1, 0xd4), 0xFE000FC8, 0x0, + PCI_ADDR(0, 0x18, 1, 0xd0), 0xFE000FCC, 0x0, + PCI_ADDR(0, 0x18, 1, 0xcc), 0xFE000FC8, 0x0, + PCI_ADDR(0, 0x18, 1, 0xc8), 0xFE000FCC, 0x0, + PCI_ADDR(0, 0x18, 1, 0xc4), 0xFE000FC8, 0x0, + PCI_ADDR(0, 0x18, 1, 0xc0), 0xFE000FCC, 0x0, /* Config Base and Limit i Registers * F1:0xE0 i = 0 * F1:0xE4 i = 1 @@ -260,10 +260,10 @@ static void setup_ibm_e325_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ - PCI_ADDR(0, 0x18, 1, 0xe0), 0x0000FC88, 0xff040103, - PCI_ADDR(0, 0x18, 1, 0xe4), 0x0000FC88, 0, - PCI_ADDR(0, 0x18, 1, 0xe8), 0x0000FC88, 0, - PCI_ADDR(0, 0x18, 1, 0xec), 0x0000FC88, 0, + PCI_ADDR(0, 0x18, 1, 0xe0), 0x0000FC88, 0xff040103, + PCI_ADDR(0, 0x18, 1, 0xe4), 0x0000FC88, 0, + PCI_ADDR(0, 0x18, 1, 0xe8), 0x0000FC88, 0, + PCI_ADDR(0, 0x18, 1, 0xec), 0x0000FC88, 0, }; int max; max = ARRAY_SIZE(register_values); diff --git a/src/mainboard/ibm/e325/romstage.c b/src/mainboard/ibm/e325/romstage.c index 0200fcd040..7697450b0e 100644 --- a/src/mainboard/ibm/e325/romstage.c +++ b/src/mainboard/ibm/e325/romstage.c @@ -1,4 +1,4 @@ - + #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -142,7 +142,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_ibm_e325_resource_map(); needs_reset = setup_coherent_ht_domain(); - + #if CONFIG_LOGICAL_CPUS==1 // It is said that we should start core1 after all core0 launched start_other_cores(); diff --git a/src/mainboard/ibm/e326/devicetree.cb b/src/mainboard/ibm/e326/devicetree.cb index a8576968cb..f1759dd81e 100644 --- a/src/mainboard/ibm/e326/devicetree.cb +++ b/src/mainboard/ibm/e326/devicetree.cb @@ -25,7 +25,7 @@ chip northbridge/amd/amdk8/root_complex end device pci 1.0 on chip superio/nsc/pc87366 - device pnp 2e.0 off # Floppy + device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 @@ -52,7 +52,7 @@ chip northbridge/amd/amdk8/root_complex device pnp 2e.7 off end # GPIO device pnp 2e.8 off end # ACB device pnp 2e.9 off end # FSCM - device pnp 2e.a off end # WDT + device pnp 2e.a off end # WDT end end device pci 1.1 on end @@ -63,12 +63,12 @@ chip northbridge/amd/amdk8/root_complex register "ide0_enable" = "1" register "ide1_enable" = "1" end - end # device pci 18.0 + end # device pci 18.0 device pci 18.0 on end # LDT2 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end end - end + end end diff --git a/src/mainboard/ibm/e326/irq_tables.c b/src/mainboard/ibm/e326/irq_tables.c index a9e8d07166..e537b65ab1 100644 --- a/src/mainboard/ibm/e326/irq_tables.c +++ b/src/mainboard/ibm/e326/irq_tables.c @@ -12,7 +12,7 @@ {linkc, AVAILABLE_IRQS}, {linkd, AVAILABLE_IRQS}}, slot, 0} /* Each IRQ_SLOT entry consists of: - * bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu + * bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ const struct irq_routing_table intel_irq_routing_table = { diff --git a/src/mainboard/ibm/e326/resourcemap.c b/src/mainboard/ibm/e326/resourcemap.c index a37496879b..98fdcc0ec6 100644 --- a/src/mainboard/ibm/e326/resourcemap.c +++ b/src/mainboard/ibm/e326/resourcemap.c @@ -134,7 +134,7 @@ static void setup_ibm_e326_resource_map(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ @@ -143,8 +143,8 @@ static void setup_ibm_e326_resource_map(void) //PCI_ADDR(0, 0x18, 1, 0xbc), 0x48, 0x0, // PCI_ADDR(0, 0x18, 1, 0xb8), 0xf0, 0x0, - PCI_ADDR(0, 0x18, 1, 0xb4), 0x48, 0xfec010, - PCI_ADDR(0, 0x18, 1, 0xb0), 0xf0, 0xfec003, + PCI_ADDR(0, 0x18, 1, 0xb4), 0x48, 0xfec010, + PCI_ADDR(0, 0x18, 1, 0xb0), 0xf0, 0xfec003, //PCI_ADDR(0, 0x18, 1, 0xb4), 0x48, 0x0, //PCI_ADDR(0, 0x18, 1, 0xb0), 0xf0, 0x0, @@ -153,19 +153,19 @@ static void setup_ibm_e326_resource_map(void) //PCI_ADDR(0, 0x18, 1, 0xac), 0x48, 0x0, //PCI_ADDR(0, 0x18, 1, 0xa8), 0xf0, 0x0, - PCI_ADDR(0, 0x18, 1, 0xa4), 0x48, 0xfed010, + PCI_ADDR(0, 0x18, 1, 0xa4), 0x48, 0xfed010, PCI_ADDR(0, 0x18, 1, 0xa0), 0xf0, 0xfed003, //PCI_ADDR(0, 0x18, 1, 0xa4), 0x48, 0x0, //PCI_ADDR(0, 0x18, 1, 0xa0), 0xf0, 0x0, - PCI_ADDR(0, 0x18, 1, 0x9c), 0x48, 0x0, - PCI_ADDR(0, 0x18, 1, 0x98), 0xf0, 0x0, - PCI_ADDR(0, 0x18, 1, 0x94), 0x48, 0x0, - PCI_ADDR(0, 0x18, 1, 0x90), 0xf0, 0x0, - PCI_ADDR(0, 0x18, 1, 0x8c), 0x48, 0x0, - PCI_ADDR(0, 0x18, 1, 0x88), 0xf0, 0x0, - PCI_ADDR(0, 0x18, 1, 0x84), 0x48, 0x0, - PCI_ADDR(0, 0x18, 1, 0x80), 0xf0, 0x0, + PCI_ADDR(0, 0x18, 1, 0x9c), 0x48, 0x0, + PCI_ADDR(0, 0x18, 1, 0x98), 0xf0, 0x0, + PCI_ADDR(0, 0x18, 1, 0x94), 0x48, 0x0, + PCI_ADDR(0, 0x18, 1, 0x90), 0xf0, 0x0, + PCI_ADDR(0, 0x18, 1, 0x8c), 0x48, 0x0, + PCI_ADDR(0, 0x18, 1, 0x88), 0xf0, 0x0, + PCI_ADDR(0, 0x18, 1, 0x84), 0x48, 0x0, + PCI_ADDR(0, 0x18, 1, 0x80), 0xf0, 0x0, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 * F1:0xCC i = 1 @@ -205,7 +205,7 @@ static void setup_ibm_e326_resource_map(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -213,17 +213,17 @@ static void setup_ibm_e326_resource_map(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(0, 0x18, 1, 0xdc), 0xFE000FC8, 0x1fff010, - PCI_ADDR(0, 0x18, 1, 0xd8), 0xFE000FCC, 0x33, - PCI_ADDR(0, 0x18, 1, 0xd4), 0xFE000FC8, 0x0, - PCI_ADDR(0, 0x18, 1, 0xd0), 0xFE000FCC, 0x0, - PCI_ADDR(0, 0x18, 1, 0xcc), 0xFE000FC8, 0x0, - PCI_ADDR(0, 0x18, 1, 0xc8), 0xFE000FCC, 0x0, - PCI_ADDR(0, 0x18, 1, 0xc4), 0xFE000FC8, 0x0, - PCI_ADDR(0, 0x18, 1, 0xc0), 0xFE000FCC, 0x0, + PCI_ADDR(0, 0x18, 1, 0xdc), 0xFE000FC8, 0x1fff010, + PCI_ADDR(0, 0x18, 1, 0xd8), 0xFE000FCC, 0x33, + PCI_ADDR(0, 0x18, 1, 0xd4), 0xFE000FC8, 0x0, + PCI_ADDR(0, 0x18, 1, 0xd0), 0xFE000FCC, 0x0, + PCI_ADDR(0, 0x18, 1, 0xcc), 0xFE000FC8, 0x0, + PCI_ADDR(0, 0x18, 1, 0xc8), 0xFE000FCC, 0x0, + PCI_ADDR(0, 0x18, 1, 0xc4), 0xFE000FC8, 0x0, + PCI_ADDR(0, 0x18, 1, 0xc0), 0xFE000FCC, 0x0, /* Config Base and Limit i Registers * F1:0xE0 i = 0 * F1:0xE4 i = 1 @@ -260,10 +260,10 @@ static void setup_ibm_e326_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ - PCI_ADDR(0, 0x18, 1, 0xe0), 0x0000FC88, 0xff040103, - PCI_ADDR(0, 0x18, 1, 0xe4), 0x0000FC88, 0, - PCI_ADDR(0, 0x18, 1, 0xe8), 0x0000FC88, 0, - PCI_ADDR(0, 0x18, 1, 0xec), 0x0000FC88, 0, + PCI_ADDR(0, 0x18, 1, 0xe0), 0x0000FC88, 0xff040103, + PCI_ADDR(0, 0x18, 1, 0xe4), 0x0000FC88, 0, + PCI_ADDR(0, 0x18, 1, 0xe8), 0x0000FC88, 0, + PCI_ADDR(0, 0x18, 1, 0xec), 0x0000FC88, 0, }; int max; max = ARRAY_SIZE(register_values); diff --git a/src/mainboard/ibm/e326/romstage.c b/src/mainboard/ibm/e326/romstage.c index 527db2fa3e..0b38ec78fa 100644 --- a/src/mainboard/ibm/e326/romstage.c +++ b/src/mainboard/ibm/e326/romstage.c @@ -1,4 +1,4 @@ - + #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -142,7 +142,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_ibm_e326_resource_map(); needs_reset = setup_coherent_ht_domain(); - + #if CONFIG_LOGICAL_CPUS==1 // It is said that we should start core1 after all core0 launched start_other_cores(); diff --git a/src/mainboard/iei/nova4899r/irq_tables.c b/src/mainboard/iei/nova4899r/irq_tables.c index 5886c20077..7893e1032f 100644 --- a/src/mainboard/iei/nova4899r/irq_tables.c +++ b/src/mainboard/iei/nova4899r/irq_tables.c @@ -118,7 +118,7 @@ const struct irq_routing_table intel_irq_routing_table = { .slot = 0x2, }, */ - + /* * Definition for "slot#2". There is no real slot, * the network device is soldered... diff --git a/src/mainboard/iei/pcisa-lx-800-r10/Kconfig b/src/mainboard/iei/pcisa-lx-800-r10/Kconfig index 5180b84cf1..2678c149b1 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/Kconfig +++ b/src/mainboard/iei/pcisa-lx-800-r10/Kconfig @@ -13,7 +13,7 @@ config BOARD_IEI_PCISA_LX_800_R10 config MAINBOARD_DIR string - default iei/pcisa-lx-800-r10 + default iei/pcisa-lx-800-r10 depends on BOARD_IEI_PCISA_LX_800_R10 config MAINBOARD_PART_NUMBER diff --git a/src/mainboard/intel/d945gclf/acpi/i945_pci_irqs.asl b/src/mainboard/intel/d945gclf/acpi/i945_pci_irqs.asl index 93e4b87fee..de2ec481fb 100644 --- a/src/mainboard/intel/d945gclf/acpi/i945_pci_irqs.asl +++ b/src/mainboard/intel/d945gclf/acpi/i945_pci_irqs.asl @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* This is board specific information: IRQ routing for the +/* This is board specific information: IRQ routing for the * i945 */ diff --git a/src/mainboard/intel/d945gclf/acpi/ich7_pci_irqs.asl b/src/mainboard/intel/d945gclf/acpi/ich7_pci_irqs.asl index b3b60d6ece..931fbfdeb4 100644 --- a/src/mainboard/intel/d945gclf/acpi/ich7_pci_irqs.asl +++ b/src/mainboard/intel/d945gclf/acpi/ich7_pci_irqs.asl @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* This is board specific information: IRQ routing for the +/* This is board specific information: IRQ routing for the * 0:1e.0 PCI bridge of the ICH7 */ diff --git a/src/mainboard/intel/d945gclf/acpi/mainboard.asl b/src/mainboard/intel/d945gclf/acpi/mainboard.asl index 3d1ad0ea29..d321771c0a 100644 --- a/src/mainboard/intel/d945gclf/acpi/mainboard.asl +++ b/src/mainboard/intel/d945gclf/acpi/mainboard.asl @@ -28,7 +28,7 @@ Device (SLPB) Device (PWRB) { Name(_HID, EisaId("PNP0C0C")) - + // Wake Name(_PRW, Package(){0x1d, 0x04}) } diff --git a/src/mainboard/intel/d945gclf/acpi/platform.asl b/src/mainboard/intel/d945gclf/acpi/platform.asl index 7c5b9da429..0a7930a3cc 100644 --- a/src/mainboard/intel/d945gclf/acpi/platform.asl +++ b/src/mainboard/intel/d945gclf/acpi/platform.asl @@ -42,9 +42,9 @@ Method(TRAP, 1, Serialized) Return (SMIF) // Return value of SMI handler } -/* The _PIC method is called by the OS to choose between interrupt +/* The _PIC method is called by the OS to choose between interrupt * routing via the i8259 interrupt controller or the APIC. - * + * * _PIC is called with a parameter of 0 for i8259 configuration and * with a parameter of 1 for Local Apic/IOAPIC configuration. */ @@ -74,12 +74,12 @@ Method(_WAK,1) // Notify PCI Express slots in case a card // was inserted while a sleep state was active. - // Are we going to S3? + // Are we going to S3? If (LEqual(Arg0, 3)) { // .. } - // Are we going to S4? + // Are we going to S4? If (LEqual(Arg0, 4)) { // .. } diff --git a/src/mainboard/intel/d945gclf/acpi/thermal.asl b/src/mainboard/intel/d945gclf/acpi/thermal.asl index fb9d940955..fc79a35f61 100644 --- a/src/mainboard/intel/d945gclf/acpi/thermal.asl +++ b/src/mainboard/intel/d945gclf/acpi/thermal.asl @@ -25,7 +25,7 @@ Scope (\_TZ) { // FIXME these could/should be read from the - // GNVS area, so they can be controlled by + // GNVS area, so they can be controlled by // coreboot Name(TC1V, 0x04) Name(TC2V, 0x03) diff --git a/src/mainboard/intel/d945gclf/acpi_tables.c b/src/mainboard/intel/d945gclf/acpi_tables.c index b7f92114c5..afa695502f 100644 --- a/src/mainboard/intel/d945gclf/acpi_tables.c +++ b/src/mainboard/intel/d945gclf/acpi_tables.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or diff --git a/src/mainboard/intel/d945gclf/chip.h b/src/mainboard/intel/d945gclf/chip.h index 90e8c27999..4e1432de69 100644 --- a/src/mainboard/intel/d945gclf/chip.h +++ b/src/mainboard/intel/d945gclf/chip.h @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2007-2008 coresystems GmbH * * This program is free software; you can redistribute it and/or diff --git a/src/mainboard/intel/d945gclf/cmos.layout b/src/mainboard/intel/d945gclf/cmos.layout index e99c43d79b..9997584a54 100644 --- a/src/mainboard/intel/d945gclf/cmos.layout +++ b/src/mainboard/intel/d945gclf/cmos.layout @@ -1,6 +1,6 @@ # # This file is part of the coreboot project. -# +# # Copyright (C) 2007-2008 coresystems GmbH # # This program is free software; you can redistribute it and/or diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb index af5f22b302..01a0bc67a5 100644 --- a/src/mainboard/intel/d945gclf/devicetree.cb +++ b/src/mainboard/intel/d945gclf/devicetree.cb @@ -1,6 +1,6 @@ ## ## This file is part of the coreboot project. -## +## ## Copyright (C) 2007-2008 coresystems GmbH ## ## This program is free software; you can redistribute it and/or @@ -25,7 +25,7 @@ chip northbridge/intel/i945 end end - device pci_domain 0 on + device pci_domain 0 on device pci 00.0 on end # host bridge device pci 01.0 off end # i945 PCIe root port device pci 02.0 on end # vga controller @@ -66,7 +66,7 @@ chip northbridge/intel/i945 device pci 1d.3 on end # USB UHCI device pci 1d.7 on end # USB2 EHCI device pci 1e.0 on end # PCI bridge - #device pci 1e.2 off end # AC'97 Audio + #device pci 1e.2 off end # AC'97 Audio #device pci 1e.3 off end # AC'97 Modem device pci 1f.0 on # LPC bridge chip superio/smsc/lpc47m15x diff --git a/src/mainboard/intel/d945gclf/dsdt.asl b/src/mainboard/intel/d945gclf/dsdt.asl index 1b025994f0..bf57e74b21 100644 --- a/src/mainboard/intel/d945gclf/dsdt.asl +++ b/src/mainboard/intel/d945gclf/dsdt.asl @@ -34,7 +34,7 @@ DefinitionBlock( // General Purpose Events //#include "acpi/gpe.asl" - + // mainboard specific devices #include "acpi/mainboard.asl" diff --git a/src/mainboard/intel/d945gclf/mainboard_smi.c b/src/mainboard/intel/d945gclf/mainboard_smi.c index fc4c508194..c07a24c399 100644 --- a/src/mainboard/intel/d945gclf/mainboard_smi.c +++ b/src/mainboard/intel/d945gclf/mainboard_smi.c @@ -23,7 +23,7 @@ #include <cpu/x86/smm.h> #include "../../../southbridge/intel/i82801gx/i82801gx_nvs.h" -/* The southbridge SMI handler checks whether gnvs has a +/* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler */ extern global_nvs_t *gnvs; diff --git a/src/mainboard/intel/d945gclf/mptable.c b/src/mainboard/intel/d945gclf/mptable.c index 5d57f3d743..62850ebf1c 100644 --- a/src/mainboard/intel/d945gclf/mptable.c +++ b/src/mainboard/intel/d945gclf/mptable.c @@ -69,7 +69,7 @@ static void *smp_write_config_table(void *v) /* Legacy Interrupts */ - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, 0x2, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x1, 0x2, 0x1); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, 0x2, 0x2); diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index e3e5814d3e..45e9fb1341 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2007-2008 coresystems GmbH * * This program is free software; you can redistribute it and/or @@ -105,7 +105,7 @@ static void ich7_enable_lpc(void) static void early_superio_config_lpc47m15x(void) { device_t dev; - + dev=PNP_DEV(0x2e, LPC47M15X_SP1); pnp_enter_conf_state(dev); @@ -276,7 +276,7 @@ void main(unsigned long bist) /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); - + #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 dump_spd_registers(); #endif @@ -286,8 +286,8 @@ void main(unsigned long bist) /* Perform some initialization that must run before stage2 */ early_ich7_init(); - /* This should probably go away. Until now it is required - * and mainboard specific + /* This should probably go away. Until now it is required + * and mainboard specific */ rcba_config(); @@ -331,7 +331,7 @@ void main(unsigned long bist) * memory completely, but that's a wonderful clean up task for another * day. */ - if (resume_backup_memory) + if (resume_backup_memory) memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE); /* Magic for S3 resume */ diff --git a/src/mainboard/intel/d945gclf/rtl8168.c b/src/mainboard/intel/d945gclf/rtl8168.c index e278bcfb4e..04fd56ccb1 100644 --- a/src/mainboard/intel/d945gclf/rtl8168.c +++ b/src/mainboard/intel/d945gclf/rtl8168.c @@ -28,7 +28,7 @@ static void nic_init(struct device *dev) { printk(BIOS_DEBUG, "Initializing RTL8168 Gigabit Ethernet\n"); - // Nothing to do yet, but this has to be here to keep + // Nothing to do yet, but this has to be here to keep // coreboot from trying to execute an option ROM. } diff --git a/src/mainboard/intel/eagleheights/Kconfig b/src/mainboard/intel/eagleheights/Kconfig index 991fddf0e2..d04e79eafe 100644 --- a/src/mainboard/intel/eagleheights/Kconfig +++ b/src/mainboard/intel/eagleheights/Kconfig @@ -57,7 +57,7 @@ config MAX_CPUS int default 4 depends on BOARD_INTEL_EAGLEHEIGHTS - + config MAX_PHYSICAL_CPUS int default 2 diff --git a/src/mainboard/intel/jarrell/debug.c b/src/mainboard/intel/jarrell/debug.c index b4f2a185b3..87c67b5964 100644 --- a/src/mainboard/intel/jarrell/debug.c +++ b/src/mainboard/intel/jarrell/debug.c @@ -5,7 +5,7 @@ static void print_reg(unsigned char index) { unsigned char data; - + outb(index, 0x2e); data = inb(0x2f); print_debug("0x"); @@ -15,7 +15,7 @@ static void print_reg(unsigned char index) print_debug("\n"); return; } - + static void xbus_en(void) { /* select the XBUS function in the SIO */ @@ -25,7 +25,7 @@ static void xbus_en(void) outb(0x01, 0x2f); return; } - + static void setup_func(unsigned char func) { /* select the function in the SIO */ @@ -43,27 +43,27 @@ static void setup_func(unsigned char func) print_reg(0x75); return; } - + static void siodump(void) { int i; unsigned char data; - + print_debug("\n*** SERVER I/O REGISTERS ***\n"); for (i=0x10; i<=0x2d; i++) { print_reg((unsigned char)i); } -#if 0 +#if 0 print_debug("\n*** XBUS REGISTERS ***\n"); setup_func(0x0f); for (i=0xf0; i<=0xff; i++) { print_reg((unsigned char)i); } - + print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); setup_func(0x03); print_reg(0xf0); - + print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); setup_func(0x02); print_reg(0xf0); @@ -82,13 +82,13 @@ static void siodump(void) print_debug("\nGPDI 4: 0x"); print_debug_hex8(data); print_debug("\n"); - -#if 0 - + +#if 0 + print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); setup_func(0x0a); print_reg(0xf0); - + print_debug("\n*** FAN CONTROL REGISTERS ***\n"); setup_func(0x09); print_reg(0xf0); @@ -103,11 +103,11 @@ static void siodump(void) print_reg(0xf7); print_reg(0xfe); print_reg(0xff); - + print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); setup_func(0x14); print_reg(0xf0); -#endif +#endif return; } @@ -124,8 +124,8 @@ static void print_debug_pci_dev(unsigned dev) static void print_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -144,7 +144,7 @@ static void dump_pci_device(unsigned dev) int i; print_debug_pci_dev(dev); print_debug("\n"); - + for(i = 0; i <= 255; i++) { unsigned char val; if ((i & 0x0f) == 0) { @@ -164,19 +164,19 @@ static void dump_bar14(unsigned dev) { int i; unsigned long bar; - + print_debug("BAR 14 Dump\n"); - + bar = pci_read_config32(dev, 0x14); for(i = 0; i <= 0x300; i+=4) { -#if 0 +#if 0 unsigned char val; if ((i & 0x0f) == 0) { print_debug_hex8(i); print_debug_char(':'); } val = pci_read_config8(dev, i); -#endif +#endif if((i%4)==0) { print_debug("\n"); print_debug_hex16(i); @@ -191,8 +191,8 @@ static void dump_bar14(unsigned dev) static void dump_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -215,8 +215,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel0[i]; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".0: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { @@ -241,8 +241,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel1[i]; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".1: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { @@ -278,7 +278,7 @@ void dump_spd_registers(void) print_debug("\n"); print_debug("dimm "); print_debug_hex8(device); - + for(i = 0; (i < 256) ; i++) { unsigned char byte; if ((i % 16) == 0) { @@ -291,7 +291,7 @@ void dump_spd_registers(void) print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); @@ -311,7 +311,7 @@ void dump_ipmi_registers(void) print_debug("\n"); print_debug("ipmi "); print_debug_hex8(device); - + for(i = 0; (i < 8) ; i++) { unsigned char byte; status = smbus_read_byte(device, 2); @@ -319,7 +319,7 @@ void dump_ipmi_registers(void) print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); @@ -327,4 +327,4 @@ void dump_ipmi_registers(void) device += SMBUS_MEM_DEVICE_INC; print_debug("\n"); } -} +} diff --git a/src/mainboard/intel/jarrell/devicetree.cb b/src/mainboard/intel/jarrell/devicetree.cb index 32f70e3e85..3a40899b29 100644 --- a/src/mainboard/intel/jarrell/devicetree.cb +++ b/src/mainboard/intel/jarrell/devicetree.cb @@ -1,9 +1,9 @@ chip northbridge/intel/e7520 - device pci_domain 0 on + device pci_domain 0 on device pci 00.0 on end device pci 00.1 on end device pci 01.0 on end - device pci 02.0 on + device pci 02.0 on chip southbridge/intel/pxhd # pxhd1 device pci 00.0 on end device pci 00.1 on end @@ -28,7 +28,7 @@ chip northbridge/intel/e7520 device pci 0c.0 on end end end - device pci 1f.0 on + device pci 1f.0 on chip superio/nsc/pc87427 device pnp 2e.0 off end device pnp 2e.2 on @@ -60,7 +60,7 @@ chip northbridge/intel/e7520 end device pci 1f.1 on end device pci 1f.2 off end - device pci 1f.3 on end + device pci 1f.3 on end device pci 1f.5 off end device pci 1f.6 off end register "gpio[40]" = "ICH5R_GPIO_USE_AS_GPIO" diff --git a/src/mainboard/intel/jarrell/jarrell_fixups.c b/src/mainboard/intel/jarrell/jarrell_fixups.c index 7fb5a20dbb..1261e61046 100644 --- a/src/mainboard/intel/jarrell/jarrell_fixups.c +++ b/src/mainboard/intel/jarrell/jarrell_fixups.c @@ -21,7 +21,7 @@ static void mch_reset(void) value = inl(base); value |= (1 <<19); outl(value, base); - + /* Pull GPIO 19 low */ value = inl(base + 0x0c); value &= ~(1 << 19); @@ -38,7 +38,7 @@ static void mainboard_set_e7520_pll(unsigned bits) /* currently only handle the Jarrell/PC87427 case */ dev = PC87427_GPIO_DEV; - + pnp_set_logical_device(dev); gpio_index = pnp_read_iobase(dev, 0x60); @@ -66,7 +66,7 @@ static void mainboard_set_e7520_pll(unsigned bits) // mch_reset(); full_reset(); } - return; + return; } static void mainboard_set_e7520_leds(void) @@ -77,7 +77,7 @@ static void mainboard_set_e7520_leds(void) /* currently only handle the Jarrell/PC87427 case */ dev = PC87427_GPIO_DEV; - + pnp_set_logical_device(dev); /* enable */ @@ -88,17 +88,17 @@ static void mainboard_set_e7520_leds(void) /* Set auto mode for dimm leds and post */ outb(0xf0,0x2e); - outb(0x70,0x2f); + outb(0x70,0x2f); outb(0xf4,0x2e); - outb(0x30,0x2f); + outb(0x30,0x2f); outb(0xf5,0x2e); - outb(0x88,0x2f); + outb(0x88,0x2f); outb(0xf6,0x2e); - outb(0x00,0x2f); + outb(0x00,0x2f); outb(0xf7,0x2e); - outb(0x90,0x2f); + outb(0x90,0x2f); outb(0xf8,0x2e); - outb(0x00,0x2f); + outb(0x00,0x2f); /* Turn the leds off */ outb(0x00,0x88); @@ -106,12 +106,12 @@ static void mainboard_set_e7520_leds(void) /* Disable the ports */ outb(0xf5,0x2e); - outb(0x00,0x2f); + outb(0x00,0x2f); outb(0xf7,0x2e); - outb(0x00,0x2f); + outb(0x00,0x2f); outb(0xf4,0x2e); - outb(0x00,0x2f); - - return; + outb(0x00,0x2f); + + return; } diff --git a/src/mainboard/intel/jarrell/mptable.c b/src/mainboard/intel/jarrell/mptable.c index 73aa575540..1386c16183 100644 --- a/src/mainboard/intel/jarrell/mptable.c +++ b/src/mainboard/intel/jarrell/mptable.c @@ -38,7 +38,7 @@ static void *smp_write_config_table(void *v) mc->reserved = 0; smp_write_processors(mc); - + { device_t dev; @@ -102,7 +102,7 @@ static void *smp_write_config_table(void *v) } } } - + /* define bus and isa numbers */ for(bus_num = 0; bus_num < bus_isa; bus_num++) { smp_write_bus(mc, bus_num, "PCI "); @@ -165,7 +165,7 @@ static void *smp_write_config_table(void *v) } } } - + /* ISA backward compatibility interrupts */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x00, 0x08, 0x00); diff --git a/src/mainboard/intel/jarrell/romstage.c b/src/mainboard/intel/jarrell/romstage.c index d3f6c7a707..823519984e 100644 --- a/src/mainboard/intel/jarrell/romstage.c +++ b/src/mainboard/intel/jarrell/romstage.c @@ -51,8 +51,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void main(unsigned long bist) { /* - * - * + * + * */ static const struct mem_controller mch[] = { { @@ -117,7 +117,7 @@ static void main(unsigned long bist) disable_watchdogs(); power_down_reset_check(); // dump_ipmi_registers(); - mainboard_set_e7520_leds(); + mainboard_set_e7520_leds(); sdram_initialize(ARRAY_SIZE(mch), mch); ich5_watchdog_on(); #if 0 @@ -128,7 +128,7 @@ static void main(unsigned long bist) dump_bar14(PCI_DEV(0, 0x00, 0)); #endif -#if 0 // temporarily disabled +#if 0 // temporarily disabled /* Check the first 1M */ // ram_check(0x00000000, 0x000100000); // ram_check(0x00000000, 0x000a0000); @@ -138,9 +138,9 @@ static void main(unsigned long bist) #if 0 ram_check(0x00000000, 0x02000000); #endif - + #endif -#if 0 +#if 0 while(1) { hlt(); } diff --git a/src/mainboard/intel/jarrell/watchdog.c b/src/mainboard/intel/jarrell/watchdog.c index 90782d9fbf..f7c42caa78 100644 --- a/src/mainboard/intel/jarrell/watchdog.c +++ b/src/mainboard/intel/jarrell/watchdog.c @@ -29,17 +29,17 @@ static void disable_ich5_watchdog(void) value = pci_read_config16(dev, 0x04); value |= (1 << 10); pci_write_config16(dev, 0x04, value); - + /* Set and enable acpibase */ pci_write_config32(dev, 0x40, ICH5_WDBASE | 1); pci_write_config8(dev, 0x44, 0x10); base = ICH5_WDBASE + 0x60; - + /* Set bit 11 in TCO1_CNT */ value = inw(base + 0x08); value |= 1 << 11; outw(value, base + 0x08); - + /* Clear TCO timeout status */ outw(0x0008, base + 0x04); outw(0x0002, base + 0x06); @@ -83,7 +83,7 @@ static void disable_jarell_frb3(void) outl(value, base + 0x38); value &= ~(1 << 16); outl(value, base + 0x38); - + } static void disable_watchdogs(void) @@ -114,12 +114,12 @@ static void ich5_watchdog_on(void) value = pci_read_config16(dev, 0x04); value |= (1 << 10); pci_write_config16(dev, 0x04, value); - + /* Set and enable acpibase */ pci_write_config32(dev, 0x40, ICH5_WDBASE | 1); pci_write_config8(dev, 0x44, 0x10); base = ICH5_WDBASE + 0x60; - + /* Clear TCO timeout status */ outw(0x0008, base + 0x04); outw(0x0002, base + 0x06); @@ -132,7 +132,7 @@ static void ich5_watchdog_on(void) /* clear bit 11 in TCO1_CNT to start watchdog */ value = inw(base + 0x08); value &= ~(1 << 11); - outw(value, base + 0x08); + outw(value, base + 0x08); print_debug("Watchdog ICH5 enabled\n"); } diff --git a/src/mainboard/intel/xe7501devkit/acpi_tables.c b/src/mainboard/intel/xe7501devkit/acpi_tables.c index fd43eb693b..1188467f20 100644 --- a/src/mainboard/intel/xe7501devkit/acpi_tables.c +++ b/src/mainboard/intel/xe7501devkit/acpi_tables.c @@ -38,21 +38,21 @@ unsigned long acpi_fill_madt(unsigned long current) device_t dev = 0; struct resource* res = NULL; - + // SJM: Hard-code CPU LAPIC entries for now // Use SourcePoint numbering of processors current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 6); current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 7); current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 2, 0); current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 3, 1); - + // Southbridge IOAPIC current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_ICH3, 0xfec00000, irq_start); irq_start += INTEL_IOAPIC_NUM_INTERRUPTS; // P64H2#2 Bus A IOAPIC - dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0)); + dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0)); if (!dev) BUG(); // Config.lb error? res = find_resource(dev, PCI_BASE_ADDRESS_0); @@ -60,7 +60,7 @@ unsigned long acpi_fill_madt(unsigned long current) irq_start += INTEL_IOAPIC_NUM_INTERRUPTS; // P64H2#2 Bus B IOAPIC - dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0)); + dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0)); if (!dev) BUG(); // Config.lb error? res = find_resource(dev, PCI_BASE_ADDRESS_0); @@ -69,7 +69,7 @@ unsigned long acpi_fill_madt(unsigned long current) // P64H2#1 Bus A IOAPIC - dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(30, 0)); + dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(30, 0)); if (!dev) BUG(); // Config.lb error? res = find_resource(dev, PCI_BASE_ADDRESS_0); @@ -77,7 +77,7 @@ unsigned long acpi_fill_madt(unsigned long current) irq_start += INTEL_IOAPIC_NUM_INTERRUPTS; // P64H2#1 Bus B IOAPIC - dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(28, 0)); + dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(28, 0)); if (!dev) BUG(); // Config.lb error? res = find_resource(dev, PCI_BASE_ADDRESS_0); @@ -104,7 +104,7 @@ unsigned long write_acpi_tables(unsigned long start) /* Align ACPI tables to 16byte */ start = ( start + 0x0f ) & -0x10; current = start; - + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); /* We need at least an RSDP and an RSDT Table */ @@ -115,10 +115,10 @@ unsigned long write_acpi_tables(unsigned long start) /* clear all table memory */ memset((void *)start, 0, current - start); - + acpi_write_rsdp(rsdp, rsdt, NULL); acpi_write_rsdt(rsdt); - + /* * We explicitly add these tables later on: */ diff --git a/src/mainboard/intel/xe7501devkit/cmos.layout b/src/mainboard/intel/xe7501devkit/cmos.layout index 494af5bb61..baae5eb617 100644 --- a/src/mainboard/intel/xe7501devkit/cmos.layout +++ b/src/mainboard/intel/xe7501devkit/cmos.layout @@ -1,4 +1,4 @@ -# NOTE: This file must be in UNIX format (not DOS) or build_opt_tbl fails: +# NOTE: This file must be in UNIX format (not DOS) or build_opt_tbl fails: # "Error - Name is an invalid identifier in line" entries diff --git a/src/mainboard/intel/xe7501devkit/ioapic.h b/src/mainboard/intel/xe7501devkit/ioapic.h index 30ae8e7a73..9ac2aee3f8 100644 --- a/src/mainboard/intel/xe7501devkit/ioapic.h +++ b/src/mainboard/intel/xe7501devkit/ioapic.h @@ -1,6 +1,6 @@ -// IOAPIC addresses determined by coreboot enumeration. +// IOAPIC addresses determined by coreboot enumeration. // Someday add functions to get APIC IDs and versions from the chips themselves. - + #define IOAPIC_ICH3 2 #define IOAPIC_P64H2_2_BUS_B 3 // IOAPIC 3 at 01:1c.0 MBAR = fe300000 DataAddr = fe300010 #define IOAPIC_P64H2_2_BUS_A 4 // IOAPIC 4 at 01:1e.0 MBAR = fe301000 DataAddr = fe301010 diff --git a/src/mainboard/intel/xe7501devkit/irq_tables.c b/src/mainboard/intel/xe7501devkit/irq_tables.c index b329351b6b..951b08f5f8 100644 --- a/src/mainboard/intel/xe7501devkit/irq_tables.c +++ b/src/mainboard/intel/xe7501devkit/irq_tables.c @@ -35,17 +35,17 @@ const struct irq_routing_table intel_irq_routing_table = { // bitmap of 0xdcf8 == routable to IRQ3-IRQ7, IRQ10-IRQ12, or IRQ14-IRQ15 // ICH-3 doesn't allow SERIRQ or PCI message to generate IRQ0, IRQ2, IRQ8, or IRQ13 // Not sure why IRQ9 isn't routable (inherited from Tyan S2735) - + // INTA# INTB# INTC# INTD# // bus, device # {link , bitmap}, {link , bitmap}, {link , bitmap}, {link , bitmap}, slot, rfu - + {PCI_BUS_CHIPSET, PCI_DEVFN(31, 0), {{PIRQ_C, 0xdcf8}, {PIRQ_B, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, // IDE / SMBus {PCI_BUS_CHIPSET, PCI_DEVFN(29, 0), {{PIRQ_A, 0xdcf8}, {PIRQ_D, 0xdcf8}, {PIRQ_C, 0xdcf8}, UNUSED_INTERRUPT}, 0, 0}, // USB 1.1 - + // P64H2#2 Bus A {PCI_BUS_P64H2_2_A, PCI_DEVFN(1, 0), {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, // SCSI // NOTE: Hotplug disabled on this bus - + // P64H2#2 Bus B {PCI_BUS_P64H2_2_B, PCI_DEVFN(1, 0), {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}}, 23, 0}, // Slot 2A (J23) {PCI_BUS_P64H2_2_B, PCI_DEVFN(2, 0), {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}}, 24, 0}, // Slot 2B (J24) @@ -61,7 +61,7 @@ const struct irq_routing_table intel_irq_routing_table = { {PCI_BUS_P64H2_1_B, PCI_DEVFN(1, 0), {{PIRQ_A, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, // GB Ethernet {PCI_BUS_P64H2_1_B, PCI_DEVFN(2, 0), {{PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}}, 21, 0}, // Slot 1B (J21) // NOTE: Hotplug disabled on this bus - + // ICH-3 PCI bus {PCI_BUS_ICH3, PCI_DEVFN(0, 0), {{PIRQ_A, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, // Video {PCI_BUS_ICH3, PCI_DEVFN(2, 0), {{PIRQ_C, 0xdcf8}, {PIRQ_D, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_B, 0xdcf8}}, 11, 0}, // Debug slot (J11) diff --git a/src/mainboard/intel/xe7501devkit/mptable.c b/src/mainboard/intel/xe7501devkit/mptable.c index ee8299389d..2f48e83285 100644 --- a/src/mainboard/intel/xe7501devkit/mptable.c +++ b/src/mainboard/intel/xe7501devkit/mptable.c @@ -40,14 +40,14 @@ static void xe7501devkit_register_ioapics(struct mp_config_table *mc) smp_write_ioapic(mc, IOAPIC_ICH3, 0x20, 0xfec00000); // APIC ID, Version, Address // P64H2#2 Bus A IOAPIC - dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0)); + dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0)); if (!dev) BUG(); // Config.lb error? res = find_resource(dev, PCI_BASE_ADDRESS_0); smp_write_ioapic(mc, IOAPIC_P64H2_2_BUS_A, P64H2_IOAPIC_VERSION, res->base); // P64H2#2 Bus B IOAPIC - dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0)); + dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0)); if (!dev) BUG(); // Config.lb error? res = find_resource(dev, PCI_BASE_ADDRESS_0); @@ -55,14 +55,14 @@ static void xe7501devkit_register_ioapics(struct mp_config_table *mc) // P64H2#1 Bus A IOAPIC - dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(30, 0)); + dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(30, 0)); if (!dev) BUG(); // Config.lb error? res = find_resource(dev, PCI_BASE_ADDRESS_0); smp_write_ioapic(mc, IOAPIC_P64H2_1_BUS_A, P64H2_IOAPIC_VERSION, res->base); // P64H2#1 Bus B IOAPIC - dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(28, 0)); + dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(28, 0)); if (!dev) BUG(); // Config.lb error? res = find_resource(dev, PCI_BASE_ADDRESS_0); @@ -98,11 +98,11 @@ static void xe7501devkit_register_interrupts(struct mp_config_table *mc) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(4, INT_B), IOAPIC_P64H2_2_BUS_B, 13); // Slot 2D (J12) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(4, INT_C), IOAPIC_P64H2_2_BUS_B, 14); // Slot 2D (J12) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(4, INT_D), IOAPIC_P64H2_2_BUS_B, 15); // Slot 2D (J12) - + // P64H2#2 Bus A smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_A, PCI_IRQ(1, INT_A), IOAPIC_P64H2_2_BUS_A, 0); // SCSI smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_A, PCI_IRQ(1, INT_B), IOAPIC_P64H2_2_BUS_A, 1); // SCSI - + // P64H2#1 Bus B smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_B, PCI_IRQ(1, INT_A), IOAPIC_P64H2_1_BUS_B, 0); // GB Ethernet smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_B, PCI_IRQ(2, INT_A), IOAPIC_P64H2_1_BUS_B, 4); // Slot 1B (J21) @@ -117,13 +117,13 @@ static void xe7501devkit_register_interrupts(struct mp_config_table *mc) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_A, PCI_IRQ(1, INT_D), IOAPIC_P64H2_1_BUS_A, 3); // Slot 1A (J20) // ICH-3 - + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_ICH3, PCI_IRQ(0, INT_A), IOAPIC_ICH3, 16); // Video smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_ICH3, PCI_IRQ(2, INT_A), IOAPIC_ICH3, 18); // Debug slot (J11) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_ICH3, PCI_IRQ(2, INT_B), IOAPIC_ICH3, 19); // Debug slot (J11) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_ICH3, PCI_IRQ(2, INT_C), IOAPIC_ICH3, 16); // Debug slot (J11) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_ICH3, PCI_IRQ(2, INT_D), IOAPIC_ICH3, 17); // Debug slot (J11) - + // TODO: Not sure how to handle BT_INTR# signals from the P64H2s. Do we even need to, in APIC mode? // Super I/O (ISA interrupts) diff --git a/src/mainboard/intel/xe7501devkit/romstage.c b/src/mainboard/intel/xe7501devkit/romstage.c index 003a37f31c..99f00212c1 100644 --- a/src/mainboard/intel/xe7501devkit/romstage.c +++ b/src/mainboard/intel/xe7501devkit/romstage.c @@ -48,7 +48,7 @@ static void main(unsigned long bist) }, }; - if (bist == 0) + if (bist == 0) { // Skip this if there was a built in self test failure early_mtrr_init(); @@ -68,14 +68,14 @@ static void main(unsigned long bist) // If this is a warm boot, some initialization can be skipped - if (!bios_reset_detected()) + if (!bios_reset_detected()) { enable_smbus(); // dump_spd_registers(&memctrl[0]); // dump_smbus_registers(); sdram_initialize(ARRAY_SIZE(memctrl), memctrl); } - + // NOTE: ROMCC dies with an internal compiler error // if the following line is removed. print_debug("SDRAM is up.\n"); diff --git a/src/mainboard/iwill/Kconfig b/src/mainboard/iwill/Kconfig index cfb986f7eb..4a157954ab 100644 --- a/src/mainboard/iwill/Kconfig +++ b/src/mainboard/iwill/Kconfig @@ -1,7 +1,7 @@ choice prompt "Mainboard model" depends on VENDOR_IWILL - + source "src/mainboard/iwill/dk8_htx/Kconfig" source "src/mainboard/iwill/dk8s2/Kconfig" source "src/mainboard/iwill/dk8x/Kconfig" diff --git a/src/mainboard/iwill/dk8_htx/acpi/amd8111.asl b/src/mainboard/iwill/dk8_htx/acpi/amd8111.asl index 19011dc47b..38aaea1525 100644 --- a/src/mainboard/iwill/dk8_htx/acpi/amd8111.asl +++ b/src/mainboard/iwill/dk8_htx/acpi/amd8111.asl @@ -4,17 +4,17 @@ //AMD8111 Name (APIC, Package (0x04) { - Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10},// 0x0004ffff : assusme 8131 is present - Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11}, - Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12}, + Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10},// 0x0004ffff : assusme 8131 is present + Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11}, + Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12}, Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13} }) Name (PICM, Package (0x04) { - Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00}, - Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00}, - Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00}, + Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00}, + Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00}, + Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00}, Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00} }) @@ -34,16 +34,16 @@ Store(Local0, Index (DeRefOf (Index (APIC, 1)), 0)) Store(Local0, Index (DeRefOf (Index (APIC, 2)), 0)) Store(Local0, Index (DeRefOf (Index (APIC, 3)), 0)) - + Store (0x00, ^DNCG) - + } - If (LNot (PICF)) { - Return (PICM) + If (LNot (PICF)) { + Return (PICM) } Else { - Return (APIC) + Return (APIC) } } @@ -57,7 +57,7 @@ OperationRegion (PIRQ, PCI_Config, 0x56, 0x02) Field (PIRQ, ByteAcc, Lock, Preserve) { - PIBA, 8, + PIBA, 8, PIDC, 8 } /* @@ -144,7 +144,7 @@ Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x13 }, Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x10 } }) - + Name (PICM, Package (0x0C) { Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //USB diff --git a/src/mainboard/iwill/dk8_htx/acpi/amd8111_isa.asl b/src/mainboard/iwill/dk8_htx/acpi/amd8111_isa.asl index 9d93e34e92..9e952c80bd 100644 --- a/src/mainboard/iwill/dk8_htx/acpi/amd8111_isa.asl +++ b/src/mainboard/iwill/dk8_htx/acpi/amd8111_isa.asl @@ -5,7 +5,7 @@ Device (ISA) { - /* lpc 0x00040000 */ + /* lpc 0x00040000 */ Method (_ADR, 0, NotSerialized) { Return (DADD(\_SB.PCI0.SBDN, 0x00010000)) @@ -15,11 +15,11 @@ Field (PIRY, ByteAcc, NoLock, Preserve) { Z000, 2, // Parallel Port Range - , 1, + , 1, ECP, 1, // ECP Enable FDC1, 1, // Floppy Drive Controller 1 FDC2, 1, // Floppy Drive Controller 2 - Offset (0x01), + Offset (0x01), Z001, 3, // Serial Port A Range SAEN, 1, // Serial Post A Enabled Z002, 3, // Serial Port B Range @@ -106,7 +106,7 @@ IO (Decode16, 0x0090, 0x0090, 0x01, 0x10) IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E) IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10) - IO (Decode16, 0x0B78, 0x0B78, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error + IO (Decode16, 0x0B78, 0x0B78, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error IO (Decode16, 0x0190, 0x0190, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error }) Method (_CRS, 0, NotSerialized) @@ -134,7 +134,7 @@ Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS }) - // Read the Video Memory length + // Read the Video Memory length CreateDWordField (BUF0, 0x14, CLEN) CreateDWordField (BUF0, 0x10, CBAS) diff --git a/src/mainboard/iwill/dk8_htx/acpi/amd8131.asl b/src/mainboard/iwill/dk8_htx/acpi/amd8131.asl index fbc0b30e42..dd82e38df5 100644 --- a/src/mainboard/iwill/dk8_htx/acpi/amd8131.asl +++ b/src/mainboard/iwill/dk8_htx/acpi/amd8131.asl @@ -1,7 +1,7 @@ /* * Copyright 2005 AMD */ - + Device (PG0A) { /* 8132 pcix bridge*/ @@ -19,60 +19,60 @@ Name (APIC, Package (0x14) { // Slot 3 - PIRQ BCDA ---- verified - Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x19 }, //Slot 3 - Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1A }, - Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x1B }, + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x19 }, //Slot 3 + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1A }, + Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x1B }, Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x18 }, - + //Slot 4 - PIRQ CDAB ---- verified Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1A }, //? - Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B }, - Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x18 }, - Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x19 }, + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B }, + Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x18 }, + Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x19 }, //Onboard NIC 1 - PIRQ DABC Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1B }, //? - Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x18 }, - Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x19 }, - Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x1A }, + Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x18 }, + Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x19 }, + Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x1A }, // NIC 2 - PIRQ ABCD -- verified Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x18 }, //? - Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x19 }, - Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x1A }, - Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x1B }, + Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x19 }, + Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x1A }, + Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x1B }, //SERIAL ATA - PIRQ BCDA Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x19 }, //? - Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x1A }, - Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x1B }, + Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x1A }, + Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x1B }, Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x18 } }) Name (PICM, Package (0x14) { - Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 3 - Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 3 + Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0002FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 } }) Method (_PRT, 0, NotSerialized) @@ -100,15 +100,15 @@ { // Slot A - PIRQ CDAB -- verfied Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1E },// Slot 2 - Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1F }, - Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1C }, + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1F }, + Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1C }, Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1D } }) Name (PICM, Package (0x04) { - Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },//Slot 2 - Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },//Slot 2 + Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 }, Package (0x04) { 0x0002FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 } }) Method (_PRT, 0, NotSerialized) diff --git a/src/mainboard/iwill/dk8_htx/acpi/amd8131_2.asl b/src/mainboard/iwill/dk8_htx/acpi/amd8131_2.asl index 163c0f6061..8b8bc9fab9 100644 --- a/src/mainboard/iwill/dk8_htx/acpi/amd8131_2.asl +++ b/src/mainboard/iwill/dk8_htx/acpi/amd8131_2.asl @@ -1,7 +1,7 @@ /* * Copyright 2005 AMD */ - + Device (PG0A) { /* 8132 pcix bridge*/ @@ -19,18 +19,18 @@ Name (APIC, Package (0x04) { // Slot A - PIRQ BCDA - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2 - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A }, + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2 + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A }, Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x001B }, - + }) Name (PICM, Package (0x04) { - Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2 - Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2 + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, }) Name (DNCG, Ones) @@ -40,7 +40,7 @@ If (LEqual (^DNCG, Ones)) { Multiply (HCIN, 0x0008, Local2) // GSI for 8132 is 4 so we get 8 Store (0x00, Local1) - While (LLess (Local1, 0x04)) + While (LLess (Local1, 0x04)) { // Update the GSI according to HCIN Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0) @@ -76,15 +76,15 @@ { // Slot A - PIRQ ABCD Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x001F },// Slot 1 - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 }, + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 }, Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x0022 } }) Name (PICM, Package (0x04) { - Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1 - Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1 + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 } }) diff --git a/src/mainboard/iwill/dk8_htx/acpi/amd8132_2.asl b/src/mainboard/iwill/dk8_htx/acpi/amd8132_2.asl index 75ef72343a..e5cfe3c951 100644 --- a/src/mainboard/iwill/dk8_htx/acpi/amd8132_2.asl +++ b/src/mainboard/iwill/dk8_htx/acpi/amd8132_2.asl @@ -1,7 +1,7 @@ /* * Copyright 2005 AMD */ - + Device (PG0A) { /* 8132 pcix bridge*/ @@ -19,18 +19,18 @@ Name (APIC, Package (0x04) { // Slot A - PIRQ BCDA - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2 - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A }, + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2 + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A }, Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x001B }, - + }) Name (PICM, Package (0x04) { - Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2 - Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2 + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, }) Name (DNCG, Ones) @@ -40,7 +40,7 @@ If (LEqual (^DNCG, Ones)) { Multiply (HCIN, 0x000e, Local2) // GSI for 8132 is 7 so we get 14 Store (0x00, Local1) - While (LLess (Local1, 0x04)) + While (LLess (Local1, 0x04)) { // Update the GSI according to HCIN Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0) @@ -76,15 +76,15 @@ { // Slot A - PIRQ ABCD Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x001F },// Slot 1 - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 }, + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 }, Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x0022 } }) Name (PICM, Package (0x04) { - Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1 - Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1 + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 } }) diff --git a/src/mainboard/iwill/dk8_htx/acpi/amd8151.asl b/src/mainboard/iwill/dk8_htx/acpi/amd8151.asl index 001d45b0fe..ce85502296 100644 --- a/src/mainboard/iwill/dk8_htx/acpi/amd8151.asl +++ b/src/mainboard/iwill/dk8_htx/acpi/amd8151.asl @@ -1,4 +1,4 @@ -// AMD8151 +// AMD8151 Device (AGPB) { Method (_ADR, 0, NotSerialized) @@ -8,16 +8,16 @@ Name (APIC, Package (0x04) { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 }, Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 } }) Name (PICM, Package (0x04) { - Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 } }) Method (_PRT, 0, NotSerialized) diff --git a/src/mainboard/iwill/dk8_htx/acpi/htx_no_ioapic.asl b/src/mainboard/iwill/dk8_htx/acpi/htx_no_ioapic.asl index 95a4860c63..1035a7edfd 100644 --- a/src/mainboard/iwill/dk8_htx/acpi/htx_no_ioapic.asl +++ b/src/mainboard/iwill/dk8_htx/acpi/htx_no_ioapic.asl @@ -1,7 +1,7 @@ /* * Copyright 2006 AMD */ - + Device (HTXA) { /* HTX */ diff --git a/src/mainboard/iwill/dk8_htx/acpi_tables.c b/src/mainboard/iwill/dk8_htx/acpi_tables.c index 05664e31a5..9113c5acc9 100644 --- a/src/mainboard/iwill/dk8_htx/acpi_tables.c +++ b/src/mainboard/iwill/dk8_htx/acpi_tables.c @@ -25,7 +25,7 @@ #if DUMP_ACPI_TABLES == 1 static void dump_mem(unsigned start, unsigned end) { - + unsigned i; print_debug("dump_mem:"); for(i=start;i<end;i++) { @@ -63,10 +63,10 @@ unsigned long acpi_fill_madt(unsigned long current) struct mb_sysconf_t *m; m = sysconf.mb; - + /* create all subtables for processors */ current = acpi_create_madt_lapics(current); - + /* Write 8111 IOAPIC */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8111, IO_APIC_ADDR, 0); @@ -102,7 +102,7 @@ unsigned long acpi_fill_madt(unsigned long current) unsigned d = 0; if(!(sysconf.pci1234[i] & 0x1) ) continue; // 8131 need to use +4 - + switch (sysconf.hcid[i]) { case 1: d = 7; @@ -145,7 +145,7 @@ unsigned long acpi_fill_madt(unsigned long current) current, 0, 0, 2, 5 ); /* 0: mean bus 0--->ISA */ /* 0: PIC 0 */ - /* 2: APIC 2 */ + /* 2: APIC 2 */ /* 5 mean: 0101 --> Edige-triggered, Active high*/ @@ -185,7 +185,7 @@ unsigned long write_acpi_tables(unsigned long start) /* Align ACPI tables to 16byte */ start = ( start + 0x0f ) & -0x10; current = start; - + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); /* We need at least an RSDP and an RSDT Table */ @@ -196,7 +196,7 @@ unsigned long write_acpi_tables(unsigned long start) /* clear all table memory */ memset((void *)start, 0, current - start); - + acpi_write_rsdp(rsdp, rsdt, NULL); acpi_write_rsdt(rsdt); diff --git a/src/mainboard/iwill/dk8_htx/devicetree.cb b/src/mainboard/iwill/dk8_htx/devicetree.cb index cfddca953d..734a93fe0a 100644 --- a/src/mainboard/iwill/dk8_htx/devicetree.cb +++ b/src/mainboard/iwill/dk8_htx/devicetree.cb @@ -8,7 +8,7 @@ chip northbridge/amd/amdk8/root_complex chip northbridge/amd/amdk8 device pci 18.0 on end device pci 18.0 on end - device pci 18.0 on # northbridge + device pci 18.0 on # northbridge chip southbridge/amd/amd8131 # the on/off keyword is mandatory device pci 0.0 on end @@ -57,7 +57,7 @@ chip northbridge/amd/amdk8/root_complex io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 - end + end device pnp 2e.8 on # GPIO2 io 0x07 = 0x08ff io 0x30 = 0x01ff diff --git a/src/mainboard/iwill/dk8_htx/dsdt.asl b/src/mainboard/iwill/dk8_htx/dsdt.asl index ee87023ff8..a549d70297 100644 --- a/src/mainboard/iwill/dk8_htx/dsdt.asl +++ b/src/mainboard/iwill/dk8_htx/dsdt.asl @@ -100,11 +100,11 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-K8", "AMDACPI", 100925440) Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) - Return (Local3) + Return (Local3) } #include "acpi/pci0_hc.asl" - + } Device (PCI1) { @@ -138,7 +138,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-K8", "AMDACPI", 100925440) Notify (\_SB.PCI0.PG0B, 0x02) } - Method (_L29, 0, NotSerialized) // GPIO25 (Suspend) - Pogo 0 Bridge A + Method (_L29, 0, NotSerialized) // GPIO25 (Suspend) - Pogo 0 Bridge A { Notify (\_SB.PCI0.PG0A, 0x02) } @@ -183,14 +183,14 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-K8", "AMDACPI", 100925440) OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100) Field (GRAM, ByteAcc, Lock, Preserve) { - Offset (0x10), + Offset (0x10), FLG0, 8 } OperationRegion (GSTS, SystemIO, 0xC028, 0x02) Field (GSTS, ByteAcc, NoLock, Preserve) { - , 4, + , 4, IRQR, 1 } diff --git a/src/mainboard/iwill/dk8_htx/fadt.c b/src/mainboard/iwill/dk8_htx/fadt.c index d4c6622847..6b6107070b 100644 --- a/src/mainboard/iwill/dk8_htx/fadt.c +++ b/src/mainboard/iwill/dk8_htx/fadt.c @@ -30,7 +30,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ // 3=Workstation,4=Enterprise Server, 7=Performance Server fadt->preferred_pm_profile=0x03; fadt->sci_int=9; - // disable system management mode by setting to 0: + // disable system management mode by setting to 0: fadt->smi_cmd = 0;//pm_base+0x2f; fadt->acpi_enable = 0xf0; fadt->acpi_disable = 0xf1; @@ -53,7 +53,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->gpe0_blk_len = 4; fadt->gpe1_blk_len = 8; fadt->gpe1_base = 16; - + fadt->cst_cnt = 0xe3; fadt->p_lvl2_lat = 101; fadt->p_lvl3_lat = 1001; @@ -66,7 +66,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->century = 0; // 0x7f to make rtc alrm work fadt->iapc_boot_arch = 0x3; // See table 5-11 fadt->flags = 0x25; - + fadt->res2 = 0; fadt->reset_reg.space_id = 1; diff --git a/src/mainboard/iwill/dk8_htx/get_bus_conf.c b/src/mainboard/iwill/dk8_htx/get_bus_conf.c index d6141158ac..30b9e368ab 100644 --- a/src/mainboard/iwill/dk8_htx/get_bus_conf.c +++ b/src/mainboard/iwill/dk8_htx/get_bus_conf.c @@ -15,10 +15,10 @@ // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables struct mb_sysconf_t mb_sysconf; -static unsigned pci1234x[] = +static unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - 0x0000ff0, // SB chain m + 0x0000ff0, // SB chain m 0x0000000, // HTX 0x0000100, // co processor on socket 1 // 0x0000ff0, @@ -27,7 +27,7 @@ static unsigned pci1234x[] = // 0x0000ff0, // 0x0000ff0 }; -static unsigned hcdnx[] = +static unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, 0x20202020, @@ -88,17 +88,17 @@ void get_bus_conf(void) get_bus_conf_done = 1; sysconf.mb = &mb_sysconf; - + m = sysconf.mb; - sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for(i=0;i<sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; } - + get_sblk_pci1234(); - + sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff; m->sbdn3 = sysconf.hcdn[0] & 0xff; @@ -209,8 +209,8 @@ void get_bus_conf(void) /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS==1 apicid_base = get_apicid_base(3); -#else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; +#else + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif m->apicid_8111 = apicid_base+0; m->apicid_8132_1 = apicid_base+1; diff --git a/src/mainboard/iwill/dk8_htx/irq_tables.c b/src/mainboard/iwill/dk8_htx/irq_tables.c index d872b0a0db..637f980055 100644 --- a/src/mainboard/iwill/dk8_htx/irq_tables.c +++ b/src/mainboard/iwill/dk8_htx/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up @@ -13,11 +13,11 @@ #include "mb_sysconf.h" -static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, +static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; + pirq_info->bus = bus; pirq_info->devfn = devfn; pirq_info->irq[0].link = link0; @@ -50,7 +50,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) struct mb_sysconf_t *m; get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c - + m = sysconf.mb; /* Align the table to be 16 byte aligned. */ @@ -62,25 +62,25 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq = (void *)(addr); v = (uint8_t *)(addr); - + pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - + pirq->rtr_bus = m->bus_8111_0; pirq->rtr_devfn = ((sysconf.sbdn+1)<<3)|0; pirq->exclusive_irqs = 0; - + pirq->rtr_vendor = 0x1022; pirq->rtr_device = 0x746b; pirq->miniport_data = 0; memset(pirq->rfu, 0, sizeof(pirq->rfu)); - + pirq_info = (void *) ( &pirq->checksum + 1); slot_num = 0; - + { device_t dev; dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn+1,3)); @@ -126,11 +126,11 @@ unsigned long write_pirq_routing_table(unsigned long addr) j++; } - - pirq->size = 32 + 16 * slot_num; + + pirq->size = 32 + 16 * slot_num; for (i = 0; i < pirq->size; i++) - sum += v[i]; + sum += v[i]; sum = pirq->checksum - sum; diff --git a/src/mainboard/iwill/dk8_htx/mptable.c b/src/mainboard/iwill/dk8_htx/mptable.c index 1b0cea02ab..061f3d8ece 100644 --- a/src/mainboard/iwill/dk8_htx/mptable.c +++ b/src/mainboard/iwill/dk8_htx/mptable.c @@ -101,8 +101,8 @@ static void *smp_write_config_table(void *v) } } - -/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + +/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_8111, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x1, m->apicid_8111, 0x1); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_8111, 0x2); @@ -149,14 +149,14 @@ static void *smp_write_config_table(void *v) //Slot 4 PCI-X 133/100/66 for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (2<<2)|i, m->apicid_8132_1, (2+i)%4); //26 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (2<<2)|i, m->apicid_8132_1, (2+i)%4); //26 } //Onboard NICS smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (3<<2)|0, m->apicid_8132_1, 3); //27 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (4<<2)|0, m->apicid_8132_1, 0); //24 -//Onboard SATA +//Onboard SATA smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (5<<2)|0, m->apicid_8132_1, 1); //25 j = 0; diff --git a/src/mainboard/iwill/dk8_htx/resourcemap.c b/src/mainboard/iwill/dk8_htx/resourcemap.c index 992510215c..d60c379669 100644 --- a/src/mainboard/iwill/dk8_htx/resourcemap.c +++ b/src/mainboard/iwill/dk8_htx/resourcemap.c @@ -143,7 +143,7 @@ static void setup_mb_resource_map(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, @@ -199,7 +199,7 @@ static void setup_mb_resource_map(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -207,7 +207,7 @@ static void setup_mb_resource_map(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003, @@ -252,7 +252,7 @@ static void setup_mb_resource_map(void) * This field defines the highest bus number in configuration regin i */ PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x06000203, // AMD 8111 on link0 of CPU 0 - PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, }; diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c index bddc5be7b0..af4c7b021c 100644 --- a/src/mainboard/iwill/dk8_htx/romstage.c +++ b/src/mainboard/iwill/dk8_htx/romstage.c @@ -1,7 +1,7 @@ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 -#define SET_NB_CFG_54 1 +#define SET_NB_CFG_54 1 //used by raminit #define QRANK_DIMM_SUPPORT 1 @@ -97,7 +97,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/ramtest.c" /* tyan does not want the default */ -#include "resourcemap.c" +#include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" @@ -165,21 +165,21 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); #if CONFIG_MEM_TRAIN_SEQ == 1 - set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram + set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS==1 // It is said that we should start core1 after all core0 launched - /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, + /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, - * (there may be apic id conflicts in that case) + * (there may be apic id conflicts in that case) */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif - + /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn @@ -202,7 +202,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); + print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } #endif diff --git a/src/mainboard/iwill/dk8_htx/ssdt2.asl b/src/mainboard/iwill/dk8_htx/ssdt2.asl index 582ef97621..791454c190 100644 --- a/src/mainboard/iwill/dk8_htx/ssdt2.asl +++ b/src/mainboard/iwill/dk8_htx/ssdt2.asl @@ -28,16 +28,16 @@ DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) // BUS ? Second HT Chain Name (HCIN, 0xcc) // HC2 0x01 - + Name (_UID, 0xdd) // HC 0x03 - Name (_HID, "PNP0A03") + Name (_HID, "PNP0A03") Method (_ADR, 0, NotSerialized) //Fake bus should be 0 { Return (DADD(GHCN(HCIN), 0x00000000)) } - + Method (_BBN, 0, NotSerialized) { Return (GBUS (GHCN(HCIN), GHCL(HCIN))) @@ -45,7 +45,7 @@ DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) Method (_STA, 0, NotSerialized) { - Return (\_SB.GHCE(HCIN)) + Return (\_SB.GHCE(HCIN)) } Method (_CRS, 0, NotSerialized) diff --git a/src/mainboard/iwill/dk8_htx/ssdt3.asl b/src/mainboard/iwill/dk8_htx/ssdt3.asl index 583e945740..28fe5f45a3 100644 --- a/src/mainboard/iwill/dk8_htx/ssdt3.asl +++ b/src/mainboard/iwill/dk8_htx/ssdt3.asl @@ -28,16 +28,16 @@ DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) // BUS ? Second HT Chain Name (HCIN, 0xcc) // HC2 0x01 - + Name (_UID, 0xdd) // HC 0x03 - Name (_HID, "PNP0A03") + Name (_HID, "PNP0A03") Method (_ADR, 0, NotSerialized) //Fake bus should be 0 { Return (DADD(GHCN(HCIN), 0x00000000)) } - + Method (_BBN, 0, NotSerialized) { Return (GBUS (GHCN(HCIN), GHCL(HCIN))) @@ -45,7 +45,7 @@ DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) Method (_STA, 0, NotSerialized) { - Return (\_SB.GHCE(HCIN)) + Return (\_SB.GHCE(HCIN)) } Method (_CRS, 0, NotSerialized) diff --git a/src/mainboard/iwill/dk8_htx/ssdt4.asl b/src/mainboard/iwill/dk8_htx/ssdt4.asl index fd7224d17a..93abb7f520 100644 --- a/src/mainboard/iwill/dk8_htx/ssdt4.asl +++ b/src/mainboard/iwill/dk8_htx/ssdt4.asl @@ -28,16 +28,16 @@ DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) // BUS ? Second HT Chain Name (HCIN, 0xcc) // HC2 0x01 - + Name (_UID, 0xdd) // HC 0x03 - Name (_HID, "PNP0A03") + Name (_HID, "PNP0A03") Method (_ADR, 0, NotSerialized) //Fake bus should be 0 { Return (DADD(GHCN(HCIN), 0x00000000)) } - + Method (_BBN, 0, NotSerialized) { Return (GBUS (GHCN(HCIN), GHCL(HCIN))) @@ -45,7 +45,7 @@ DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) Method (_STA, 0, NotSerialized) { - Return (\_SB.GHCE(HCIN)) + Return (\_SB.GHCE(HCIN)) } Method (_CRS, 0, NotSerialized) diff --git a/src/mainboard/iwill/dk8_htx/ssdt5.asl b/src/mainboard/iwill/dk8_htx/ssdt5.asl index 7592301902..5910e0fac2 100644 --- a/src/mainboard/iwill/dk8_htx/ssdt5.asl +++ b/src/mainboard/iwill/dk8_htx/ssdt5.asl @@ -28,16 +28,16 @@ DefinitionBlock ("SSDT5.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) // BUS ? Second HT Chain Name (HCIN, 0xcc) // HC2 0x01 - + Name (_UID, 0xdd) // HC 0x03 - Name (_HID, "PNP0A03") + Name (_HID, "PNP0A03") Method (_ADR, 0, NotSerialized) //Fake bus should be 0 { Return (DADD(GHCN(HCIN), 0x00000000)) } - + Method (_BBN, 0, NotSerialized) { Return (GBUS (GHCN(HCIN), GHCL(HCIN))) @@ -45,7 +45,7 @@ DefinitionBlock ("SSDT5.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) Method (_STA, 0, NotSerialized) { - Return (\_SB.GHCE(HCIN)) + Return (\_SB.GHCE(HCIN)) } Method (_CRS, 0, NotSerialized) diff --git a/src/mainboard/iwill/dk8s2/irq_tables.c b/src/mainboard/iwill/dk8s2/irq_tables.c index 75f1790abd..c3928f06ff 100644 --- a/src/mainboard/iwill/dk8s2/irq_tables.c +++ b/src/mainboard/iwill/dk8s2/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up * diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c index 8dc9dc0049..9a2fede061 100644 --- a/src/mainboard/iwill/dk8s2/romstage.c +++ b/src/mainboard/iwill/dk8s2/romstage.c @@ -1,7 +1,7 @@ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 -#define SET_NB_CFG_54 1 +#define SET_NB_CFG_54 1 //used by raminit #define QRANK_DIMM_SUPPORT 1 @@ -165,21 +165,21 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); #if CONFIG_MEM_TRAIN_SEQ == 1 - set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram + set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS==1 // It is said that we should start core1 after all core0 launched - /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, + /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, - * (there may be apic id conflicts in that case) + * (there may be apic id conflicts in that case) */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif - + /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn @@ -202,7 +202,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); + print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } #endif diff --git a/src/mainboard/iwill/dk8x/devicetree.cb b/src/mainboard/iwill/dk8x/devicetree.cb index 77c96aa944..a275425751 100644 --- a/src/mainboard/iwill/dk8x/devicetree.cb +++ b/src/mainboard/iwill/dk8x/devicetree.cb @@ -1,8 +1,8 @@ chip northbridge/amd/amdk8/root_complex device pci_domain 0 on chip northbridge/amd/amdk8 - device pci 18.0 on # northbridge - # devices on link 0, link 0 == LDT 0 + device pci 18.0 on # northbridge + # devices on link 0, link 0 == LDT 0 chip southbridge/amd/amd8131 # the on/off keyword is mandatory device pci 0.0 on end @@ -28,15 +28,15 @@ chip northbridge/amd/amdk8/root_complex device pnp 2e.4 on end device pnp 2e.5 on end device pnp 2e.6 on end - device pnp 2e.7 on end - device pnp 2e.8 on end - device pnp 2e.9 on end - device pnp 2e.a on end + device pnp 2e.7 on end + device pnp 2e.8 on end + device pnp 2e.9 on end + device pnp 2e.a on end end end device pci 1.1 on end device pci 1.2 on end - device pci 1.3 on end + device pci 1.3 on end device pci 1.5 off end device pci 1.6 off end end @@ -55,7 +55,7 @@ chip northbridge/amd/amdk8/root_complex device pci 19.2 on end device pci 19.3 on end end - end + end device apic_cluster 0 on chip cpu/amd/socket_940 device apic 0 on end diff --git a/src/mainboard/iwill/dk8x/irq_tables.c b/src/mainboard/iwill/dk8x/irq_tables.c index 1f35cbaef2..06b9cfb6b5 100644 --- a/src/mainboard/iwill/dk8x/irq_tables.c +++ b/src/mainboard/iwill/dk8x/irq_tables.c @@ -12,13 +12,13 @@ {linkc, AVAILABLE_IRQS}, {linkd, AVAILABLE_IRQS}}, slot, 0} /* Each IRQ_SLOT entry consists of: - * bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu + * bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ - 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT + 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT * devices on the bus */ IRQ_ROUTER_BUS, /* Where the interrupt router lies (bus) */ IRQ_ROUTER_DEVFN, /* Where the interrupt router lies (dev) */ @@ -28,7 +28,7 @@ const struct irq_routing_table intel_irq_routing_table = { 0x00, /* Crap (miniport) */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ 0x00, /* u8 checksum , mod 256 checksum must give - * zero, will be corrected later + * zero, will be corrected later */ { diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c index 8dc9dc0049..9a2fede061 100644 --- a/src/mainboard/iwill/dk8x/romstage.c +++ b/src/mainboard/iwill/dk8x/romstage.c @@ -1,7 +1,7 @@ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 -#define SET_NB_CFG_54 1 +#define SET_NB_CFG_54 1 //used by raminit #define QRANK_DIMM_SUPPORT 1 @@ -165,21 +165,21 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); #if CONFIG_MEM_TRAIN_SEQ == 1 - set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram + set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS==1 // It is said that we should start core1 after all core0 launched - /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, + /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, - * (there may be apic id conflicts in that case) + * (there may be apic id conflicts in that case) */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif - + /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn @@ -202,7 +202,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); + print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } #endif diff --git a/src/mainboard/kontron/986lcd-m/acpi/i945_pci_irqs.asl b/src/mainboard/kontron/986lcd-m/acpi/i945_pci_irqs.asl index a6043867b9..e466658dd4 100644 --- a/src/mainboard/kontron/986lcd-m/acpi/i945_pci_irqs.asl +++ b/src/mainboard/kontron/986lcd-m/acpi/i945_pci_irqs.asl @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* This is board specific information: IRQ routing for the +/* This is board specific information: IRQ routing for the * i945 */ diff --git a/src/mainboard/kontron/986lcd-m/acpi/ich7_pci_irqs.asl b/src/mainboard/kontron/986lcd-m/acpi/ich7_pci_irqs.asl index e86df0f973..c108d3f5b2 100644 --- a/src/mainboard/kontron/986lcd-m/acpi/ich7_pci_irqs.asl +++ b/src/mainboard/kontron/986lcd-m/acpi/ich7_pci_irqs.asl @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* This is board specific information: IRQ routing for the +/* This is board specific information: IRQ routing for the * 0:1e.0 PCI bridge of the ICH7 */ diff --git a/src/mainboard/kontron/986lcd-m/acpi/platform.asl b/src/mainboard/kontron/986lcd-m/acpi/platform.asl index 39faa5d729..2e4223c19c 100644 --- a/src/mainboard/kontron/986lcd-m/acpi/platform.asl +++ b/src/mainboard/kontron/986lcd-m/acpi/platform.asl @@ -42,9 +42,9 @@ Method(TRAP, 1, Serialized) Return (SMIF) // Return value of SMI handler } -/* The _PIC method is called by the OS to choose between interrupt +/* The _PIC method is called by the OS to choose between interrupt * routing via the i8259 interrupt controller or the APIC. - * + * * _PIC is called with a parameter of 0 for i8259 configuration and * with a parameter of 1 for Local Apic/IOAPIC configuration. */ @@ -74,12 +74,12 @@ Method(_WAK,1) // Notify PCI Express slots in case a card // was inserted while a sleep state was active. - // Are we going to S3? + // Are we going to S3? If (LEqual(Arg0, 3)) { // .. } - // Are we going to S4? + // Are we going to S4? If (LEqual(Arg0, 4)) { // .. } diff --git a/src/mainboard/kontron/986lcd-m/acpi/thermal.asl b/src/mainboard/kontron/986lcd-m/acpi/thermal.asl index ad653bc5fc..d1774d4756 100644 --- a/src/mainboard/kontron/986lcd-m/acpi/thermal.asl +++ b/src/mainboard/kontron/986lcd-m/acpi/thermal.asl @@ -25,7 +25,7 @@ Scope (\_TZ) { // FIXME these could/should be read from the - // GNVS area, so they can be controlled by + // GNVS area, so they can be controlled by // coreboot Name(TC1V, 0x04) Name(TC2V, 0x03) diff --git a/src/mainboard/kontron/986lcd-m/acpi_tables.c b/src/mainboard/kontron/986lcd-m/acpi_tables.c index 55f02b10c2..6adff9f56b 100644 --- a/src/mainboard/kontron/986lcd-m/acpi_tables.c +++ b/src/mainboard/kontron/986lcd-m/acpi_tables.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify diff --git a/src/mainboard/kontron/986lcd-m/chip.h b/src/mainboard/kontron/986lcd-m/chip.h index 9d7e5968e1..800384aca4 100644 --- a/src/mainboard/kontron/986lcd-m/chip.h +++ b/src/mainboard/kontron/986lcd-m/chip.h @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2007-2008 coresystems GmbH * * This program is free software; you can redistribute it and/or modify diff --git a/src/mainboard/kontron/986lcd-m/cmos.layout b/src/mainboard/kontron/986lcd-m/cmos.layout index 18867e514d..2217cb365a 100644 --- a/src/mainboard/kontron/986lcd-m/cmos.layout +++ b/src/mainboard/kontron/986lcd-m/cmos.layout @@ -102,7 +102,7 @@ entries 968 1 e 2 ethernet1 969 1 e 2 ethernet2 970 1 e 2 ethernet3 - + #971 13 r 0 unused # coreboot config options: check sums diff --git a/src/mainboard/kontron/986lcd-m/devicetree.cb b/src/mainboard/kontron/986lcd-m/devicetree.cb index f1f771ad72..f4e6b9318a 100644 --- a/src/mainboard/kontron/986lcd-m/devicetree.cb +++ b/src/mainboard/kontron/986lcd-m/devicetree.cb @@ -6,7 +6,7 @@ chip northbridge/intel/i945 end end - device pci_domain 0 on + device pci_domain 0 on device pci 00.0 on end # host bridge device pci 01.0 off end # i945 PCIe root port device pci 02.0 on end # vga controller @@ -46,7 +46,7 @@ chip northbridge/intel/i945 device pci 1d.3 on end # USB UHCI device pci 1d.7 on end # USB2 EHCI device pci 1e.0 on end # PCI bridge - #device pci 1e.2 off end # AC'97 Audio + #device pci 1e.2 off end # AC'97 Audio #device pci 1e.3 off end # AC'97 Modem device pci 1f.0 on # LPC bridge chip superio/winbond/w83627thg diff --git a/src/mainboard/kontron/986lcd-m/dsdt.asl b/src/mainboard/kontron/986lcd-m/dsdt.asl index 653cd5b266..f06b225fe0 100644 --- a/src/mainboard/kontron/986lcd-m/dsdt.asl +++ b/src/mainboard/kontron/986lcd-m/dsdt.asl @@ -34,7 +34,7 @@ DefinitionBlock( // General Purpose Events //#include "acpi/gpe.asl" - + //#include "acpi/thermal.asl" Scope (\_SB) { diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c index c7f2ee00e4..28d6de18e1 100644 --- a/src/mainboard/kontron/986lcd-m/mainboard.c +++ b/src/mainboard/kontron/986lcd-m/mainboard.c @@ -104,7 +104,7 @@ struct fan_speed { u16 fan_speed; }; -// FANIN Target Speed Register +// FANIN Target Speed Register // FANIN = 337500 / RPM struct fan_speed fan_speeds[] = { { 0x3c, 5625 }, { 0x41, 5192 }, { 0x47, 4753 }, { 0x4e, 4326 }, @@ -119,7 +119,7 @@ struct temperature { }; struct temperature temperatures[] = { - { 30, 86 }, { 33, 91 }, { 36, 96 }, { 39, 102 }, + { 30, 86 }, { 33, 91 }, { 36, 96 }, { 39, 102 }, { 42, 107 }, { 45, 113 }, { 48, 118 }, { 51, 123 }, { 54, 129 }, { 57, 134 }, { 60, 140 }, { 63, 145 }, { 66, 150 }, { 69, 156 }, { 72, 161 }, { 75, 167 } @@ -144,7 +144,7 @@ static void hwm_setup(void) sysfan_speed = FAN_SPEED_5625; //if (get_option(&sysfan_temperature, "sysfan_temperature") < 0) // sysfan_temperature = FAN_TEMPERATURE_30DEGC; - + // hwm_write(0x31, 0x20); // AVCC high limit // hwm_write(0x34, 0x06); // VIN2 low limit @@ -223,10 +223,10 @@ static void verb_setup(void) cim_verb_data_size = 0; } -// mainboard_enable is executed as first thing after +// mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(device_t dev) { #if CONFIG_PCI_OPTION_ROM_RUN_YABEL /* Install custom int15 handler for VGA OPROM */ diff --git a/src/mainboard/kontron/986lcd-m/mainboard_smi.c b/src/mainboard/kontron/986lcd-m/mainboard_smi.c index 6e4b5ad8d1..1aac802f2e 100644 --- a/src/mainboard/kontron/986lcd-m/mainboard_smi.c +++ b/src/mainboard/kontron/986lcd-m/mainboard_smi.c @@ -23,7 +23,7 @@ #include <cpu/x86/smm.h> #include "../../../southbridge/intel/i82801gx/i82801gx_nvs.h" -/* The southbridge SMI handler checks whether gnvs has a +/* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler */ extern global_nvs_t *gnvs; diff --git a/src/mainboard/kontron/986lcd-m/mptable.c b/src/mainboard/kontron/986lcd-m/mptable.c index dbf36bd51c..28c506f132 100644 --- a/src/mainboard/kontron/986lcd-m/mptable.c +++ b/src/mainboard/kontron/986lcd-m/mptable.c @@ -90,7 +90,7 @@ static void *smp_write_config_table(void *v) /* Legacy Interrupts */ - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, ioapic_id, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x1, ioapic_id, 0x1); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, ioapic_id, 0x2); @@ -158,11 +158,11 @@ static void *smp_write_config_table(void *v) return smp_next_mpe_entry(mc); } -/* MP table generation in coreboot is not very well designed; - * One of the issues is that it knows nothing about Virtual +/* MP table generation in coreboot is not very well designed; + * One of the issues is that it knows nothing about Virtual * Wire mode, which everyone uses since a decade or so. This * function fixes up our floating table. This spares us doing - * a half-baked fix of adding a new parameter to 200+ calls + * a half-baked fix of adding a new parameter to 200+ calls * to smp_write_floating_table() */ static void fixup_virtual_wire(void *v) diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index d29b23bde7..5c7724828e 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2007-2010 coresystems GmbH * * This program is free software; you can redistribute it and/or modify @@ -21,7 +21,7 @@ /* Configuration of the i945 driver */ #define CHIPSET_I945GM 1 -/* Usually system firmware turns off system memory clock signals to +/* Usually system firmware turns off system memory clock signals to * unused SO-DIMM slots to reduce EMI and power consumption. * However, the Kontron 986LCD-M does not like unused clock signals to * be disabled. If other similar mainboard occur, it would make sense @@ -107,7 +107,7 @@ static void ich7_enable_lpc(void) pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000403e9); // COM4 decode pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000402e9); - // io 0x300 decode + // io 0x300 decode pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301); } @@ -119,7 +119,7 @@ static void ich7_enable_lpc(void) static void early_superio_config_w83627thg(void) { device_t dev; - + dev=PNP_DEV(0x2e, W83627THG_SP1); pnp_enter_ext_func_mode(dev); @@ -194,7 +194,7 @@ static void early_superio_config_w83627thg(void) pnp_set_irq(dev, PNP_IDX_IRQ0, 11); pnp_set_enable(dev, 1); - dev=PNP_DEV(0x4e, W83627THG_SP2); + dev=PNP_DEV(0x4e, W83627THG_SP2); pnp_set_logical_device(dev); // Set COM4 to sane non-conflicting values pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x2e8); @@ -249,7 +249,7 @@ static void rcba_config(void) * would essentially disable all three ethernet ports of the mainboard. * It's possible to rename the ports to achieve compatibility to the * PCI spec but this will confuse all (static!) tables containing - * interrupt routing information. + * interrupt routing information. * To avoid this, we enable (unused) port 6 and swap it with port 1 * in the case that ethernet port 1 is disabled. Since no devices * are connected to that port, we don't have to worry about interrupt @@ -413,7 +413,7 @@ void main(unsigned long bist) /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); - + #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 dump_spd_registers(); #endif @@ -423,8 +423,8 @@ void main(unsigned long bist) /* Perform some initialization that must run before stage2 */ early_ich7_init(); - /* This should probably go away. Until now it is required - * and mainboard specific + /* This should probably go away. Until now it is required + * and mainboard specific */ rcba_config(); @@ -470,7 +470,7 @@ void main(unsigned long bist) * memory completely, but that's a wonderful clean up task for another * day. */ - if (resume_backup_memory) + if (resume_backup_memory) memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE); /* Magic for S3 resume */ diff --git a/src/mainboard/kontron/986lcd-m/rtl8168.c b/src/mainboard/kontron/986lcd-m/rtl8168.c index e278bcfb4e..04fd56ccb1 100644 --- a/src/mainboard/kontron/986lcd-m/rtl8168.c +++ b/src/mainboard/kontron/986lcd-m/rtl8168.c @@ -28,7 +28,7 @@ static void nic_init(struct device *dev) { printk(BIOS_DEBUG, "Initializing RTL8168 Gigabit Ethernet\n"); - // Nothing to do yet, but this has to be here to keep + // Nothing to do yet, but this has to be here to keep // coreboot from trying to execute an option ROM. } diff --git a/src/mainboard/kontron/kt690/acpi/routing.asl b/src/mainboard/kontron/kt690/acpi/routing.asl index 4b6b111f05..2315120310 100644 --- a/src/mainboard/kontron/kt690/acpi/routing.asl +++ b/src/mainboard/kontron/kt690/acpi/routing.asl @@ -92,38 +92,38 @@ Scope(\_SB) { /* Bus 0, Dev 0 - RS690 Host Controller */ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){ 0x0002FFFF, 0, 0, 18 }, - Package(){ 0x0002FFFF, 1, 0, 19 }, - Package(){ 0x0002FFFF, 2, 0, 16 }, - Package(){ 0x0002FFFF, 3, 0, 17 }, + Package(){ 0x0002FFFF, 0, 0, 18 }, + Package(){ 0x0002FFFF, 1, 0, 19 }, + Package(){ 0x0002FFFF, 2, 0, 16 }, + Package(){ 0x0002FFFF, 3, 0, 17 }, /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){ 0x0003FFFF, 0, 0, 19 }, - Package(){ 0x0003FFFF, 1, 0, 16 }, - Package(){ 0x0003FFFF, 2, 0, 17 }, - Package(){ 0x0003FFFF, 3, 0, 18 }, - + Package(){ 0x0003FFFF, 0, 0, 19 }, + Package(){ 0x0003FFFF, 1, 0, 16 }, + Package(){ 0x0003FFFF, 2, 0, 17 }, + Package(){ 0x0003FFFF, 3, 0, 18 }, + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){ 0x0004FFFF, 0, 0, 16 }, - Package(){ 0x0004FFFF, 1, 0, 17 }, - Package(){ 0x0004FFFF, 2, 0, 18 }, - Package(){ 0x0004FFFF, 3, 0, 19 }, + Package(){ 0x0004FFFF, 0, 0, 16 }, + Package(){ 0x0004FFFF, 1, 0, 17 }, + Package(){ 0x0004FFFF, 2, 0, 18 }, + Package(){ 0x0004FFFF, 3, 0, 19 }, /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - Package(){ 0x0005FFFF, 0, 0, 17 }, - Package(){ 0x0005FFFF, 1, 0, 18 }, - Package(){ 0x0005FFFF, 2, 0, 19 }, - Package(){ 0x0005FFFF, 3, 0, 16 }, + Package(){ 0x0005FFFF, 0, 0, 17 }, + Package(){ 0x0005FFFF, 1, 0, 18 }, + Package(){ 0x0005FFFF, 2, 0, 19 }, + Package(){ 0x0005FFFF, 3, 0, 16 }, /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - Package(){ 0x0006FFFF, 0, 0, 18 }, - Package(){ 0x0006FFFF, 1, 0, 19 }, - Package(){ 0x0006FFFF, 2, 0, 16 }, - Package(){ 0x0006FFFF, 3, 0, 17 }, + Package(){ 0x0006FFFF, 0, 0, 18 }, + Package(){ 0x0006FFFF, 1, 0, 19 }, + Package(){ 0x0006FFFF, 2, 0, 16 }, + Package(){ 0x0006FFFF, 3, 0, 17 }, /* Bus 0, Dev 7 - PCIe Bridge for network card */ - Package(){ 0x0007FFFF, 0, 0, 19 }, - Package(){ 0x0007FFFF, 1, 0, 16 }, + Package(){ 0x0007FFFF, 0, 0, 19 }, + Package(){ 0x0007FFFF, 1, 0, 16 }, Package(){ 0x0007FFFF, 2, 0, 17 }, Package(){ 0x0007FFFF, 3, 0, 18 }, diff --git a/src/mainboard/lippert/Kconfig b/src/mainboard/lippert/Kconfig index 82c0b282e3..792a1430b7 100644 --- a/src/mainboard/lippert/Kconfig +++ b/src/mainboard/lippert/Kconfig @@ -1,7 +1,7 @@ choice prompt "Mainboard model" depends on VENDOR_LIPPERT - + source "src/mainboard/lippert/frontrunner/Kconfig" source "src/mainboard/lippert/roadrunner-lx/Kconfig" source "src/mainboard/lippert/spacerunner-lx/Kconfig" diff --git a/src/mainboard/lippert/frontrunner/devicetree.cb b/src/mainboard/lippert/frontrunner/devicetree.cb index 28c6af67a1..1386de9d77 100644 --- a/src/mainboard/lippert/frontrunner/devicetree.cb +++ b/src/mainboard/lippert/frontrunner/devicetree.cb @@ -1,7 +1,7 @@ chip northbridge/amd/gx2 register "setupflash" = "0" #register "irqmap" = "0xaa5b" - device pci_domain 0 on + device pci_domain 0 on device pci 0.0 on end chip southbridge/amd/cs5535 device pci 12.0 on diff --git a/src/mainboard/lippert/frontrunner/irq_tables.c b/src/mainboard/lippert/frontrunner/irq_tables.c index 598350b4b8..f751b481ca 100644 --- a/src/mainboard/lippert/frontrunner/irq_tables.c +++ b/src/mainboard/lippert/frontrunner/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up * diff --git a/src/mainboard/lippert/frontrunner/romstage.c b/src/mainboard/lippert/frontrunner/romstage.c index 4c3f615da0..87337a2be9 100644 --- a/src/mainboard/lippert/frontrunner/romstage.c +++ b/src/mainboard/lippert/frontrunner/romstage.c @@ -19,7 +19,7 @@ #include "northbridge/amd/gx2/raminit.h" /* this has to be done on a per-mainboard basis, esp. if you don't have smbus */ -static void sdram_set_spd_registers(const struct mem_controller *ctrl) +static void sdram_set_spd_registers(const struct mem_controller *ctrl) { msr_t msr; /* 1. Initialize GLMC registers base on SPD values, diff --git a/src/mainboard/mitac/Kconfig b/src/mainboard/mitac/Kconfig index a02f150f9d..34cb1de7aa 100644 --- a/src/mainboard/mitac/Kconfig +++ b/src/mainboard/mitac/Kconfig @@ -21,7 +21,7 @@ choice prompt "Mainboard model" depends on VENDOR_MITAC - + source "src/mainboard/mitac/6513wu/Kconfig" endchoice diff --git a/src/mainboard/msi/Kconfig b/src/mainboard/msi/Kconfig index 7377da7f65..fd836987e3 100644 --- a/src/mainboard/msi/Kconfig +++ b/src/mainboard/msi/Kconfig @@ -21,7 +21,7 @@ choice prompt "Mainboard model" depends on VENDOR_MSI - + source "src/mainboard/msi/ms6119/Kconfig" source "src/mainboard/msi/ms6147/Kconfig" source "src/mainboard/msi/ms6156/Kconfig" diff --git a/src/mainboard/msi/ms6147/irq_tables.c b/src/mainboard/msi/ms6147/irq_tables.c index b3cd1194a6..d41e9b7115 100644 --- a/src/mainboard/msi/ms6147/irq_tables.c +++ b/src/mainboard/msi/ms6147/irq_tables.c @@ -35,7 +35,7 @@ const struct irq_routing_table intel_irq_routing_table = { { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00,(0x0e<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0}, - {0x00,(0x10<<3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0}, + {0x00,(0x10<<3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0}, {0x00,(0x12<<3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x3, 0x0}, {0x00,(0x14<<3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x4, 0x0}, {0x00,(0x00<<3)|0x0, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, /* North bridge */ diff --git a/src/mainboard/msi/ms7135/get_bus_conf.c b/src/mainboard/msi/ms7135/get_bus_conf.c index ae7a7f1a03..6ccd97587d 100644 --- a/src/mainboard/msi/ms7135/get_bus_conf.c +++ b/src/mainboard/msi/ms7135/get_bus_conf.c @@ -47,7 +47,7 @@ unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO 0x0000ff0, //no HTIO for ms7135 }; unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most - 0x20202020, //ms7135 has only one ht-chain + 0x20202020, //ms7135 has only one ht-chain }; unsigned bus_type[256]; @@ -100,7 +100,7 @@ void get_bus_conf(void) switch (i) { case 1: dn = 9; break; case 2: dn = 13; break; - case 3: dn = 14; break; + case 3: dn = 14; break; default: dn = -1; break; } dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + dn, 0)); diff --git a/src/mainboard/msi/ms7135/irq_tables.c b/src/mainboard/msi/ms7135/irq_tables.c index f43af44bf5..e4a717ba72 100644 --- a/src/mainboard/msi/ms7135/irq_tables.c +++ b/src/mainboard/msi/ms7135/irq_tables.c @@ -78,7 +78,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) int i; unsigned sbdn; - /* get_bus_conf() will find out all bus num and apic that share with + /* get_bus_conf() will find out all bus num and apic that share with * mptable.c and mptable.c */ get_bus_conf(); @@ -112,7 +112,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq_info = (void *)(&pirq->checksum + 1); slot_num = 0; -//Slot1 PCIE 16x +//Slot1 PCIE 16x write_pirq_info(pirq_info, bus_ck804[1], (0 << 3) | 0, 0x3, 0xdeb8, 0x4, 0xdeb8, 0x1, 0xdeb8, 0x2, 0xdeb8, 4, 0); pirq_info++; @@ -130,7 +130,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq_info++; slot_num++; -//Slot4 PCIE 4x +//Slot4 PCIE 4x write_pirq_info(pirq_info, bus_ck804[4], (0x4 << 3) | 0, 0x2, 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 0x1, 0xdeb8, 7, 0); @@ -229,7 +229,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) irq[0] = 10; /* Ethernet */ pci_assign_irqs(bus_ck804[0], 10, irq); - + /* physical slots */ irq[0] = 5; /* PCI E1 - x1 */ @@ -237,7 +237,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) irq[0] = 11; /* PCI E2 - x16 */ pci_assign_irqs(bus_ck804[3], 0, irq); - + /* AGP-on-PCI "AGR" ignored */ irq[0] = 10; /* PCI1 */ @@ -257,7 +257,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) irq[2] = 11; irq[3] = 0; pci_assign_irqs(bus_ck804[1], 9, irq); -#endif +#endif return (unsigned long)pirq_info; } diff --git a/src/mainboard/msi/ms7260/Kconfig b/src/mainboard/msi/ms7260/Kconfig index 9752597d7a..cce07a7f94 100644 --- a/src/mainboard/msi/ms7260/Kconfig +++ b/src/mainboard/msi/ms7260/Kconfig @@ -15,7 +15,7 @@ config BOARD_MSI_MS7260 select LIFT_BSP_APIC_ID select K8_REV_F_SUPPORT select BOARD_ROMSIZE_KB_512 - + config MAINBOARD_DIR string default msi/ms7260 @@ -25,7 +25,7 @@ config DCACHE_RAM_BASE hex default 0xc8000 depends on BOARD_MSI_MS7260 - + config DCACHE_RAM_SIZE hex default 0x08000 @@ -37,7 +37,7 @@ config DCACHE_RAM_GLOBAL_VAR_SIZE depends on BOARD_MSI_MS7260 config APIC_ID_OFFSET - hex + hex default 0x10 depends on BOARD_MSI_MS7260 @@ -77,7 +77,7 @@ config MAX_PHYSICAL_CPUS depends on BOARD_MSI_MS7260 config HW_MEM_HOLE_SIZE_AUTO_INC - bool + bool default n depends on BOARD_MSI_MS7260 @@ -87,12 +87,12 @@ config HT_CHAIN_UNITID_BASE depends on BOARD_MSI_MS7260 config HT_CHAIN_END_UNITID_BASE - hex + hex default 0x20 depends on BOARD_MSI_MS7260 config SERIAL_CPU_INIT - bool + bool default n depends on BOARD_MSI_MS7260 diff --git a/src/mainboard/msi/ms7260/cmos.layout b/src/mainboard/msi/ms7260/cmos.layout index 51f4a6c598..5266518e56 100644 --- a/src/mainboard/msi/ms7260/cmos.layout +++ b/src/mainboard/msi/ms7260/cmos.layout @@ -1,22 +1,22 @@ -## +## ## This file is part of the coreboot project. -## +## ## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> -## +## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or ## (at your option) any later version. -## +## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. -## +## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## +## # TODO: Check and fix up the values as needed. diff --git a/src/mainboard/msi/ms7260/resourcemap.c b/src/mainboard/msi/ms7260/resourcemap.c index d72530a3ae..a051500c64 100644 --- a/src/mainboard/msi/ms7260/resourcemap.c +++ b/src/mainboard/msi/ms7260/resourcemap.c @@ -163,7 +163,7 @@ static void setup_mb_resource_map(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, @@ -201,7 +201,7 @@ static void setup_mb_resource_map(void) * [31:25] Reserved */ // PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000, - PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, @@ -219,7 +219,7 @@ static void setup_mb_resource_map(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -227,7 +227,7 @@ static void setup_mb_resource_map(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033, @@ -272,9 +272,9 @@ static void setup_mb_resource_map(void) * This field defines the highest bus number in configuration region i */ // PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of cpu 0 --> Nvidia MCP55 */ - PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, }; diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index 3f7b69dc1b..a5fbffbe4b 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -152,7 +152,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) (0xa << 3) | 5, (0xa << 3) | 7, 0, 0, }; - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); int needs_reset = 0; diff --git a/src/mainboard/msi/ms9282/Kconfig b/src/mainboard/msi/ms9282/Kconfig index bd73487313..cf1896d2d7 100644 --- a/src/mainboard/msi/ms9282/Kconfig +++ b/src/mainboard/msi/ms9282/Kconfig @@ -14,7 +14,7 @@ config BOARD_MSI_MS9282 select HAVE_HARD_RESET select K8_REV_F_SUPPORT select BOARD_ROMSIZE_KB_512 - + config MAINBOARD_DIR string default msi/ms9282 @@ -24,7 +24,7 @@ config DCACHE_RAM_BASE hex default 0xcc000 depends on BOARD_MSI_MS9282 - + config DCACHE_RAM_SIZE hex default 0x04000 @@ -36,7 +36,7 @@ config DCACHE_RAM_GLOBAL_VAR_SIZE depends on BOARD_MSI_MS9282 config APIC_ID_OFFSET - hex + hex default 0x10 depends on BOARD_MSI_MS9282 @@ -71,7 +71,7 @@ config MAX_PHYSICAL_CPUS depends on BOARD_MSI_MS9282 config HW_MEM_HOLE_SIZE_AUTO_INC - bool + bool default n depends on BOARD_MSI_MS9282 @@ -81,12 +81,12 @@ config HT_CHAIN_UNITID_BASE depends on BOARD_MSI_MS9282 config HT_CHAIN_END_UNITID_BASE - hex + hex default 0x20 depends on BOARD_MSI_MS9282 config SERIAL_CPU_INIT - bool + bool default n depends on BOARD_MSI_MS9282 diff --git a/src/mainboard/msi/ms9282/Makefile.inc b/src/mainboard/msi/ms9282/Makefile.inc index 8f94666961..e94ce3fd0e 100644 --- a/src/mainboard/msi/ms9282/Makefile.inc +++ b/src/mainboard/msi/ms9282/Makefile.inc @@ -1,6 +1,6 @@ ## ## This file is part of the coreboot project. -## +## ## Copyright (C) 2007-2008 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify diff --git a/src/mainboard/msi/ms9652_fam10/acpi_tables.c b/src/mainboard/msi/ms9652_fam10/acpi_tables.c index 54e8be4f67..c76f830d89 100644 --- a/src/mainboard/msi/ms9652_fam10/acpi_tables.c +++ b/src/mainboard/msi/ms9652_fam10/acpi_tables.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Written by Stefan Reinauer <stepan@openbios.org>. - * ACPI FADT, FACS, and DSDT table support added by + * ACPI FADT, FACS, and DSDT table support added by * * Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org> * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com> @@ -49,7 +49,7 @@ unsigned long acpi_fill_madt(unsigned long current) struct mb_sysconf_t *m; //extern unsigned char bus_mcp55[8]; //extern unsigned apicid_mcp55; - + unsigned sbdn; struct resource *res; device_t dev; @@ -57,7 +57,7 @@ unsigned long acpi_fill_madt(unsigned long current) get_bus_conf(); sbdn = sysconf.sbdn; m = sysconf.mb; - + /* Create all subtables for processors. */ current = acpi_create_madt_lapics(current); @@ -87,7 +87,7 @@ unsigned long acpi_fill_madt(unsigned long current) /* IRQ0 -> APIC IRQ2. */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0x0); + current, 0, 0, 2, 0x0); /* Create all subtables for processors. */ current = acpi_create_madt_lapic_nmis(current, diff --git a/src/mainboard/msi/ms9652_fam10/dsdt.asl b/src/mainboard/msi/ms9652_fam10/dsdt.asl index 84e1a76630..e5361b6822 100644 --- a/src/mainboard/msi/ms9652_fam10/dsdt.asl +++ b/src/mainboard/msi/ms9652_fam10/dsdt.asl @@ -51,7 +51,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) External (HCLK) External (SBDN) External (HCDN) - + Method (_CRS, 0, NotSerialized) { Name (BUF0, ResourceTemplate () @@ -272,7 +272,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) Method (_CRS, 0, NotSerialized) { Name (BUF1, ResourceTemplate () { - IO (Decode16, 0x0378, 0x0378, 0x01, 0x08) + IO (Decode16, 0x0378, 0x0378, 0x01, 0x08) IRQNoFlags () {7} }) Return (BUF1) @@ -289,7 +289,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) Method (_CRS, 0, NotSerialized) { Name (BUF1, ResourceTemplate () { - IO (Decode16, 0x0378, 0x0378, 0x01, 0x04) + IO (Decode16, 0x0378, 0x0378, 0x01, 0x04) IO (Decode16, 0x0778, 0x0778, 0x01, 0x04) IRQNoFlags() {7} DMA (Compatibility, NotBusMaster, Transfer8) {0,1,3} diff --git a/src/mainboard/msi/ms9652_fam10/irq_tables.c b/src/mainboard/msi/ms9652_fam10/irq_tables.c index bb14f3310b..a1de4c4f57 100644 --- a/src/mainboard/msi/ms9652_fam10/irq_tables.c +++ b/src/mainboard/msi/ms9652_fam10/irq_tables.c @@ -19,7 +19,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! * (but if you do, please run checkpir on it to verify) * Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up @@ -34,11 +34,11 @@ #include <cpu/amd/amdfam10_sysconf.h> #include "mb_sysconf.h" -static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, +static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; + pirq_info->bus = bus; pirq_info->devfn = devfn; pirq_info->irq[0].link = link0; pirq_info->irq[0].bitmap = bitmap0; @@ -80,15 +80,15 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq = (void *)(addr); v = (uint8_t *)(addr); - + pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - + pirq->rtr_bus = m->bus_mcp55[0]; pirq->rtr_devfn = ((sbdn+6)<<3)|0; pirq->exclusive_irqs = 0; - + pirq->rtr_vendor = 0x10de; pirq->rtr_device = 0x0370; @@ -101,7 +101,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) //pci bridge write_pirq_info(pirq_info, m->bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; - + for(i=1; i< sysconf.hc_possible_num; i++) { if(!(sysconf.pci1234[i] & 0x1) ) continue; unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff; @@ -120,10 +120,10 @@ unsigned long write_pirq_routing_table(unsigned long addr) } #endif - pirq->size = 32 + 16 * slot_num; + pirq->size = 32 + 16 * slot_num; for (i = 0; i < pirq->size; i++) - sum += v[i]; + sum += v[i]; sum = pirq->checksum - sum; diff --git a/src/mainboard/msi/ms9652_fam10/mb_sysconf.h b/src/mainboard/msi/ms9652_fam10/mb_sysconf.h index 83f9dbab28..a2e6fc7ade 100644 --- a/src/mainboard/msi/ms9652_fam10/mb_sysconf.h +++ b/src/mainboard/msi/ms9652_fam10/mb_sysconf.h @@ -26,7 +26,7 @@ struct mb_sysconf_t { unsigned char bus_isa; unsigned char bus_mcp55[8]; //1 unsigned apicid_mcp55; - unsigned bus_type[256]; + unsigned bus_type[256]; }; diff --git a/src/mainboard/newisys/Kconfig b/src/mainboard/newisys/Kconfig index fd8f9176e1..308cced541 100644 --- a/src/mainboard/newisys/Kconfig +++ b/src/mainboard/newisys/Kconfig @@ -1,7 +1,7 @@ choice prompt "Mainboard model" depends on VENDOR_NEWISYS - + source "src/mainboard/newisys/khepri/Kconfig" endchoice diff --git a/src/mainboard/newisys/khepri/devicetree.cb b/src/mainboard/newisys/khepri/devicetree.cb index cb8f356e5a..30e73f774d 100644 --- a/src/mainboard/newisys/khepri/devicetree.cb +++ b/src/mainboard/newisys/khepri/devicetree.cb @@ -10,7 +10,7 @@ chip northbridge/amd/amdk8/root_complex device pci_domain 0 on chip northbridge/amd/amdk8 - device pci 18.0 on end # LDT 0 + device pci 18.0 on end # LDT 0 device pci 18.0 on # LDT 1 chip southbridge/amd/amd8131 device pci 0.0 on end @@ -57,7 +57,7 @@ chip northbridge/amd/amdk8/root_complex io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 - end + end device pnp 2e.8 off end # GPIO2 device pnp 2e.9 off end # GPIO3 device pnp 2e.a off end # ACPI @@ -69,7 +69,7 @@ chip northbridge/amd/amdk8/root_complex end device pci 1.1 on end device pci 1.2 on end - device pci 1.3 on end + device pci 1.3 on end device pci 1.5 on end device pci 1.6 on end end @@ -87,6 +87,6 @@ chip northbridge/amd/amdk8/root_complex device pci 19.2 on end device pci 19.3 on end end - end + end end diff --git a/src/mainboard/newisys/khepri/resourcemap.c b/src/mainboard/newisys/khepri/resourcemap.c index d533b6357e..81bdefa835 100644 --- a/src/mainboard/newisys/khepri/resourcemap.c +++ b/src/mainboard/newisys/khepri/resourcemap.c @@ -151,7 +151,7 @@ static void setup_khepri_resource_map(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, @@ -207,7 +207,7 @@ static void setup_khepri_resource_map(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -215,7 +215,7 @@ static void setup_khepri_resource_map(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003, diff --git a/src/mainboard/newisys/khepri/romstage.c b/src/mainboard/newisys/khepri/romstage.c index e8c040950f..bf1186df46 100644 --- a/src/mainboard/newisys/khepri/romstage.c +++ b/src/mainboard/newisys/khepri/romstage.c @@ -1,10 +1,10 @@ /* * This code is derived from the Tyan s2882 romstage.c * Adapted by Stefan Reinauer <stepan@coresystems.de> - * Additional (C) 2007 coresystems GmbH + * Additional (C) 2007 coresystems GmbH */ - + #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -81,7 +81,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" /* newisys khepri does not want the default */ -#include "resourcemap.c" +#include "resourcemap.c" #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 @@ -129,13 +129,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } // post_code(0x32); - + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - + /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/nvidia/Kconfig b/src/mainboard/nvidia/Kconfig index 54a0c0a99c..ac3b92f915 100644 --- a/src/mainboard/nvidia/Kconfig +++ b/src/mainboard/nvidia/Kconfig @@ -1,7 +1,7 @@ choice prompt "Mainboard model" depends on VENDOR_NVIDIA - + source "src/mainboard/nvidia/l1_2pvv/Kconfig" endchoice diff --git a/src/mainboard/nvidia/l1_2pvv/Kconfig b/src/mainboard/nvidia/l1_2pvv/Kconfig index 80f9f16d33..ab361f175f 100644 --- a/src/mainboard/nvidia/l1_2pvv/Kconfig +++ b/src/mainboard/nvidia/l1_2pvv/Kconfig @@ -15,7 +15,7 @@ config BOARD_NVIDIA_L1_2PVV select LIFT_BSP_APIC_ID select K8_REV_F_SUPPORT select BOARD_ROMSIZE_KB_512 - + config MAINBOARD_DIR string default nvidia/l1_2pvv @@ -25,7 +25,7 @@ config DCACHE_RAM_BASE hex default 0xc8000 depends on BOARD_NVIDIA_L1_2PVV - + config DCACHE_RAM_SIZE hex default 0x08000 @@ -37,7 +37,7 @@ config DCACHE_RAM_GLOBAL_VAR_SIZE depends on BOARD_NVIDIA_L1_2PVV config APIC_ID_OFFSET - hex + hex default 0x10 depends on BOARD_NVIDIA_L1_2PVV @@ -77,7 +77,7 @@ config MAX_PHYSICAL_CPUS depends on BOARD_NVIDIA_L1_2PVV config HW_MEM_HOLE_SIZE_AUTO_INC - bool + bool default n depends on BOARD_NVIDIA_L1_2PVV @@ -87,12 +87,12 @@ config HT_CHAIN_UNITID_BASE depends on BOARD_NVIDIA_L1_2PVV config HT_CHAIN_END_UNITID_BASE - hex + hex default 0x20 depends on BOARD_NVIDIA_L1_2PVV config SERIAL_CPU_INIT - bool + bool default n depends on BOARD_NVIDIA_L1_2PVV diff --git a/src/mainboard/olpc/Kconfig b/src/mainboard/olpc/Kconfig index 658ebb51c6..a74f393774 100644 --- a/src/mainboard/olpc/Kconfig +++ b/src/mainboard/olpc/Kconfig @@ -1,7 +1,7 @@ choice prompt "Mainboard model" depends on VENDOR_OLPC - + source "src/mainboard/olpc/rev_a/Kconfig" source "src/mainboard/olpc/btest/Kconfig" diff --git a/src/mainboard/olpc/btest/devicetree.cb b/src/mainboard/olpc/btest/devicetree.cb index e0da82836a..ca55ce1b7e 100644 --- a/src/mainboard/olpc/btest/devicetree.cb +++ b/src/mainboard/olpc/btest/devicetree.cb @@ -6,7 +6,7 @@ chip northbridge/amd/gx2 device apic 0 on end end end - device pci_domain 0 on + device pci_domain 0 on device pci 1.0 on end device pci 1.1 on end chip southbridge/amd/cs5536 @@ -18,7 +18,7 @@ chip northbridge/amd/gx2 # SIRQ Mode = continous , It would be better if the EC could operate in # Active(Quiet) mode. Save power.... # SIRQ Enable = Enabled - # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK + # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK #register "lpc_irq" = "0x00001002" #register "lpc_serirq_enable" = "0xEFFD0080" #register "enable_gpio0_inta" = "1" diff --git a/src/mainboard/olpc/btest/irq_tables.c b/src/mainboard/olpc/btest/irq_tables.c index 598350b4b8..f751b481ca 100644 --- a/src/mainboard/olpc/btest/irq_tables.c +++ b/src/mainboard/olpc/btest/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up * diff --git a/src/mainboard/olpc/btest/mainboard.c b/src/mainboard/olpc/btest/mainboard.c index b184a566d0..1e5add3dc0 100644 --- a/src/mainboard/olpc/btest/mainboard.c +++ b/src/mainboard/olpc/btest/mainboard.c @@ -73,26 +73,26 @@ static void init_cafe_irq(void){ const unsigned char slots_cafe[4] = {11, 0, 0, 0}; - - /* CAFE PCI slots */ - pci_assign_irqs(0, 0x0C, slots_cafe); - - /* Make the pin assignments - NOTENOTENOTE: This should be - * configurable! - */ - - /* Configure the GPIO pins to use - class 0, index 9 to configure - * AB. Write 0xFF to disable - */ - - vrWrite(0x9, 0XFF00); - - /* Configure the GPIO pins to use - class 0, index A to configure - * CD. Write 0xFF to disable - */ - - vrWrite(0xA, 0xFFFF); - + + /* CAFE PCI slots */ + pci_assign_irqs(0, 0x0C, slots_cafe); + + /* Make the pin assignments - NOTENOTENOTE: This should be + * configurable! + */ + + /* Configure the GPIO pins to use - class 0, index 9 to configure + * AB. Write 0xFF to disable + */ + + vrWrite(0x9, 0XFF00); + + /* Configure the GPIO pins to use - class 0, index A to configure + * CD. Write 0xFF to disable + */ + + vrWrite(0xA, 0xFFFF); + } @@ -111,7 +111,7 @@ static void init(struct device *dev) { * conditional we can make it a config variable later. */ - printk(BIOS_DEBUG, "%s (%x,%x)SET USB PCI interrupt line to %d\n", + printk(BIOS_DEBUG, "%s (%x,%x)SET USB PCI interrupt line to %d\n", __func__, bus, devfn, usbirq); usb = dev_find_slot(bus, devfn); if (! usb){ diff --git a/src/mainboard/olpc/btest/romstage.c b/src/mainboard/olpc/btest/romstage.c index 1503baa6ba..fc605d1a88 100644 --- a/src/mainboard/olpc/btest/romstage.c +++ b/src/mainboard/olpc/btest/romstage.c @@ -50,7 +50,7 @@ static inline unsigned int fls(unsigned int x) Trrd=2 (act2act) Tref=17.8ms */ -static void sdram_set_spd_registers(const struct mem_controller *ctrl) +static void sdram_set_spd_registers(const struct mem_controller *ctrl) { /* Total size of DIMM = 2^row address (byte 3) * 2^col address (byte 4) * * component Banks (byte 17) * module banks, side (byte 5) * @@ -100,11 +100,11 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) /* timing and mode ... */ msr = rdmsr(0x20000019); - - /* per standard bios settings */ + + /* per standard bios settings */ msr.hi = 0x18000108; - msr.lo = + msr.lo = (6<<28) | // cas_lat (10<<24)| // ref2act (7<<20)| // act2pre @@ -114,8 +114,8 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) (2<<6)| // dplwr (2<<4)| // dplrd (3); // dal - /* the msr value reported by quanta is very, very different. - * we will go with that value for now. + /* the msr value reported by quanta is very, very different. + * we will go with that value for now. */ msr.lo = 0x286332a3; @@ -180,9 +180,9 @@ static void main(unsigned long bist) cpuRegInit(); print_err("done cpuRegInit\n"); - + sdram_initialize(1, memctrl); - + /* Check all of memory */ //ram_check(0x00000000, 640*1024); } diff --git a/src/mainboard/olpc/rev_a/devicetree.cb b/src/mainboard/olpc/rev_a/devicetree.cb index e0da82836a..ca55ce1b7e 100644 --- a/src/mainboard/olpc/rev_a/devicetree.cb +++ b/src/mainboard/olpc/rev_a/devicetree.cb @@ -6,7 +6,7 @@ chip northbridge/amd/gx2 device apic 0 on end end end - device pci_domain 0 on + device pci_domain 0 on device pci 1.0 on end device pci 1.1 on end chip southbridge/amd/cs5536 @@ -18,7 +18,7 @@ chip northbridge/amd/gx2 # SIRQ Mode = continous , It would be better if the EC could operate in # Active(Quiet) mode. Save power.... # SIRQ Enable = Enabled - # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK + # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK #register "lpc_irq" = "0x00001002" #register "lpc_serirq_enable" = "0xEFFD0080" #register "enable_gpio0_inta" = "1" diff --git a/src/mainboard/olpc/rev_a/irq_tables.c b/src/mainboard/olpc/rev_a/irq_tables.c index 598350b4b8..f751b481ca 100644 --- a/src/mainboard/olpc/rev_a/irq_tables.c +++ b/src/mainboard/olpc/rev_a/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up * diff --git a/src/mainboard/olpc/rev_a/mainboard.c b/src/mainboard/olpc/rev_a/mainboard.c index a02e583558..adfb957ab7 100644 --- a/src/mainboard/olpc/rev_a/mainboard.c +++ b/src/mainboard/olpc/rev_a/mainboard.c @@ -83,7 +83,7 @@ static void init(struct device *dev) { * conditional we can make it a config variable later. */ - printk(BIOS_DEBUG, "%s (%x,%x)SET USB PCI interrupt line to %d\n", + printk(BIOS_DEBUG, "%s (%x,%x)SET USB PCI interrupt line to %d\n", __func__, bus, devfn, usbirq); usb = dev_find_slot(bus, devfn); if (! usb){ diff --git a/src/mainboard/olpc/rev_a/romstage.c b/src/mainboard/olpc/rev_a/romstage.c index 1503baa6ba..fc605d1a88 100644 --- a/src/mainboard/olpc/rev_a/romstage.c +++ b/src/mainboard/olpc/rev_a/romstage.c @@ -50,7 +50,7 @@ static inline unsigned int fls(unsigned int x) Trrd=2 (act2act) Tref=17.8ms */ -static void sdram_set_spd_registers(const struct mem_controller *ctrl) +static void sdram_set_spd_registers(const struct mem_controller *ctrl) { /* Total size of DIMM = 2^row address (byte 3) * 2^col address (byte 4) * * component Banks (byte 17) * module banks, side (byte 5) * @@ -100,11 +100,11 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) /* timing and mode ... */ msr = rdmsr(0x20000019); - - /* per standard bios settings */ + + /* per standard bios settings */ msr.hi = 0x18000108; - msr.lo = + msr.lo = (6<<28) | // cas_lat (10<<24)| // ref2act (7<<20)| // act2pre @@ -114,8 +114,8 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) (2<<6)| // dplwr (2<<4)| // dplrd (3); // dal - /* the msr value reported by quanta is very, very different. - * we will go with that value for now. + /* the msr value reported by quanta is very, very different. + * we will go with that value for now. */ msr.lo = 0x286332a3; @@ -180,9 +180,9 @@ static void main(unsigned long bist) cpuRegInit(); print_err("done cpuRegInit\n"); - + sdram_initialize(1, memctrl); - + /* Check all of memory */ //ram_check(0x00000000, 640*1024); } diff --git a/src/mainboard/pcengines/Kconfig b/src/mainboard/pcengines/Kconfig index 23b46536c8..c1b0168505 100644 --- a/src/mainboard/pcengines/Kconfig +++ b/src/mainboard/pcengines/Kconfig @@ -1,7 +1,7 @@ choice prompt "Mainboard model" depends on VENDOR_PC_ENGINES - + source "src/mainboard/pcengines/alix1c/Kconfig" endchoice diff --git a/src/mainboard/pcengines/alix1c/Kconfig b/src/mainboard/pcengines/alix1c/Kconfig index 3e1237a47c..0ba52ce937 100644 --- a/src/mainboard/pcengines/alix1c/Kconfig +++ b/src/mainboard/pcengines/alix1c/Kconfig @@ -14,7 +14,7 @@ config BOARD_PCENGINES_ALIX1C config MAINBOARD_DIR string - default pcengines/alix1c + default pcengines/alix1c depends on BOARD_PCENGINES_ALIX1C config MAINBOARD_PART_NUMBER diff --git a/src/mainboard/pcengines/alix1c/devicetree.cb b/src/mainboard/pcengines/alix1c/devicetree.cb index 34668d1025..f40e302956 100644 --- a/src/mainboard/pcengines/alix1c/devicetree.cb +++ b/src/mainboard/pcengines/alix1c/devicetree.cb @@ -1,5 +1,5 @@ chip northbridge/amd/lx - device pci_domain 0 on + device pci_domain 0 on device pci 1.0 on end device pci 1.1 on end chip southbridge/amd/cs5536 @@ -57,7 +57,7 @@ chip northbridge/amd/lx io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 - end + end device pnp 2e.8 on end # GPIO2 device pnp 2e.9 on end # GPIO3 device pnp 2e.a on end # ACPI diff --git a/src/mainboard/rca/Kconfig b/src/mainboard/rca/Kconfig index e4e913559d..bd272be17e 100644 --- a/src/mainboard/rca/Kconfig +++ b/src/mainboard/rca/Kconfig @@ -1,7 +1,7 @@ choice prompt "Mainboard model" depends on VENDOR_RCA - + source "src/mainboard/rca/rm4100/Kconfig" endchoice diff --git a/src/mainboard/rca/rm4100/chip.h b/src/mainboard/rca/rm4100/chip.h index 14d6677a22..c46c318c29 100644 --- a/src/mainboard/rca/rm4100/chip.h +++ b/src/mainboard/rca/rm4100/chip.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org> + * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/rca/rm4100/gpio.c b/src/mainboard/rca/rm4100/gpio.c index a27b7bb327..0f7512c1b2 100644 --- a/src/mainboard/rca/rm4100/gpio.c +++ b/src/mainboard/rca/rm4100/gpio.c @@ -58,13 +58,13 @@ static void mb_gpio_init(void) outl(0x01, PME_IO_BASE_ADDR + 0x2c); /* GP30 - FAN2_TACH */ - outl(0x05, PME_IO_BASE_ADDR + 0x33); + outl(0x05, PME_IO_BASE_ADDR + 0x33); /* GP31 - FAN1_TACH */ outl(0x05, PME_IO_BASE_ADDR + 0x34); /* GP32 - FAN2_CTRL */ - outl(0x04, PME_IO_BASE_ADDR + 0x35); + outl(0x04, PME_IO_BASE_ADDR + 0x35); /* GP33 - FAN1_CTRL */ outl(0x04, PME_IO_BASE_ADDR + 0x36); @@ -79,7 +79,7 @@ static void mb_gpio_init(void) outl(0x00, PME_IO_BASE_ADDR + 0x3a); /* GP42 - GPIO_PME_OUT */ - outl(0x00, PME_IO_BASE_ADDR + 0x3d); + outl(0x00, PME_IO_BASE_ADDR + 0x3d); /* GP50 - SER2_RI */ outl(0x05, PME_IO_BASE_ADDR + 0x3f); diff --git a/src/mainboard/rca/rm4100/mainboard.c b/src/mainboard/rca/rm4100/mainboard.c index 2248ba791e..653b22ab76 100644 --- a/src/mainboard/rca/rm4100/mainboard.c +++ b/src/mainboard/rca/rm4100/mainboard.c @@ -38,7 +38,7 @@ static void mainboard_enable(device_t dev) // TODO Switch parport LEDs dev->ops->init = mainboard_init; } - + struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, CHIP_NAME("RCA RM4100 Mainboard") diff --git a/src/mainboard/rca/rm4100/romstage.c b/src/mainboard/rca/rm4100/romstage.c index 5830af0b40..554d7f125b 100644 --- a/src/mainboard/rca/rm4100/romstage.c +++ b/src/mainboard/rca/rm4100/romstage.c @@ -88,11 +88,11 @@ static void mb_early_setup(void) /* CPU Frequency Strap */ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd5, 0x02); /* ACPI base address and enable Resource Indicator */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, (PMBASE_ADDR | 1)); + pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, (PMBASE_ADDR | 1)); /* Enable the SMBUS */ enable_smbus(); /* ACPI base address and disable Resource Indicator */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, (PMBASE_ADDR)); + pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, (PMBASE_ADDR)); /* ACPI Enable */ pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x10); } diff --git a/src/mainboard/roda/rk886ex/acpi/battery.asl b/src/mainboard/roda/rk886ex/acpi/battery.asl index 77269ad143..df61526867 100644 --- a/src/mainboard/roda/rk886ex/acpi/battery.asl +++ b/src/mainboard/roda/rk886ex/acpi/battery.asl @@ -113,7 +113,7 @@ Device (BAT1) } } } - + Store (CBA1, Local0) Store (Local0, Index(PBST, 2)) Store (DerefOf(Index(PBIF, 4)), Index(PBST, 3)) @@ -130,7 +130,7 @@ Device (BAT1) Store (1, Local1) } } - + Store (Local1, Index(PBST, 0)) If (\_SB.PCI0.LPCB.EC0.P63S) { Store (0x16, Index(PBST, 1)) @@ -253,7 +253,7 @@ Device (BAT2) } } } - + Store (CBA2, Local0) Store (Local0, Index(PBST, 2)) Store (DerefOf(Index(PBIF, 4)), Index(PBST, 3)) @@ -270,7 +270,7 @@ Device (BAT2) Store (1, Local1) } } - + Store (Local1, Index(PBST, 0)) If (\_SB.PCI0.LPCB.EC0.P62S) { Store (0x16, Index(PBST, 1)) diff --git a/src/mainboard/roda/rk886ex/acpi/ec.asl b/src/mainboard/roda/rk886ex/acpi/ec.asl index 2b8c7ea429..fc0ae547e2 100644 --- a/src/mainboard/roda/rk886ex/acpi/ec.asl +++ b/src/mainboard/roda/rk886ex/acpi/ec.asl @@ -81,14 +81,14 @@ Device(EC0) { // This method is needed by Windows XP/2000 for // EC initialization before a driver is loaded - + If (LEqual(Arg0, 0x03)) { Store (Arg1, ECON) } } // EC Query methods - + Method (_Q11, 0) { Store("_Q11: Fn-F8 (Sleep Button) pressed", Debug) diff --git a/src/mainboard/roda/rk886ex/acpi/i945_pci_irqs.asl b/src/mainboard/roda/rk886ex/acpi/i945_pci_irqs.asl index 6a16b5b887..674c3d41f0 100644 --- a/src/mainboard/roda/rk886ex/acpi/i945_pci_irqs.asl +++ b/src/mainboard/roda/rk886ex/acpi/i945_pci_irqs.asl @@ -19,7 +19,7 @@ * MA 02110-1301 USA */ -/* This is board specific information: IRQ routing for the +/* This is board specific information: IRQ routing for the * i945 */ diff --git a/src/mainboard/roda/rk886ex/acpi/ich7_pci_irqs.asl b/src/mainboard/roda/rk886ex/acpi/ich7_pci_irqs.asl index 4c4edd7c17..dc1f9da6f6 100644 --- a/src/mainboard/roda/rk886ex/acpi/ich7_pci_irqs.asl +++ b/src/mainboard/roda/rk886ex/acpi/ich7_pci_irqs.asl @@ -19,7 +19,7 @@ * MA 02110-1301 USA */ -/* This is board specific information: IRQ routing for the +/* This is board specific information: IRQ routing for the * 0:1e.0 PCI bridge of the ICH7 */ diff --git a/src/mainboard/roda/rk886ex/acpi/mainboard.asl b/src/mainboard/roda/rk886ex/acpi/mainboard.asl index 7a2dea76a2..4be20c3ed8 100644 --- a/src/mainboard/roda/rk886ex/acpi/mainboard.asl +++ b/src/mainboard/roda/rk886ex/acpi/mainboard.asl @@ -36,7 +36,7 @@ Device (SLPB) Device (PWRB) { Name(_HID, EisaId("PNP0C0C")) - + // Wake Name(_PRW, Package(){0x1d, 0x04}) } diff --git a/src/mainboard/roda/rk886ex/acpi/platform.asl b/src/mainboard/roda/rk886ex/acpi/platform.asl index 9e86d0b7a7..5de4a83324 100644 --- a/src/mainboard/roda/rk886ex/acpi/platform.asl +++ b/src/mainboard/roda/rk886ex/acpi/platform.asl @@ -48,9 +48,9 @@ Method(TRAP, 1, Serialized) Return (SMIF) // Return value of SMI handler } -/* The _PIC method is called by the OS to choose between interrupt +/* The _PIC method is called by the OS to choose between interrupt * routing via the i8259 interrupt controller or the APIC. - * + * * _PIC is called with a parameter of 0 for i8259 configuration and * with a parameter of 1 for Local Apic/IOAPIC configuration. */ @@ -80,12 +80,12 @@ Method(_WAK,1) // Notify PCI Express slots in case a card // was inserted while a sleep state was active. - // Are we going to S3? + // Are we going to S3? If (LEqual(Arg0, 3)) { // .. } - // Are we going to S4? + // Are we going to S4? If (LEqual(Arg0, 4)) { // .. } diff --git a/src/mainboard/roda/rk886ex/acpi/superio.asl b/src/mainboard/roda/rk886ex/acpi/superio.asl index 67ff1f91f7..31cb44ad64 100644 --- a/src/mainboard/roda/rk886ex/acpi/superio.asl +++ b/src/mainboard/roda/rk886ex/acpi/superio.asl @@ -138,7 +138,7 @@ Device (SIO1) CreateByteField(RSRC, 0x05, IORH) // Why? CreateByteField(RSRC, \_SB.PCI0.LPCB.SIO1.COMA._CRS._IRA._INT, IRQL) - + Store (READ(0, 0x24, 0xff), Local0) And (Local0, 0xc0, Local1) ShiftRight(Local1, 0x06, Local1) @@ -297,7 +297,7 @@ Device (SIO1) CreateByteField(RSRC, 0x05, IORH) CreateByteField(RSRC, \_SB.PCI0.LPCB.SIO1.COMB._CRS._IRB._INT, IRQL) - + Store (READ(0, 0x25, 0xff), Local0) And (Local0, 0xc0, Local1) ShiftRight(Local1, 0x06, Local1) diff --git a/src/mainboard/roda/rk886ex/acpi/thermal.asl b/src/mainboard/roda/rk886ex/acpi/thermal.asl index cea3e8ea7b..b7efc53c3a 100644 --- a/src/mainboard/roda/rk886ex/acpi/thermal.asl +++ b/src/mainboard/roda/rk886ex/acpi/thermal.asl @@ -27,7 +27,7 @@ Scope (\_TZ) { // FIXME these could/should be read from the - // GNVS area, so they can be controlled by + // GNVS area, so they can be controlled by // coreboot Name(TC1V, 0x04) Name(TC2V, 0x03) diff --git a/src/mainboard/roda/rk886ex/acpi_tables.c b/src/mainboard/roda/rk886ex/acpi_tables.c index d89adf5e8b..00088f7b65 100644 --- a/src/mainboard/roda/rk886ex/acpi_tables.c +++ b/src/mainboard/roda/rk886ex/acpi_tables.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or @@ -161,7 +161,7 @@ unsigned long acpi_fill_madt(unsigned long current) MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE, 0x01); current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 1, MP_IRQ_POLARITY_HIGH | + current, 1, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE, 0x01); /* INT_SRC_OVR */ @@ -277,7 +277,7 @@ unsigned long write_acpi_tables(unsigned long start) current += dsdt->length; memcpy(dsdt, &AmlCode, dsdt->length); - /* Fix up global NVS region for SMI handler. The GNVS region lives + /* Fix up global NVS region for SMI handler. The GNVS region lives * in the (high) table area. The low memory map looks like this: * * 0x00000000 - 0x000003ff Real Mode IVT diff --git a/src/mainboard/roda/rk886ex/chip.h b/src/mainboard/roda/rk886ex/chip.h index 538f91425e..9fcb67fddb 100644 --- a/src/mainboard/roda/rk886ex/chip.h +++ b/src/mainboard/roda/rk886ex/chip.h @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify diff --git a/src/mainboard/roda/rk886ex/cmos.layout b/src/mainboard/roda/rk886ex/cmos.layout index 985aa14275..b5ae473ac6 100644 --- a/src/mainboard/roda/rk886ex/cmos.layout +++ b/src/mainboard/roda/rk886ex/cmos.layout @@ -1,6 +1,6 @@ # # This file is part of the coreboot project. -# +# # Copyright (C) 2007-2008 coresystems GmbH # # This program is free software; you can redistribute it and/or diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb index b578e19a55..9ce265955e 100644 --- a/src/mainboard/roda/rk886ex/devicetree.cb +++ b/src/mainboard/roda/rk886ex/devicetree.cb @@ -1,6 +1,6 @@ ## ## This file is part of the coreboot project. -## +## ## Copyright (C) 2007-2009 coresystems GmbH ## ## This program is free software; you can redistribute it and/or @@ -27,7 +27,7 @@ chip northbridge/intel/i945 end end - device pci_domain 0 on + device pci_domain 0 on device pci 00.0 on end # host bridge # auto detection: #device pci 01.0 off end # i945 PCIe root port @@ -79,7 +79,7 @@ chip northbridge/intel/i945 device pci 3.3 off end # smartcard end end # PCI bridge - #device pci 1e.2 off end # AC'97 Audio + #device pci 1e.2 off end # AC'97 Audio #device pci 1e.3 off end # AC'97 Modem device pci 1f.0 on # LPC bridge chip superio/smsc/lpc47n227 diff --git a/src/mainboard/roda/rk886ex/dsdt.asl b/src/mainboard/roda/rk886ex/dsdt.asl index 67539cce53..593b8d351f 100644 --- a/src/mainboard/roda/rk886ex/dsdt.asl +++ b/src/mainboard/roda/rk886ex/dsdt.asl @@ -36,7 +36,7 @@ DefinitionBlock( // General Purpose Events #include "acpi/gpe.asl" - + // mainboard specific devices #include "acpi/mainboard.asl" diff --git a/src/mainboard/roda/rk886ex/ec.c b/src/mainboard/roda/rk886ex/ec.c index f2d23ad6c5..4c39a8419e 100644 --- a/src/mainboard/roda/rk886ex/ec.c +++ b/src/mainboard/roda/rk886ex/ec.c @@ -35,7 +35,7 @@ int send_ec_command(u8 command) printk(BIOS_SPEW, "."); } if (!timeout) { - printk(BIOS_DEBUG, "Timeout while sending command 0x%02x to EC!\n", + printk(BIOS_DEBUG, "Timeout while sending command 0x%02x to EC!\n", command); // return -1; } diff --git a/src/mainboard/roda/rk886ex/m3885.c b/src/mainboard/roda/rk886ex/m3885.c index 62752e9065..5173ecfd39 100644 --- a/src/mainboard/roda/rk886ex/m3885.c +++ b/src/mainboard/roda/rk886ex/m3885.c @@ -54,7 +54,7 @@ static u8 variables[] = { 0x1e, 0xff, 0x87, // FuncKey Task = c5 Command Data (funcTsk) 0x1f, 0xff, 0x9f, // Delayed Task = c5 Command Data (dlyTsk1) 0x20, 0xff, 0x9f, // Wake-Up Task = c5 Command Data (wakeTsk) - // + // 0x21, 0xff, 0x08, // WigglePin Pulse Width * 2.4ms (tmPulse) 0x24, 0xff, 0x30, // Keyboard State Flags (kState7) // @@ -121,7 +121,7 @@ static int send_kbd_command(u8 command) printk(BIOS_SPEW, "."); } if (!timeout) { - printk(BIOS_DEBUG, "Timeout while sending command 0x%02x to EC!\n", + printk(BIOS_DEBUG, "Timeout while sending command 0x%02x to EC!\n", command); // return -1; } @@ -249,7 +249,7 @@ void m3885_configure_multikey(void) m3885_set_proc_ram(i + 0x80, matrix[i]); } - + /* ram bank 2 */ m3885_set_variable(0x0c, (kstate5_flags & (~(7 << 4))) | (2 << 4)); @@ -303,7 +303,7 @@ void m3885_configure_multikey(void) /* Critical Task */ m3885_set_proc_ram(0xf3, 0x5d); - + /* Thermal Polling Period */ m3885_set_proc_ram(0xf9, 0x0a); @@ -316,21 +316,21 @@ void m3885_configure_multikey(void) else reg8 = 0x9a; m3885_set_proc_ram(0xd0, reg8); // P60SPEC - + /* SENSE1# */ if (m3885_read_port() & (1 << 2)) reg8 = 0x8a; else reg8 = 0x9a; m3885_set_proc_ram(0xd2, reg8); // P62SPEC - + /* SENSE2# */ if (m3885_read_port() & (1 << 3)) reg8 = 0x8a; else reg8 = 0x9a; m3885_set_proc_ram(0xd3, reg8); // P63SPEC - + /* Low Active Port */ m3885_set_proc_ram(0xd1, 0x88); // P61SPEC m3885_set_proc_ram(0xd6, 0x88); // P66SPEC diff --git a/src/mainboard/roda/rk886ex/mainboard.c b/src/mainboard/roda/rk886ex/mainboard.c index f23a15932e..acfdfaa67b 100644 --- a/src/mainboard/roda/rk886ex/mainboard.c +++ b/src/mainboard/roda/rk886ex/mainboard.c @@ -114,7 +114,7 @@ static void dump_runtime_registers(void) } #endif -static void mainboard_enable(device_t dev) +static void mainboard_enable(device_t dev) { /* Configure the MultiKey controller */ // m3885_configure_multikey(); diff --git a/src/mainboard/roda/rk886ex/mainboard_smi.c b/src/mainboard/roda/rk886ex/mainboard_smi.c index 947f642802..a87d99da47 100644 --- a/src/mainboard/roda/rk886ex/mainboard_smi.c +++ b/src/mainboard/roda/rk886ex/mainboard_smi.c @@ -25,7 +25,7 @@ #include <cpu/x86/smm.h> #include "../../../southbridge/intel/i82801gx/i82801gx_nvs.h" -/* The southbridge SMI handler checks whether gnvs has a +/* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler */ extern global_nvs_t *gnvs; diff --git a/src/mainboard/roda/rk886ex/mptable.c b/src/mainboard/roda/rk886ex/mptable.c index c9de525d11..027be50b99 100644 --- a/src/mainboard/roda/rk886ex/mptable.c +++ b/src/mainboard/roda/rk886ex/mptable.c @@ -71,7 +71,7 @@ static void *smp_write_config_table(void *v) /* Legacy Interrupts */ - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, 0x2, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x1, 0x2, 0x1); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, 0x2, 0x2); diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index c888871e5f..044107cd5a 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or @@ -184,7 +184,7 @@ static void rcba_config(void) RCBA32(0x3400) = (1 << 2); /* Disable unused devices */ - RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE3 | FD_PCIE2 | + RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE3 | FD_PCIE2 | FD_INTLAN | FD_ACMOD | FD_HDAUD | FD_PATA; RCBA32(0x3418) |= (1 << 0); // Required. @@ -266,7 +266,7 @@ static void init_artec_dongle(void) #include <cbmem.h> // Now, this needs to be included because it relies on the symbol -// __PRE_RAM__ being set during CAR stage (in order to compile the +// __PRE_RAM__ being set during CAR stage (in order to compile the // BSS free versions of the functions). Either rewrite the code // to be always BSS free, or invent a flag that's better suited than // __PRE_RAM__ to determine whether we're in ram init stage (stage 1) @@ -330,7 +330,7 @@ void main(unsigned long bist) /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); - + #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 dump_spd_registers(); #endif @@ -340,8 +340,8 @@ void main(unsigned long bist) /* Perform some initialization that must run before stage2 */ early_ich7_init(); - /* This should probably go away. Until now it is required - * and mainboard specific + /* This should probably go away. Until now it is required + * and mainboard specific */ rcba_config(); @@ -385,7 +385,7 @@ void main(unsigned long bist) * memory completely, but that's a wonderful clean up task for another * day. */ - if (resume_backup_memory) + if (resume_backup_memory) memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE); /* Magic for S3 resume */ diff --git a/src/mainboard/roda/rk886ex/rtl8168.c b/src/mainboard/roda/rk886ex/rtl8168.c index e278bcfb4e..04fd56ccb1 100644 --- a/src/mainboard/roda/rk886ex/rtl8168.c +++ b/src/mainboard/roda/rk886ex/rtl8168.c @@ -28,7 +28,7 @@ static void nic_init(struct device *dev) { printk(BIOS_DEBUG, "Initializing RTL8168 Gigabit Ethernet\n"); - // Nothing to do yet, but this has to be here to keep + // Nothing to do yet, but this has to be here to keep // coreboot from trying to execute an option ROM. } diff --git a/src/mainboard/soyo/Kconfig b/src/mainboard/soyo/Kconfig index bb20b7475a..224e9a7409 100644 --- a/src/mainboard/soyo/Kconfig +++ b/src/mainboard/soyo/Kconfig @@ -21,7 +21,7 @@ choice prompt "Mainboard model" depends on VENDOR_SOYO - + source "src/mainboard/soyo/sy-6ba-plus-iii/Kconfig" endchoice diff --git a/src/mainboard/sunw/Kconfig b/src/mainboard/sunw/Kconfig index b04d9053c0..8a42be7414 100644 --- a/src/mainboard/sunw/Kconfig +++ b/src/mainboard/sunw/Kconfig @@ -1,7 +1,7 @@ choice prompt "Mainboard model" depends on VENDOR_SUNW - + source "src/mainboard/sunw/ultra40/Kconfig" endchoice diff --git a/src/mainboard/sunw/ultra40/devicetree.cb b/src/mainboard/sunw/ultra40/devicetree.cb index afa6f66beb..e7917495b7 100644 --- a/src/mainboard/sunw/ultra40/devicetree.cb +++ b/src/mainboard/sunw/ultra40/devicetree.cb @@ -7,9 +7,9 @@ chip northbridge/amd/amdk8/root_complex device pci_domain 0 on chip northbridge/amd/amdk8 #mc0 device pci 18.0 on end # link 0 - device pci 18.0 on # link1 - # devices on link 0, link 0 == LDT 0 - chip southbridge/nvidia/ck804 + device pci 18.0 on # link1 + # devices on link 0, link 0 == LDT 0 + chip southbridge/nvidia/ck804 device pci 0.0 on end # HT device pci 1.0 on # LPC chip superio/smsc/lpc47m10x @@ -40,29 +40,29 @@ chip northbridge/amd/amdk8/root_complex end device pci 1.1 on # SM 0 chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end + device i2c 50 on end + end chip drivers/generic/generic #dimm 0-0-1 device i2c 51 on end - end + end chip drivers/generic/generic #dimm 0-1-0 device i2c 52 on end - end + end chip drivers/generic/generic #dimm 0-1-1 device i2c 53 on end - end + end chip drivers/generic/generic #dimm 1-0-0 device i2c 54 on end - end + end chip drivers/generic/generic #dimm 1-0-1 device i2c 55 on end - end + end chip drivers/generic/generic #dimm 1-1-0 device i2c 56 on end - end + end chip drivers/generic/generic #dimm 1-1-1 device i2c 57 on end - end + end end # SM device pci 1.1 on # SM 1 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? @@ -71,24 +71,24 @@ chip northbridge/amd/amdk8/root_complex # end # chip drivers/generic/generic #PCIXB Slot1 # device i2c 51 on end -# end +# end # chip drivers/generic/generic #PCIXB Slot2 # device i2c 52 on end -# end +# end # chip drivers/generic/generic #PCI Slot1 # device i2c 53 on end -# end +# end # chip drivers/generic/generic #Master CK804 PCI-E # device i2c 54 on end -# end +# end # chip drivers/generic/generic #Slave CK804 PCI-E # device i2c 55 on end -# end +# end chip drivers/generic/generic #MAC EEPROM device i2c 51 on end - end + end - end # SM + end # SM device pci 2.0 on end # USB 1.1 device pci 2.1 on end # USB 2 device pci 4.0 on end # ACI @@ -109,18 +109,18 @@ chip northbridge/amd/amdk8/root_complex register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_addr" = "0x51" end - end # device pci 18.0 + end # device pci 18.0 device pci 18.0 on end # link 2 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end end # mc0 - + chip northbridge/amd/amdk8 device pci 19.0 on end # link 0 - device pci 19.0 on + device pci 19.0 on # devices on link 1, link 1 == LDT 1 - chip southbridge/nvidia/ck804 + chip southbridge/nvidia/ck804 device pci 0.0 on end # HT device pci 1.0 on end # LPC device pci 1.1 off end # SM @@ -140,13 +140,13 @@ chip northbridge/amd/amdk8/root_complex register "mac_eeprom_smbus" = "3" register "mac_eeprom_addr" = "0x51" end - end # device pci 19.0 - + end # device pci 19.0 + device pci 19.0 on end device pci 19.1 on end device pci 19.2 on end device pci 19.3 on end end end # PCI domain - + end #root_complex diff --git a/src/mainboard/sunw/ultra40/get_bus_conf.c b/src/mainboard/sunw/ultra40/get_bus_conf.c index 53162da97f..8309c8a10f 100644 --- a/src/mainboard/sunw/ultra40/get_bus_conf.c +++ b/src/mainboard/sunw/ultra40/get_bus_conf.c @@ -34,7 +34,7 @@ unsigned apicid_ck804b; unsigned sblk; -unsigned pci1234[] = +unsigned pci1234[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail 0x0000ff0, @@ -48,7 +48,7 @@ unsigned pci1234[] = }; unsigned hc_possible_num; unsigned sbdn; -unsigned hcdn[] = +unsigned hcdn[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, 0x20202020, @@ -77,10 +77,10 @@ void get_bus_conf(void) get_bus_conf_done = 1; - hc_possible_num = ARRAY_SIZE(pci1234); - + hc_possible_num = ARRAY_SIZE(pci1234); + get_sblk_pci1234(); - + sbdn = (hcdn[0] & 0xff); // first byte of first chain sbdn3 = (hcdn[1] & 0xff); @@ -262,8 +262,8 @@ void get_bus_conf(void) /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS==1 apicid_base = get_apicid_base(4); -#else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; +#else + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif apicid_ck804 = apicid_base+0; apicid_8131_1 = apicid_base+1; diff --git a/src/mainboard/sunw/ultra40/irq_tables.c b/src/mainboard/sunw/ultra40/irq_tables.c index 2bbbe7b110..324c87d995 100644 --- a/src/mainboard/sunw/ultra40/irq_tables.c +++ b/src/mainboard/sunw/ultra40/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up @@ -11,11 +11,11 @@ #include <arch/pirq_routing.h> #include <cpu/amd/amdk8_sysconf.h> -static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, +static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; + pirq_info->bus = bus; pirq_info->devfn = devfn; pirq_info->irq[0].link = link0; pirq_info->irq[0].bitmap = bitmap0; @@ -76,15 +76,15 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq = (void *)(addr); v = (uint8_t *)(addr); - + pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - + pirq->rtr_bus = bus_ck804_0; pirq->rtr_devfn = ((sbdn+9)<<3)|0; pirq->exclusive_irqs = 0; - + pirq->rtr_vendor = 0x10de; pirq->rtr_device = 0x005c; @@ -100,9 +100,9 @@ unsigned long write_pirq_routing_table(unsigned long addr) //pcix bridge write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; - - if(pci1234[2] & 0xf) { - //second pci beidge + + if(pci1234[2] & 0xf) { + //second pci beidge write_pirq_info(pirq_info, bus_ck804b_0, ((sbdnb+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x0, 0); pirq_info++; slot_num++; } @@ -139,10 +139,10 @@ unsigned long write_pirq_routing_table(unsigned long addr) //Slot2 pci write_pirq_info(pirq_info, bus_ck804_1, (0x4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 2, 0); pirq_info++; slot_num++; -//nic +//nic write_pirq_info(pirq_info, bus_ck804b_0, ((sbdnb+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); pirq_info++; slot_num++; -//Slot3 PCIE x16 +//Slot3 PCIE x16 write_pirq_info(pirq_info, bus_ck804b_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 3, 0); pirq_info++; slot_num++; @@ -162,11 +162,11 @@ unsigned long write_pirq_routing_table(unsigned long addr) write_pirq_info(pirq_info, bus_8131_1, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 6, 0); pirq_info++; slot_num++; #endif - - pirq->size = 32 + 16 * slot_num; + + pirq->size = 32 + 16 * slot_num; for (i = 0; i < pirq->size; i++) - sum += v[i]; + sum += v[i]; sum = pirq->checksum - sum; diff --git a/src/mainboard/sunw/ultra40/mptable.c b/src/mainboard/sunw/ultra40/mptable.c index b019ffea13..be92616e2d 100644 --- a/src/mainboard/sunw/ultra40/mptable.c +++ b/src/mainboard/sunw/ultra40/mptable.c @@ -133,7 +133,7 @@ static void *smp_write_config_table(void *v) } } - + /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_ck804, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_ck804, 0x1); @@ -212,7 +212,7 @@ static void *smp_write_config_table(void *v) //Channel A of 8131 -//Slot 6 PCIX 133/100/66 +//Slot 6 PCIX 133/100/66 for(i=0;i<4;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|i, apicid_8131_1, (0+i)%4); //24 } diff --git a/src/mainboard/sunw/ultra40/resourcemap.c b/src/mainboard/sunw/ultra40/resourcemap.c index 726373093f..eae21b4817 100644 --- a/src/mainboard/sunw/ultra40/resourcemap.c +++ b/src/mainboard/sunw/ultra40/resourcemap.c @@ -145,7 +145,7 @@ static void setup_ultra40_resource_map(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, @@ -183,7 +183,7 @@ static void setup_ultra40_resource_map(void) * [31:25] Reserved */ PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000, - PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x01fff001, + PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x01fff001, PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, @@ -201,7 +201,7 @@ static void setup_ultra40_resource_map(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -209,7 +209,7 @@ static void setup_ultra40_resource_map(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033, diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c index de16a4481f..76822ce45d 100644 --- a/src/mainboard/sunw/ultra40/romstage.c +++ b/src/mainboard/sunw/ultra40/romstage.c @@ -6,7 +6,7 @@ #define SET_NB_CFG_54 1 #endif - + #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -55,7 +55,7 @@ static void sio_gpio_setup(void) unsigned value; /*Enable onboard scsi*/ - lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L + lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c); lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1))); } @@ -76,7 +76,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" /* tyan does not want the default */ -#include "resourcemap.c" +#include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" @@ -111,21 +111,21 @@ static void sio_setup(void) unsigned value; uint32_t dword; uint8_t byte; - + pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400); - + byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b); - byte |= 0x20; + byte |= 0x20; pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte); - + dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0); dword |= (1<<29)|(1<<0); pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword); - + lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE); - + value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77); - value &= 0xbf; + value &= 0xbf; lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value); } @@ -165,7 +165,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); - + /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/supermicro/Kconfig b/src/mainboard/supermicro/Kconfig index f44677118c..1948784761 100644 --- a/src/mainboard/supermicro/Kconfig +++ b/src/mainboard/supermicro/Kconfig @@ -1,7 +1,7 @@ choice prompt "Mainboard model" depends on VENDOR_SUPERMICRO - + source "src/mainboard/supermicro/h8dme/Kconfig" source "src/mainboard/supermicro/h8dmr/Kconfig" source "src/mainboard/supermicro/h8dmr_fam10/Kconfig" diff --git a/src/mainboard/supermicro/h8dme/ap_romstage.c b/src/mainboard/supermicro/h8dme/ap_romstage.c index 60dd1b275e..3454cae313 100644 --- a/src/mainboard/supermicro/h8dme/ap_romstage.c +++ b/src/mainboard/supermicro/h8dme/ap_romstage.c @@ -25,7 +25,7 @@ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 -#define SET_NB_CFG_54 1 +#define SET_NB_CFG_54 1 //used by raminit #define QRANK_DIMM_SUPPORT 1 diff --git a/src/mainboard/supermicro/h8dme/cmos.layout b/src/mainboard/supermicro/h8dme/cmos.layout index 9d37e2bba6..518f9458b6 100644 --- a/src/mainboard/supermicro/h8dme/cmos.layout +++ b/src/mainboard/supermicro/h8dme/cmos.layout @@ -1,23 +1,23 @@ -## +## ## This file is part of the coreboot project. -## +## ## Copyright (C) 2007 AMD ## Written by Yinghai Lu <yinghailu@amd.com> for AMD. -## +## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or ## (at your option) any later version. -## +## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. -## +## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## +## entries diff --git a/src/mainboard/supermicro/h8dme/devicetree.cb b/src/mainboard/supermicro/h8dme/devicetree.cb index 5d6776a3f2..f6f75efb65 100644 --- a/src/mainboard/supermicro/h8dme/devicetree.cb +++ b/src/mainboard/supermicro/h8dme/devicetree.cb @@ -8,9 +8,9 @@ chip northbridge/amd/amdk8/root_complex chip northbridge/amd/amdk8 #mc0 device pci 18.0 on end device pci 18.0 on end - device pci 18.0 on - # devices on link 0, link 0 == LDT 0 - chip southbridge/nvidia/mcp55 + device pci 18.0 on + # devices on link 0, link 0 == LDT 0 + chip southbridge/nvidia/mcp55 device pci 0.0 on end # HT device pci 1.0 on # LPC chip superio/winbond/w83627hf @@ -37,14 +37,14 @@ chip northbridge/amd/amdk8/root_complex irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # SFI + device pnp 2e.6 off # SFI io 0x62 = 0x100 end device pnp 2e.7 off # GPIO_GAME_MIDI io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 - end + end device pnp 2e.8 off end # WDTO_PLED device pnp 2e.9 off end # GPIO_SUSLED device pnp 2e.a off end # ACPI @@ -67,24 +67,24 @@ chip northbridge/amd/amdk8/root_complex # end # chip drivers/generic/generic #PCIXB Slot1 # device i2c 51 on end -# end +# end # chip drivers/generic/generic #PCIXB Slot2 # device i2c 52 on end -# end +# end # chip drivers/generic/generic #PCI Slot1 # device i2c 53 on end -# end +# end # chip drivers/generic/generic #Master MCP55 PCI-E # device i2c 54 on end -# end +# end # chip drivers/generic/generic #Slave MCP55 PCI-E # device i2c 55 on end -# end +# end chip drivers/generic/generic #MAC EEPROM device i2c 51 on end end - end # SM + end # SM device pci 2.0 on end # USB 1.1 device pci 2.1 on end # USB 2 device pci 4.0 on end # IDE @@ -116,15 +116,15 @@ chip northbridge/amd/amdk8/root_complex register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_addr" = "0x51" end - end # device pci 18.0 + end # device pci 18.0 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end end # mc0 - + end # PCI domain - -# chip drivers/generic/debug + +# chip drivers/generic/debug # device pnp 0.0 off end # chip name # device pnp 0.1 on end # pci_regs_all # device pnp 0.2 off end # mem @@ -135,5 +135,5 @@ chip northbridge/amd/amdk8/root_complex # device pnp 0.7 off end # tsc # device pnp 0.8 off end # io # device pnp 0.9 on end # io -# end +# end end #root_complex diff --git a/src/mainboard/supermicro/h8dme/get_bus_conf.c b/src/mainboard/supermicro/h8dme/get_bus_conf.c index 3a9218ba6c..5052f35d7b 100644 --- a/src/mainboard/supermicro/h8dme/get_bus_conf.c +++ b/src/mainboard/supermicro/h8dme/get_bus_conf.c @@ -40,7 +40,7 @@ unsigned char bus_pcix[3]; // under bus_mcp55_2 -unsigned pci1234x[] = +unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail 0x0000ff0, @@ -52,7 +52,7 @@ unsigned pci1234x[] = // 0x0000ff0, // 0x0000ff0 }; -unsigned hcdnx[] = +unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, 0x20202020, @@ -98,7 +98,7 @@ void get_bus_conf(void) for(i=0; i<8; i++) { bus_mcp55[i] = 0; } - + for(i=0; i<3; i++) { bus_pcix[i] = 0; } @@ -142,13 +142,13 @@ void get_bus_conf(void) } } } - + /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS==1 apicid_base = get_apicid_base(1); -#else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; +#else + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif apicid_mcp55 = apicid_base+0; diff --git a/src/mainboard/supermicro/h8dme/irq_tables.c b/src/mainboard/supermicro/h8dme/irq_tables.c index 5cb6d8420c..bc6aded97f 100644 --- a/src/mainboard/supermicro/h8dme/irq_tables.c +++ b/src/mainboard/supermicro/h8dme/irq_tables.c @@ -19,7 +19,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up @@ -33,11 +33,11 @@ #include <cpu/amd/amdk8_sysconf.h> -static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, +static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; + pirq_info->bus = bus; pirq_info->devfn = devfn; pirq_info->irq[0].link = link0; pirq_info->irq[0].bitmap = bitmap0; @@ -79,15 +79,15 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq = (void *)(addr); v = (uint8_t *)(addr); - + pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - + pirq->rtr_bus = bus_mcp55[0]; pirq->rtr_devfn = ((sbdn+6)<<3)|0; pirq->exclusive_irqs = 0; - + pirq->rtr_vendor = 0x10de; pirq->rtr_device = 0x0370; @@ -100,11 +100,11 @@ unsigned long write_pirq_routing_table(unsigned long addr) //pci bridge write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; - - pirq->size = 32 + 16 * slot_num; + + pirq->size = 32 + 16 * slot_num; for (i = 0; i < pirq->size; i++) - sum += v[i]; + sum += v[i]; sum = pirq->checksum - sum; diff --git a/src/mainboard/supermicro/h8dme/mptable.c b/src/mainboard/supermicro/h8dme/mptable.c index c7e46f2bda..8146923ef7 100644 --- a/src/mainboard/supermicro/h8dme/mptable.c +++ b/src/mainboard/supermicro/h8dme/mptable.c @@ -102,7 +102,7 @@ static void *smp_write_config_table(void *v) } - + /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_mcp55, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_mcp55, 0x1); @@ -144,9 +144,9 @@ static void *smp_write_config_table(void *v) } - if(bus_pcix[0]) { + if(bus_pcix[0]) { for(i=0;i<2;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[2], (4<<2)|i, apicid_mcp55, 0x10 + (0+i+4-sbdn%4)%4); //16, 17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[2], (4<<2)|i, apicid_mcp55, 0x10 + (0+i+4-sbdn%4)%4); //16, 17 } for(i=0;i<4;i++) { diff --git a/src/mainboard/supermicro/h8dme/resourcemap.c b/src/mainboard/supermicro/h8dme/resourcemap.c index fa22ee337b..db5d5fe185 100644 --- a/src/mainboard/supermicro/h8dme/resourcemap.c +++ b/src/mainboard/supermicro/h8dme/resourcemap.c @@ -161,7 +161,7 @@ static void setup_mb_resource_map(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, @@ -217,7 +217,7 @@ static void setup_mb_resource_map(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -225,7 +225,7 @@ static void setup_mb_resource_map(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033, @@ -270,9 +270,9 @@ static void setup_mb_resource_map(void) * This field defines the highest bus number in configuration region i */ PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of cpu 0 --> Nvidia MCP55 Pro */ - PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, }; diff --git a/src/mainboard/supermicro/h8dmr/ap_romstage.c b/src/mainboard/supermicro/h8dmr/ap_romstage.c index 60dd1b275e..3454cae313 100644 --- a/src/mainboard/supermicro/h8dmr/ap_romstage.c +++ b/src/mainboard/supermicro/h8dmr/ap_romstage.c @@ -25,7 +25,7 @@ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 -#define SET_NB_CFG_54 1 +#define SET_NB_CFG_54 1 //used by raminit #define QRANK_DIMM_SUPPORT 1 diff --git a/src/mainboard/supermicro/h8dmr/cmos.layout b/src/mainboard/supermicro/h8dmr/cmos.layout index 9d37e2bba6..518f9458b6 100644 --- a/src/mainboard/supermicro/h8dmr/cmos.layout +++ b/src/mainboard/supermicro/h8dmr/cmos.layout @@ -1,23 +1,23 @@ -## +## ## This file is part of the coreboot project. -## +## ## Copyright (C) 2007 AMD ## Written by Yinghai Lu <yinghailu@amd.com> for AMD. -## +## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or ## (at your option) any later version. -## +## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. -## +## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## +## entries diff --git a/src/mainboard/supermicro/h8dmr/devicetree.cb b/src/mainboard/supermicro/h8dmr/devicetree.cb index d83f00637d..67920c4657 100644 --- a/src/mainboard/supermicro/h8dmr/devicetree.cb +++ b/src/mainboard/supermicro/h8dmr/devicetree.cb @@ -8,9 +8,9 @@ chip northbridge/amd/amdk8/root_complex chip northbridge/amd/amdk8 #mc0 device pci 18.0 on end device pci 18.0 on end - device pci 18.0 on - # devices on link 0, link 0 == LDT 0 - chip southbridge/nvidia/mcp55 + device pci 18.0 on + # devices on link 0, link 0 == LDT 0 + chip southbridge/nvidia/mcp55 device pci 0.0 on end # HT device pci 1.0 on # LPC chip superio/winbond/w83627hf @@ -37,14 +37,14 @@ chip northbridge/amd/amdk8/root_complex irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # SFI + device pnp 2e.6 off # SFI io 0x62 = 0x100 end device pnp 2e.7 off # GPIO_GAME_MIDI io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 - end + end device pnp 2e.8 off end # WDTO_PLED device pnp 2e.9 off end # GPIO_SUSLED device pnp 2e.a off end # ACPI @@ -56,29 +56,29 @@ chip northbridge/amd/amdk8/root_complex end device pci 1.1 on # SM 0 chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end + device i2c 50 on end + end chip drivers/generic/generic #dimm 0-0-1 device i2c 51 on end - end + end chip drivers/generic/generic #dimm 0-1-0 device i2c 52 on end - end + end chip drivers/generic/generic #dimm 0-1-1 device i2c 53 on end - end + end chip drivers/generic/generic #dimm 1-0-0 device i2c 54 on end - end + end chip drivers/generic/generic #dimm 1-0-1 device i2c 55 on end - end + end chip drivers/generic/generic #dimm 1-1-0 device i2c 56 on end - end + end chip drivers/generic/generic #dimm 1-1-1 device i2c 57 on end - end + end end # SM device pci 1.1 on # SM 1 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? @@ -87,24 +87,24 @@ chip northbridge/amd/amdk8/root_complex # end # chip drivers/generic/generic #PCIXB Slot1 # device i2c 51 on end -# end +# end # chip drivers/generic/generic #PCIXB Slot2 # device i2c 52 on end -# end +# end # chip drivers/generic/generic #PCI Slot1 # device i2c 53 on end -# end +# end # chip drivers/generic/generic #Master MCP55 PCI-E # device i2c 54 on end -# end +# end # chip drivers/generic/generic #Slave MCP55 PCI-E # device i2c 55 on end -# end +# end chip drivers/generic/generic #MAC EEPROM device i2c 51 on end - end + end - end # SM + end # SM device pci 2.0 on end # USB 1.1 device pci 2.1 on end # USB 2 device pci 4.0 on end # IDE @@ -136,15 +136,15 @@ chip northbridge/amd/amdk8/root_complex register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_addr" = "0x51" end - end # device pci 18.0 + end # device pci 18.0 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end end # mc0 - + end # PCI domain - -# chip drivers/generic/debug + +# chip drivers/generic/debug # device pnp 0.0 off end # chip name # device pnp 0.1 on end # pci_regs_all # device pnp 0.2 off end # mem @@ -155,5 +155,5 @@ chip northbridge/amd/amdk8/root_complex # device pnp 0.7 off end # tsc # device pnp 0.8 off end # io # device pnp 0.9 on end # io -# end +# end end #root_complex diff --git a/src/mainboard/supermicro/h8dmr/get_bus_conf.c b/src/mainboard/supermicro/h8dmr/get_bus_conf.c index 3a9218ba6c..5052f35d7b 100644 --- a/src/mainboard/supermicro/h8dmr/get_bus_conf.c +++ b/src/mainboard/supermicro/h8dmr/get_bus_conf.c @@ -40,7 +40,7 @@ unsigned char bus_pcix[3]; // under bus_mcp55_2 -unsigned pci1234x[] = +unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail 0x0000ff0, @@ -52,7 +52,7 @@ unsigned pci1234x[] = // 0x0000ff0, // 0x0000ff0 }; -unsigned hcdnx[] = +unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, 0x20202020, @@ -98,7 +98,7 @@ void get_bus_conf(void) for(i=0; i<8; i++) { bus_mcp55[i] = 0; } - + for(i=0; i<3; i++) { bus_pcix[i] = 0; } @@ -142,13 +142,13 @@ void get_bus_conf(void) } } } - + /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS==1 apicid_base = get_apicid_base(1); -#else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; +#else + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif apicid_mcp55 = apicid_base+0; diff --git a/src/mainboard/supermicro/h8dmr/irq_tables.c b/src/mainboard/supermicro/h8dmr/irq_tables.c index 5cb6d8420c..bc6aded97f 100644 --- a/src/mainboard/supermicro/h8dmr/irq_tables.c +++ b/src/mainboard/supermicro/h8dmr/irq_tables.c @@ -19,7 +19,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up @@ -33,11 +33,11 @@ #include <cpu/amd/amdk8_sysconf.h> -static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, +static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; + pirq_info->bus = bus; pirq_info->devfn = devfn; pirq_info->irq[0].link = link0; pirq_info->irq[0].bitmap = bitmap0; @@ -79,15 +79,15 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq = (void *)(addr); v = (uint8_t *)(addr); - + pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - + pirq->rtr_bus = bus_mcp55[0]; pirq->rtr_devfn = ((sbdn+6)<<3)|0; pirq->exclusive_irqs = 0; - + pirq->rtr_vendor = 0x10de; pirq->rtr_device = 0x0370; @@ -100,11 +100,11 @@ unsigned long write_pirq_routing_table(unsigned long addr) //pci bridge write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; - - pirq->size = 32 + 16 * slot_num; + + pirq->size = 32 + 16 * slot_num; for (i = 0; i < pirq->size; i++) - sum += v[i]; + sum += v[i]; sum = pirq->checksum - sum; diff --git a/src/mainboard/supermicro/h8dmr/mptable.c b/src/mainboard/supermicro/h8dmr/mptable.c index c7e46f2bda..8146923ef7 100644 --- a/src/mainboard/supermicro/h8dmr/mptable.c +++ b/src/mainboard/supermicro/h8dmr/mptable.c @@ -102,7 +102,7 @@ static void *smp_write_config_table(void *v) } - + /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_mcp55, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_mcp55, 0x1); @@ -144,9 +144,9 @@ static void *smp_write_config_table(void *v) } - if(bus_pcix[0]) { + if(bus_pcix[0]) { for(i=0;i<2;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[2], (4<<2)|i, apicid_mcp55, 0x10 + (0+i+4-sbdn%4)%4); //16, 17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[2], (4<<2)|i, apicid_mcp55, 0x10 + (0+i+4-sbdn%4)%4); //16, 17 } for(i=0;i<4;i++) { diff --git a/src/mainboard/supermicro/h8dmr/resourcemap.c b/src/mainboard/supermicro/h8dmr/resourcemap.c index fa22ee337b..db5d5fe185 100644 --- a/src/mainboard/supermicro/h8dmr/resourcemap.c +++ b/src/mainboard/supermicro/h8dmr/resourcemap.c @@ -161,7 +161,7 @@ static void setup_mb_resource_map(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, @@ -217,7 +217,7 @@ static void setup_mb_resource_map(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -225,7 +225,7 @@ static void setup_mb_resource_map(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033, @@ -270,9 +270,9 @@ static void setup_mb_resource_map(void) * This field defines the highest bus number in configuration region i */ PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of cpu 0 --> Nvidia MCP55 Pro */ - PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, }; diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index fd0634ff62..3ef91c82bb 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -37,7 +37,7 @@ #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif - + #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -98,7 +98,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" -#include "resourcemap.c" +#include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" @@ -129,13 +129,13 @@ static void sio_setup(void) smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */ byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); - byte |= 0x20; + byte |= 0x20; pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); - + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); dword |= (1<<0); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); - + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); dword |= (1<<16); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); @@ -181,7 +181,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) uart_init(); console_init(); - + /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/supermicro/h8dmr_fam10/cmos.layout b/src/mainboard/supermicro/h8dmr_fam10/cmos.layout index 9d37e2bba6..518f9458b6 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/cmos.layout +++ b/src/mainboard/supermicro/h8dmr_fam10/cmos.layout @@ -1,23 +1,23 @@ -## +## ## This file is part of the coreboot project. -## +## ## Copyright (C) 2007 AMD ## Written by Yinghai Lu <yinghailu@amd.com> for AMD. -## +## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or ## (at your option) any later version. -## +## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. -## +## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## +## entries diff --git a/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb b/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb index 8d8936c92f..c142dcb290 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb +++ b/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb @@ -8,9 +8,9 @@ chip northbridge/amd/amdfam10/root_complex chip northbridge/amd/amdfam10 #mc0 device pci 18.0 on end device pci 18.0 on end - device pci 18.0 on + device pci 18.0 on # SB on link 2.0 - chip southbridge/nvidia/mcp55 + chip southbridge/nvidia/mcp55 device pci 0.0 on end # HT device pci 1.0 on # LPC chip superio/winbond/w83627hf @@ -37,14 +37,14 @@ chip northbridge/amd/amdfam10/root_complex irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # SFI + device pnp 2e.6 off # SFI io 0x62 = 0x100 end device pnp 2e.7 off # GPIO_GAME_MIDI io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 - end + end device pnp 2e.8 off end # WDTO_PLED device pnp 2e.9 off end # GPIO_SUSLED device pnp 2e.a off end # ACPI @@ -56,29 +56,29 @@ chip northbridge/amd/amdfam10/root_complex end device pci 1.1 on # SM 0 chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end + device i2c 50 on end + end chip drivers/generic/generic #dimm 0-0-1 device i2c 51 on end - end + end chip drivers/generic/generic #dimm 0-1-0 device i2c 52 on end - end + end chip drivers/generic/generic #dimm 0-1-1 device i2c 53 on end - end + end chip drivers/generic/generic #dimm 1-0-0 device i2c 54 on end - end + end chip drivers/generic/generic #dimm 1-0-1 device i2c 55 on end - end + end chip drivers/generic/generic #dimm 1-1-0 device i2c 56 on end - end + end chip drivers/generic/generic #dimm 1-1-1 device i2c 57 on end - end + end end # SM device pci 1.1 on # SM 1 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? @@ -87,24 +87,24 @@ chip northbridge/amd/amdfam10/root_complex # end # chip drivers/generic/generic #PCIXB Slot1 # device i2c 51 on end -# end +# end # chip drivers/generic/generic #PCIXB Slot2 # device i2c 52 on end -# end +# end # chip drivers/generic/generic #PCI Slot1 # device i2c 53 on end -# end +# end # chip drivers/generic/generic #Master MCP55 PCI-E # device i2c 54 on end -# end +# end # chip drivers/generic/generic #Slave MCP55 PCI-E # device i2c 55 on end -# end +# end chip drivers/generic/generic #MAC EEPROM device i2c 51 on end - end + end - end # SM + end # SM device pci 2.0 on end # USB 1.1 device pci 2.1 on end # USB 2 device pci 4.0 on end # IDE @@ -136,7 +136,7 @@ chip northbridge/amd/amdfam10/root_complex register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_addr" = "0x51" end - end # device pci 18.0 + end # device pci 18.0 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end @@ -147,10 +147,10 @@ chip northbridge/amd/amdfam10/root_complex device pci 19.3 on end device pci 19.4 on end end # mc0 - + end # PCI domain - -# chip drivers/generic/debug + +# chip drivers/generic/debug # device pnp 0.0 off end # chip name # device pnp 0.1 on end # pci_regs_all # device pnp 0.2 off end # mem @@ -161,5 +161,5 @@ chip northbridge/amd/amdfam10/root_complex # device pnp 0.7 off end # tsc # device pnp 0.8 off end # io # device pnp 0.9 on end # io -# end +# end end #root_complex diff --git a/src/mainboard/supermicro/h8dmr_fam10/irq_tables.c b/src/mainboard/supermicro/h8dmr_fam10/irq_tables.c index 673db742fb..a981fe1b9c 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/irq_tables.c +++ b/src/mainboard/supermicro/h8dmr_fam10/irq_tables.c @@ -19,7 +19,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! * (but if you do, please run checkpir on it to verify) * Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up @@ -34,11 +34,11 @@ #include <cpu/amd/amdfam10_sysconf.h> #include "mb_sysconf.h" -static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, +static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; + pirq_info->bus = bus; pirq_info->devfn = devfn; pirq_info->irq[0].link = link0; pirq_info->irq[0].bitmap = bitmap0; @@ -80,15 +80,15 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq = (void *)(addr); v = (uint8_t *)(addr); - + pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - + pirq->rtr_bus = m->bus_mcp55[0]; pirq->rtr_devfn = ((sbdn+6)<<3)|0; pirq->exclusive_irqs = 0; - + pirq->rtr_vendor = 0x10de; pirq->rtr_device = 0x0370; @@ -101,7 +101,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) //pci bridge write_pirq_info(pirq_info, m->bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; - + for(i=1; i< sysconf.hc_possible_num; i++) { if(!(sysconf.pci1234[i] & 0x1) ) continue; unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff; @@ -120,10 +120,10 @@ unsigned long write_pirq_routing_table(unsigned long addr) } #endif - pirq->size = 32 + 16 * slot_num; + pirq->size = 32 + 16 * slot_num; for (i = 0; i < pirq->size; i++) - sum += v[i]; + sum += v[i]; sum = pirq->checksum - sum; diff --git a/src/mainboard/supermicro/h8dmr_fam10/mb_sysconf.h b/src/mainboard/supermicro/h8dmr_fam10/mb_sysconf.h index 83f9dbab28..a2e6fc7ade 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/mb_sysconf.h +++ b/src/mainboard/supermicro/h8dmr_fam10/mb_sysconf.h @@ -26,7 +26,7 @@ struct mb_sysconf_t { unsigned char bus_isa; unsigned char bus_mcp55[8]; //1 unsigned apicid_mcp55; - unsigned bus_type[256]; + unsigned bus_type[256]; }; diff --git a/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c b/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c index 13ae166708..0aded2ccbd 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c +++ b/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c @@ -161,7 +161,7 @@ static void setup_mb_resource_map(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, @@ -218,7 +218,7 @@ static void setup_mb_resource_map(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -226,7 +226,7 @@ static void setup_mb_resource_map(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ // WARD CHANGED @@ -273,9 +273,9 @@ static void setup_mb_resource_map(void) */ // WARD CHANGED PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of cpu 0 --> Nvidia MCP55 Pro */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, }; diff --git a/src/mainboard/supermicro/h8qme_fam10/cmos.layout b/src/mainboard/supermicro/h8qme_fam10/cmos.layout index 9d37e2bba6..518f9458b6 100644 --- a/src/mainboard/supermicro/h8qme_fam10/cmos.layout +++ b/src/mainboard/supermicro/h8qme_fam10/cmos.layout @@ -1,23 +1,23 @@ -## +## ## This file is part of the coreboot project. -## +## ## Copyright (C) 2007 AMD ## Written by Yinghai Lu <yinghailu@amd.com> for AMD. -## +## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or ## (at your option) any later version. -## +## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. -## +## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## +## entries diff --git a/src/mainboard/supermicro/h8qme_fam10/devicetree.cb b/src/mainboard/supermicro/h8qme_fam10/devicetree.cb index 51c2feb000..5759f40ccf 100644 --- a/src/mainboard/supermicro/h8qme_fam10/devicetree.cb +++ b/src/mainboard/supermicro/h8qme_fam10/devicetree.cb @@ -8,9 +8,9 @@ chip northbridge/amd/amdfam10/root_complex chip northbridge/amd/amdfam10 #mc0 device pci 18.0 on end device pci 18.0 on end - device pci 18.0 on + device pci 18.0 on # SB on link 2.0 - chip southbridge/nvidia/mcp55 + chip southbridge/nvidia/mcp55 device pci 0.0 on end # HT device pci 1.0 on # LPC chip superio/winbond/w83627hf @@ -37,14 +37,14 @@ chip northbridge/amd/amdfam10/root_complex irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # SFI + device pnp 2e.6 off # SFI io 0x62 = 0x100 end device pnp 2e.7 off # GPIO_GAME_MIDI io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 - end + end device pnp 2e.8 off end # WDTO_PLED device pnp 2e.9 off end # GPIO_SUSLED device pnp 2e.a off end # ACPI @@ -57,12 +57,12 @@ chip northbridge/amd/amdfam10/root_complex device pci 1.1 on end device pci 1.1 on # SM 1 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? -# +# chip drivers/generic/generic #MAC EEPROM device i2c 51 on end - end + end - end # SM + end # SM device pci 2.0 on end # USB 1.1 device pci 2.1 on end # USB 2 device pci 4.0 on end # IDE @@ -70,7 +70,7 @@ chip northbridge/amd/amdfam10/root_complex device pci 5.1 on end # SATA 1 device pci 5.2 on end # SATA 2 device pci 6.1 off end # AZA - device pci 7.0 on + device pci 7.0 on device pci 1.0 on end end device pci 8.0 off end @@ -87,7 +87,7 @@ chip northbridge/amd/amdfam10/root_complex register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_addr" = "0x51" end - end # device pci 18.0 + end # device pci 18.0 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end @@ -110,10 +110,10 @@ chip northbridge/amd/amdfam10/root_complex device pci 19.3 on end device pci 19.4 on end end # mc0 - + end # PCI domain - -# chip drivers/generic/debug + +# chip drivers/generic/debug # device pnp 0.0 off end # chip name # device pnp 0.1 on end # pci_regs_all # device pnp 0.2 off end # mem @@ -124,5 +124,5 @@ chip northbridge/amd/amdfam10/root_complex # device pnp 0.7 off end # tsc # device pnp 0.8 off end # io # device pnp 0.9 on end # io -# end +# end end #root_complex diff --git a/src/mainboard/supermicro/h8qme_fam10/irq_tables.c b/src/mainboard/supermicro/h8qme_fam10/irq_tables.c index efaf4cb754..9338d5e08c 100644 --- a/src/mainboard/supermicro/h8qme_fam10/irq_tables.c +++ b/src/mainboard/supermicro/h8qme_fam10/irq_tables.c @@ -19,7 +19,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! * (but if you do, please run checkpir on it to verify) * Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up @@ -34,11 +34,11 @@ #include <cpu/amd/amdfam10_sysconf.h> #include "mb_sysconf.h" -static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, +static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; + pirq_info->bus = bus; pirq_info->devfn = devfn; pirq_info->irq[0].link = link0; pirq_info->irq[0].bitmap = bitmap0; @@ -80,15 +80,15 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq = (void *)(addr); v = (uint8_t *)(addr); - + pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - + pirq->rtr_bus = m->bus_mcp55[0]; pirq->rtr_devfn = ((sbdn+6)<<3)|0; pirq->exclusive_irqs = 0; - + pirq->rtr_vendor = 0x10de; pirq->rtr_device = 0x0364; @@ -101,7 +101,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) //pci bridge write_pirq_info(pirq_info, m->bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, 0x4ca0, 0x2, 0x4ca0, 0x3, 0x4ca0, 0x4, 0x4ca0, 0, 0); pirq_info++; slot_num++; - + for(i=1; i< sysconf.hc_possible_num; i++) { if(!(sysconf.pci1234[i] & 0x1) ) continue; unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff; @@ -120,10 +120,10 @@ unsigned long write_pirq_routing_table(unsigned long addr) } #endif - pirq->size = 32 + 16 * slot_num; + pirq->size = 32 + 16 * slot_num; for (i = 0; i < pirq->size; i++) - sum += v[i]; + sum += v[i]; sum = pirq->checksum - sum; diff --git a/src/mainboard/supermicro/h8qme_fam10/mb_sysconf.h b/src/mainboard/supermicro/h8qme_fam10/mb_sysconf.h index 42969bb71e..5a17fa9442 100644 --- a/src/mainboard/supermicro/h8qme_fam10/mb_sysconf.h +++ b/src/mainboard/supermicro/h8qme_fam10/mb_sysconf.h @@ -26,7 +26,7 @@ struct mb_sysconf_t { unsigned char bus_isa; unsigned char bus_mcp55[8]; //1 unsigned apicid_mcp55; - unsigned bus_type[256]; + unsigned bus_type[256]; unsigned char bus_8132_0; //7 unsigned char bus_8132_1; //8 diff --git a/src/mainboard/supermicro/h8qme_fam10/mptable.c b/src/mainboard/supermicro/h8qme_fam10/mptable.c index 551ee977fa..c365ddbe2d 100644 --- a/src/mainboard/supermicro/h8qme_fam10/mptable.c +++ b/src/mainboard/supermicro/h8qme_fam10/mptable.c @@ -100,33 +100,33 @@ static void *smp_write_config_table(void *v) } - + /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x1, m->apicid_mcp55, 0x1); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x2); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x3, m->apicid_mcp55, 0x3); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x4, m->apicid_mcp55, 0x4); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x6, m->apicid_mcp55, 0x6); + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x1, m->apicid_mcp55, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x3, m->apicid_mcp55, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x4, m->apicid_mcp55, 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x6, m->apicid_mcp55, 0x6); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x7, m->apicid_mcp55, 0x7); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x8, m->apicid_mcp55, 0x8); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xc, m->apicid_mcp55, 0xc); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xd, m->apicid_mcp55, 0xd); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xe, m->apicid_mcp55, 0xe); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xf, m->apicid_mcp55, 0xf); - - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0x5); /* 5 SMBus, OK */ + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0x5); /* 5 SMBus, OK */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0xb); /* 11 USB, OK */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0xa); /* 10 USB, OK */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x5); /* 5 IDE, OK*/ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0xa); /* 10 IDE, OK*/ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0xa); /* 10 IDE, OK*/ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0xa); /* 10 IDE, OK*/ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0xa); /* 10 IDE, OK*/ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+6)<<2)|1, m->apicid_mcp55, 0xa); /* 10 VGA, OK*/ - + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, ((3)<<2)|0, m->apicid_mcp55, 0x5); /* 5 eth0, OK*/ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, ((3)<<2)|1, m->apicid_mcp55, 0xb); /* 11 eth1, OK*/ - for(j=7;j>=2; j--) { + for(j=7;j>=2; j--) { if(!m->bus_mcp55[j]) continue; for(i=0;i<4;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); diff --git a/src/mainboard/supermicro/h8qme_fam10/resourcemap.c b/src/mainboard/supermicro/h8qme_fam10/resourcemap.c index 13ae166708..0aded2ccbd 100644 --- a/src/mainboard/supermicro/h8qme_fam10/resourcemap.c +++ b/src/mainboard/supermicro/h8qme_fam10/resourcemap.c @@ -161,7 +161,7 @@ static void setup_mb_resource_map(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, @@ -218,7 +218,7 @@ static void setup_mb_resource_map(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -226,7 +226,7 @@ static void setup_mb_resource_map(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ // WARD CHANGED @@ -273,9 +273,9 @@ static void setup_mb_resource_map(void) */ // WARD CHANGED PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of cpu 0 --> Nvidia MCP55 Pro */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, }; diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index aa2081f7df..0d1657a170 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -93,12 +93,12 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdfam10/raminit_amdmct.c" #include "northbridge/amd/amdfam10/amdfam10_pci.c" -#include "resourcemap.c" +#include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" #define MCP55_NUM 1 -#define MCP55_USE_NIC 0 +#define MCP55_USE_NIC 0 #define MCP55_USE_AZA 0 #define MCP55_PCI_E_X_0 4 @@ -128,13 +128,13 @@ static void sio_setup(void) smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */ byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); - byte |= 0x20; + byte |= 0x20; pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); - + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); dword |= (1<<0); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); - + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); dword |= (1<<16); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); @@ -206,7 +206,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } post_code(0x30); - + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } diff --git a/src/mainboard/supermicro/x6dai_g/debug.c b/src/mainboard/supermicro/x6dai_g/debug.c index b4f2a185b3..87c67b5964 100644 --- a/src/mainboard/supermicro/x6dai_g/debug.c +++ b/src/mainboard/supermicro/x6dai_g/debug.c @@ -5,7 +5,7 @@ static void print_reg(unsigned char index) { unsigned char data; - + outb(index, 0x2e); data = inb(0x2f); print_debug("0x"); @@ -15,7 +15,7 @@ static void print_reg(unsigned char index) print_debug("\n"); return; } - + static void xbus_en(void) { /* select the XBUS function in the SIO */ @@ -25,7 +25,7 @@ static void xbus_en(void) outb(0x01, 0x2f); return; } - + static void setup_func(unsigned char func) { /* select the function in the SIO */ @@ -43,27 +43,27 @@ static void setup_func(unsigned char func) print_reg(0x75); return; } - + static void siodump(void) { int i; unsigned char data; - + print_debug("\n*** SERVER I/O REGISTERS ***\n"); for (i=0x10; i<=0x2d; i++) { print_reg((unsigned char)i); } -#if 0 +#if 0 print_debug("\n*** XBUS REGISTERS ***\n"); setup_func(0x0f); for (i=0xf0; i<=0xff; i++) { print_reg((unsigned char)i); } - + print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); setup_func(0x03); print_reg(0xf0); - + print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); setup_func(0x02); print_reg(0xf0); @@ -82,13 +82,13 @@ static void siodump(void) print_debug("\nGPDI 4: 0x"); print_debug_hex8(data); print_debug("\n"); - -#if 0 - + +#if 0 + print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); setup_func(0x0a); print_reg(0xf0); - + print_debug("\n*** FAN CONTROL REGISTERS ***\n"); setup_func(0x09); print_reg(0xf0); @@ -103,11 +103,11 @@ static void siodump(void) print_reg(0xf7); print_reg(0xfe); print_reg(0xff); - + print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); setup_func(0x14); print_reg(0xf0); -#endif +#endif return; } @@ -124,8 +124,8 @@ static void print_debug_pci_dev(unsigned dev) static void print_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -144,7 +144,7 @@ static void dump_pci_device(unsigned dev) int i; print_debug_pci_dev(dev); print_debug("\n"); - + for(i = 0; i <= 255; i++) { unsigned char val; if ((i & 0x0f) == 0) { @@ -164,19 +164,19 @@ static void dump_bar14(unsigned dev) { int i; unsigned long bar; - + print_debug("BAR 14 Dump\n"); - + bar = pci_read_config32(dev, 0x14); for(i = 0; i <= 0x300; i+=4) { -#if 0 +#if 0 unsigned char val; if ((i & 0x0f) == 0) { print_debug_hex8(i); print_debug_char(':'); } val = pci_read_config8(dev, i); -#endif +#endif if((i%4)==0) { print_debug("\n"); print_debug_hex16(i); @@ -191,8 +191,8 @@ static void dump_bar14(unsigned dev) static void dump_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -215,8 +215,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel0[i]; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".0: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { @@ -241,8 +241,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel1[i]; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".1: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { @@ -278,7 +278,7 @@ void dump_spd_registers(void) print_debug("\n"); print_debug("dimm "); print_debug_hex8(device); - + for(i = 0; (i < 256) ; i++) { unsigned char byte; if ((i % 16) == 0) { @@ -291,7 +291,7 @@ void dump_spd_registers(void) print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); @@ -311,7 +311,7 @@ void dump_ipmi_registers(void) print_debug("\n"); print_debug("ipmi "); print_debug_hex8(device); - + for(i = 0; (i < 8) ; i++) { unsigned char byte; status = smbus_read_byte(device, 2); @@ -319,7 +319,7 @@ void dump_ipmi_registers(void) print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); @@ -327,4 +327,4 @@ void dump_ipmi_registers(void) device += SMBUS_MEM_DEVICE_INC; print_debug("\n"); } -} +} diff --git a/src/mainboard/supermicro/x6dai_g/devicetree.cb b/src/mainboard/supermicro/x6dai_g/devicetree.cb index 97176b9b78..038964e9ad 100644 --- a/src/mainboard/supermicro/x6dai_g/devicetree.cb +++ b/src/mainboard/supermicro/x6dai_g/devicetree.cb @@ -1,20 +1,20 @@ chip northbridge/intel/e7525 # mch device pci_domain 0 on - chip southbridge/intel/esb6300 # esb6300 + chip southbridge/intel/esb6300 # esb6300 register "pirq_a_d" = "0x0b0a0a05" register "pirq_e_h" = "0x0a0b0c80" - + device pci 1c.0 on end - + device pci 1d.0 on end device pci 1d.1 on end device pci 1d.4 on end device pci 1d.5 on end device pci 1d.7 on end - + device pci 1e.0 on end - - device pci 1f.0 on + + device pci 1f.0 on chip superio/winbond/w83627hf device pnp 2e.0 off end device pnp 2e.1 off end @@ -45,7 +45,7 @@ chip northbridge/intel/e7525 # mch device pci 1f.6 on end end device pci 00.0 on end - device pci 00.1 on end + device pci 00.1 on end device pci 00.2 on end device pci 02.0 on end device pci 03.0 on end diff --git a/src/mainboard/supermicro/x6dai_g/mptable.c b/src/mainboard/supermicro/x6dai_g/mptable.c index a3bb398fa2..a0c863cb45 100644 --- a/src/mainboard/supermicro/x6dai_g/mptable.c +++ b/src/mainboard/supermicro/x6dai_g/mptable.c @@ -32,7 +32,7 @@ static void *smp_write_config_table(void *v) mc->reserved = 0; smp_write_processors(mc); - + { device_t dev; @@ -49,7 +49,7 @@ static void *smp_write_config_table(void *v) bus_isa = 6; } } - + /* define bus and isa numbers */ for(bus_num = 0; bus_num < bus_isa; bus_num++) { smp_write_bus(mc, bus_num, "PCI "); diff --git a/src/mainboard/supermicro/x6dai_g/romstage.c b/src/mainboard/supermicro/x6dai_g/romstage.c index b718daf9ab..da5cadac00 100644 --- a/src/mainboard/supermicro/x6dai_g/romstage.c +++ b/src/mainboard/supermicro/x6dai_g/romstage.c @@ -54,8 +54,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void main(unsigned long bist) { /* - * - * + * + * */ static const struct mem_controller mch[] = { { @@ -116,7 +116,7 @@ static void main(unsigned long bist) // dump_bar14(PCI_DEV(0, 0x00, 0)); #endif -#if 0 // temporarily disabled +#if 0 // temporarily disabled /* Check the first 1M */ // ram_check(0x00000000, 0x000100000); // ram_check(0x00000000, 0x000a0000); @@ -127,8 +127,8 @@ static void main(unsigned long bist) #if 0 ram_check(0x00000000, 0x02000000); #endif - -#if 0 + +#if 0 while(1) { hlt(); } diff --git a/src/mainboard/supermicro/x6dai_g/watchdog.c b/src/mainboard/supermicro/x6dai_g/watchdog.c index 2531bc2969..1b1162c00d 100644 --- a/src/mainboard/supermicro/x6dai_g/watchdog.c +++ b/src/mainboard/supermicro/x6dai_g/watchdog.c @@ -18,17 +18,17 @@ static void disable_esb6300_watchdog(void) value = pci_read_config16(dev, 0x04); value |= (1 << 10); pci_write_config16(dev, 0x04, value); - + /* Set and enable acpibase */ pci_write_config32(dev, 0x40, ICH5_WDBASE | 1); pci_write_config8(dev, 0x44, 0x10); base = ICH5_WDBASE + 0x60; - + /* Set bit 11 in TCO1_CNT */ value = inw(base + 0x08); value |= 1 << 11; outw(value, base + 0x08); - + /* Clear TCO timeout status */ outw(0x0008, base + 0x04); outw(0x0002, base + 0x06); diff --git a/src/mainboard/supermicro/x6dhe_g/debug.c b/src/mainboard/supermicro/x6dhe_g/debug.c index b4f2a185b3..87c67b5964 100644 --- a/src/mainboard/supermicro/x6dhe_g/debug.c +++ b/src/mainboard/supermicro/x6dhe_g/debug.c @@ -5,7 +5,7 @@ static void print_reg(unsigned char index) { unsigned char data; - + outb(index, 0x2e); data = inb(0x2f); print_debug("0x"); @@ -15,7 +15,7 @@ static void print_reg(unsigned char index) print_debug("\n"); return; } - + static void xbus_en(void) { /* select the XBUS function in the SIO */ @@ -25,7 +25,7 @@ static void xbus_en(void) outb(0x01, 0x2f); return; } - + static void setup_func(unsigned char func) { /* select the function in the SIO */ @@ -43,27 +43,27 @@ static void setup_func(unsigned char func) print_reg(0x75); return; } - + static void siodump(void) { int i; unsigned char data; - + print_debug("\n*** SERVER I/O REGISTERS ***\n"); for (i=0x10; i<=0x2d; i++) { print_reg((unsigned char)i); } -#if 0 +#if 0 print_debug("\n*** XBUS REGISTERS ***\n"); setup_func(0x0f); for (i=0xf0; i<=0xff; i++) { print_reg((unsigned char)i); } - + print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); setup_func(0x03); print_reg(0xf0); - + print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); setup_func(0x02); print_reg(0xf0); @@ -82,13 +82,13 @@ static void siodump(void) print_debug("\nGPDI 4: 0x"); print_debug_hex8(data); print_debug("\n"); - -#if 0 - + +#if 0 + print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); setup_func(0x0a); print_reg(0xf0); - + print_debug("\n*** FAN CONTROL REGISTERS ***\n"); setup_func(0x09); print_reg(0xf0); @@ -103,11 +103,11 @@ static void siodump(void) print_reg(0xf7); print_reg(0xfe); print_reg(0xff); - + print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); setup_func(0x14); print_reg(0xf0); -#endif +#endif return; } @@ -124,8 +124,8 @@ static void print_debug_pci_dev(unsigned dev) static void print_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -144,7 +144,7 @@ static void dump_pci_device(unsigned dev) int i; print_debug_pci_dev(dev); print_debug("\n"); - + for(i = 0; i <= 255; i++) { unsigned char val; if ((i & 0x0f) == 0) { @@ -164,19 +164,19 @@ static void dump_bar14(unsigned dev) { int i; unsigned long bar; - + print_debug("BAR 14 Dump\n"); - + bar = pci_read_config32(dev, 0x14); for(i = 0; i <= 0x300; i+=4) { -#if 0 +#if 0 unsigned char val; if ((i & 0x0f) == 0) { print_debug_hex8(i); print_debug_char(':'); } val = pci_read_config8(dev, i); -#endif +#endif if((i%4)==0) { print_debug("\n"); print_debug_hex16(i); @@ -191,8 +191,8 @@ static void dump_bar14(unsigned dev) static void dump_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -215,8 +215,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel0[i]; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".0: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { @@ -241,8 +241,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel1[i]; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".1: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { @@ -278,7 +278,7 @@ void dump_spd_registers(void) print_debug("\n"); print_debug("dimm "); print_debug_hex8(device); - + for(i = 0; (i < 256) ; i++) { unsigned char byte; if ((i % 16) == 0) { @@ -291,7 +291,7 @@ void dump_spd_registers(void) print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); @@ -311,7 +311,7 @@ void dump_ipmi_registers(void) print_debug("\n"); print_debug("ipmi "); print_debug_hex8(device); - + for(i = 0; (i < 8) ; i++) { unsigned char byte; status = smbus_read_byte(device, 2); @@ -319,7 +319,7 @@ void dump_ipmi_registers(void) print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); @@ -327,4 +327,4 @@ void dump_ipmi_registers(void) device += SMBUS_MEM_DEVICE_INC; print_debug("\n"); } -} +} diff --git a/src/mainboard/supermicro/x6dhe_g/devicetree.cb b/src/mainboard/supermicro/x6dhe_g/devicetree.cb index d5625e4c7c..075acfc232 100644 --- a/src/mainboard/supermicro/x6dhe_g/devicetree.cb +++ b/src/mainboard/supermicro/x6dhe_g/devicetree.cb @@ -10,8 +10,8 @@ chip northbridge/intel/e7520 # MCH register "pirq_a_d" = "0x0b070a05" register "pirq_e_h" = "0x0a808080" - device pci 1c.0 on - chip drivers/generic/generic + device pci 1c.0 on + chip drivers/generic/generic device pci 01.0 on end # onboard gige1 device pci 02.0 on end # onboard gige2 end @@ -25,9 +25,9 @@ chip northbridge/intel/e7520 # MCH device pci 1d.7 on end # VGA / PCI 32-bit - device pci 1e.0 on + device pci 1e.0 on chip drivers/generic/generic - device pci 01.0 on end + device pci 01.0 on end end end @@ -35,7 +35,7 @@ chip northbridge/intel/e7520 # MCH device pci 1f.0 on # ISA bridge chip superio/winbond/w83627hf device pnp 2e.0 off end - device pnp 2e.2 on + device pnp 2e.2 on io 0x60 = 0x3f8 irq 0x70 = 4 end @@ -62,17 +62,17 @@ chip northbridge/intel/e7520 # MCH device pci 00.0 on end # Northbridge device pci 00.1 on end # Northbridge Error reporting device pci 01.0 on end - device pci 02.0 on - chip southbridge/intel/pxhd # PXHD 6700 - device pci 00.0 on end # bridge + device pci 02.0 on + chip southbridge/intel/pxhd # PXHD 6700 + device pci 00.0 on end # bridge device pci 00.1 on end # I/O apic device pci 00.2 on end # bridge device pci 00.3 on end # I/O apic end end -# device register "intrline" = "0x00070105" - device pci 04.0 on end - device pci 06.0 on end +# device register "intrline" = "0x00070105" + device pci 04.0 on end + device pci 06.0 on end end device apic_cluster 0 on diff --git a/src/mainboard/supermicro/x6dhe_g/mptable.c b/src/mainboard/supermicro/x6dhe_g/mptable.c index c50fabb0f3..81ccf85458 100644 --- a/src/mainboard/supermicro/x6dhe_g/mptable.c +++ b/src/mainboard/supermicro/x6dhe_g/mptable.c @@ -35,7 +35,7 @@ static void *smp_write_config_table(void *v) mc->reserved = 0; smp_write_processors(mc); - + { device_t dev; @@ -75,7 +75,7 @@ static void *smp_write_config_table(void *v) bus_pxhd_2 = 3; } } - + /* define bus and isa numbers */ for(bus_num = 0; bus_num < bus_isa; bus_num++) { smp_write_bus(mc, bus_num, "PCI "); @@ -162,7 +162,7 @@ static void *smp_write_config_table(void *v) bus_esb6300_2, 0x04, 0x02, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added bus_esb6300_2, 0x08, 0x02, 0x14); - + /* Standard local interrupt assignments */ smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x00, MP_APIC_ALL, 0x00); diff --git a/src/mainboard/supermicro/x6dhe_g/romstage.c b/src/mainboard/supermicro/x6dhe_g/romstage.c index 67bd2cfb56..2549cb1327 100644 --- a/src/mainboard/supermicro/x6dhe_g/romstage.c +++ b/src/mainboard/supermicro/x6dhe_g/romstage.c @@ -55,8 +55,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void main(unsigned long bist) { /* - * - * + * + * */ static const struct mem_controller mch[] = { { @@ -118,7 +118,7 @@ static void main(unsigned long bist) #endif disable_watchdogs(); // dump_ipmi_registers(); -// mainboard_set_e7520_leds(); +// mainboard_set_e7520_leds(); sdram_initialize(ARRAY_SIZE(mch), mch); #if 0 dump_pci_devices(); @@ -128,7 +128,7 @@ static void main(unsigned long bist) dump_bar14(PCI_DEV(0, 0x00, 0)); #endif -#if 0 // temporarily disabled +#if 0 // temporarily disabled /* Check the first 1M */ // ram_check(0x00000000, 0x000100000); // ram_check(0x00000000, 0x000a0000); @@ -139,8 +139,8 @@ static void main(unsigned long bist) #if 0 ram_check(0x00000000, 0x02000000); #endif - -#if 0 + +#if 0 while(1) { hlt(); } diff --git a/src/mainboard/supermicro/x6dhe_g/watchdog.c b/src/mainboard/supermicro/x6dhe_g/watchdog.c index 17ec9621ad..a3c55c1543 100644 --- a/src/mainboard/supermicro/x6dhe_g/watchdog.c +++ b/src/mainboard/supermicro/x6dhe_g/watchdog.c @@ -31,17 +31,17 @@ static void disable_esb6300_watchdog(void) value = pci_read_config16(dev, 0x04); value |= (1 << 10); pci_write_config16(dev, 0x04, value); - + /* Set and enable acpibase */ pci_write_config32(dev, 0x40, ESB6300_WDBASE | 1); pci_write_config8(dev, 0x44, 0x10); base = ESB6300_WDBASE + 0x60; - + /* Set bit 11 in TCO1_CNT */ value = inw(base + 0x08); value |= 1 << 11; outw(value, base + 0x08); - + /* Clear TCO timeout status */ outw(0x0008, base + 0x04); outw(0x0002, base + 0x06); @@ -86,7 +86,7 @@ static void disable_jarell_frb3(void) outl(value, base + 0x38); value &= ~(1 << 16); outl(value, base + 0x38); -#endif +#endif } static void disable_watchdogs(void) diff --git a/src/mainboard/supermicro/x6dhe_g/x6dhe_g_fixups.c b/src/mainboard/supermicro/x6dhe_g/x6dhe_g_fixups.c index 82c070b0c1..cc3e41eb9f 100644 --- a/src/mainboard/supermicro/x6dhe_g/x6dhe_g_fixups.c +++ b/src/mainboard/supermicro/x6dhe_g/x6dhe_g_fixups.c @@ -9,13 +9,13 @@ static void mch_reset(void) static void mainboard_set_e7520_pll(unsigned bits) { - return; + return; } static void mainboard_set_e7520_leds(void) { - return; + return; } diff --git a/src/mainboard/supermicro/x6dhe_g2/debug.c b/src/mainboard/supermicro/x6dhe_g2/debug.c index b4f2a185b3..87c67b5964 100644 --- a/src/mainboard/supermicro/x6dhe_g2/debug.c +++ b/src/mainboard/supermicro/x6dhe_g2/debug.c @@ -5,7 +5,7 @@ static void print_reg(unsigned char index) { unsigned char data; - + outb(index, 0x2e); data = inb(0x2f); print_debug("0x"); @@ -15,7 +15,7 @@ static void print_reg(unsigned char index) print_debug("\n"); return; } - + static void xbus_en(void) { /* select the XBUS function in the SIO */ @@ -25,7 +25,7 @@ static void xbus_en(void) outb(0x01, 0x2f); return; } - + static void setup_func(unsigned char func) { /* select the function in the SIO */ @@ -43,27 +43,27 @@ static void setup_func(unsigned char func) print_reg(0x75); return; } - + static void siodump(void) { int i; unsigned char data; - + print_debug("\n*** SERVER I/O REGISTERS ***\n"); for (i=0x10; i<=0x2d; i++) { print_reg((unsigned char)i); } -#if 0 +#if 0 print_debug("\n*** XBUS REGISTERS ***\n"); setup_func(0x0f); for (i=0xf0; i<=0xff; i++) { print_reg((unsigned char)i); } - + print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); setup_func(0x03); print_reg(0xf0); - + print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); setup_func(0x02); print_reg(0xf0); @@ -82,13 +82,13 @@ static void siodump(void) print_debug("\nGPDI 4: 0x"); print_debug_hex8(data); print_debug("\n"); - -#if 0 - + +#if 0 + print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); setup_func(0x0a); print_reg(0xf0); - + print_debug("\n*** FAN CONTROL REGISTERS ***\n"); setup_func(0x09); print_reg(0xf0); @@ -103,11 +103,11 @@ static void siodump(void) print_reg(0xf7); print_reg(0xfe); print_reg(0xff); - + print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); setup_func(0x14); print_reg(0xf0); -#endif +#endif return; } @@ -124,8 +124,8 @@ static void print_debug_pci_dev(unsigned dev) static void print_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -144,7 +144,7 @@ static void dump_pci_device(unsigned dev) int i; print_debug_pci_dev(dev); print_debug("\n"); - + for(i = 0; i <= 255; i++) { unsigned char val; if ((i & 0x0f) == 0) { @@ -164,19 +164,19 @@ static void dump_bar14(unsigned dev) { int i; unsigned long bar; - + print_debug("BAR 14 Dump\n"); - + bar = pci_read_config32(dev, 0x14); for(i = 0; i <= 0x300; i+=4) { -#if 0 +#if 0 unsigned char val; if ((i & 0x0f) == 0) { print_debug_hex8(i); print_debug_char(':'); } val = pci_read_config8(dev, i); -#endif +#endif if((i%4)==0) { print_debug("\n"); print_debug_hex16(i); @@ -191,8 +191,8 @@ static void dump_bar14(unsigned dev) static void dump_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -215,8 +215,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel0[i]; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".0: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { @@ -241,8 +241,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel1[i]; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".1: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { @@ -278,7 +278,7 @@ void dump_spd_registers(void) print_debug("\n"); print_debug("dimm "); print_debug_hex8(device); - + for(i = 0; (i < 256) ; i++) { unsigned char byte; if ((i % 16) == 0) { @@ -291,7 +291,7 @@ void dump_spd_registers(void) print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); @@ -311,7 +311,7 @@ void dump_ipmi_registers(void) print_debug("\n"); print_debug("ipmi "); print_debug_hex8(device); - + for(i = 0; (i < 8) ; i++) { unsigned char byte; status = smbus_read_byte(device, 2); @@ -319,7 +319,7 @@ void dump_ipmi_registers(void) print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); @@ -327,4 +327,4 @@ void dump_ipmi_registers(void) device += SMBUS_MEM_DEVICE_INC; print_debug("\n"); } -} +} diff --git a/src/mainboard/supermicro/x6dhe_g2/devicetree.cb b/src/mainboard/supermicro/x6dhe_g2/devicetree.cb index e621594b93..bbc4e76778 100644 --- a/src/mainboard/supermicro/x6dhe_g2/devicetree.cb +++ b/src/mainboard/supermicro/x6dhe_g2/devicetree.cb @@ -6,12 +6,12 @@ chip northbridge/intel/e7520 # MCH device pnp 00.3 off end end device pci_domain 0 on - chip southbridge/intel/i82801ex # ICH5R + chip southbridge/intel/i82801ex # ICH5R register "pirq_a_d" = "0x0b070a05" register "pirq_e_h" = "0x0a808080" - device pci 1c.0 on - chip drivers/generic/generic + device pci 1c.0 on + chip drivers/generic/generic device pci 01.0 on end # onboard gige1 device pci 02.0 on end # onboard gige2 end @@ -25,9 +25,9 @@ chip northbridge/intel/e7520 # MCH device pci 1d.7 on end # VGA / PCI 32-bit - device pci 1e.0 on + device pci 1e.0 on chip drivers/generic/generic - device pci 01.0 on end + device pci 01.0 on end end end @@ -35,7 +35,7 @@ chip northbridge/intel/e7520 # MCH device pci 1f.0 on # ISA bridge chip superio/nsc/pc87427 device pnp 2e.0 off end - device pnp 2e.2 on + device pnp 2e.2 on io 0x60 = 0x3f8 irq 0x70 = 4 end @@ -62,17 +62,17 @@ chip northbridge/intel/e7520 # MCH device pci 00.0 on end # Northbridge device pci 00.1 on end # Northbridge Error reporting device pci 01.0 on end - device pci 02.0 on - chip southbridge/intel/pxhd # PXHD 6700 - device pci 00.0 on end # bridge + device pci 02.0 on + chip southbridge/intel/pxhd # PXHD 6700 + device pci 00.0 on end # bridge device pci 00.1 on end # I/O apic device pci 00.2 on end # bridge device pci 00.3 on end # I/O apic end end -# device register "intrline" = "0x00070105" - device pci 04.0 on end - device pci 06.0 on end +# device register "intrline" = "0x00070105" + device pci 04.0 on end + device pci 06.0 on end end device apic_cluster 0 on diff --git a/src/mainboard/supermicro/x6dhe_g2/mptable.c b/src/mainboard/supermicro/x6dhe_g2/mptable.c index c50fabb0f3..81ccf85458 100644 --- a/src/mainboard/supermicro/x6dhe_g2/mptable.c +++ b/src/mainboard/supermicro/x6dhe_g2/mptable.c @@ -35,7 +35,7 @@ static void *smp_write_config_table(void *v) mc->reserved = 0; smp_write_processors(mc); - + { device_t dev; @@ -75,7 +75,7 @@ static void *smp_write_config_table(void *v) bus_pxhd_2 = 3; } } - + /* define bus and isa numbers */ for(bus_num = 0; bus_num < bus_isa; bus_num++) { smp_write_bus(mc, bus_num, "PCI "); @@ -162,7 +162,7 @@ static void *smp_write_config_table(void *v) bus_esb6300_2, 0x04, 0x02, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added bus_esb6300_2, 0x08, 0x02, 0x14); - + /* Standard local interrupt assignments */ smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x00, MP_APIC_ALL, 0x00); diff --git a/src/mainboard/supermicro/x6dhe_g2/romstage.c b/src/mainboard/supermicro/x6dhe_g2/romstage.c index 68ad41de40..2b0cbc84d4 100644 --- a/src/mainboard/supermicro/x6dhe_g2/romstage.c +++ b/src/mainboard/supermicro/x6dhe_g2/romstage.c @@ -53,8 +53,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void main(unsigned long bist) { /* - * - * + * + * */ static const struct mem_controller mch[] = { { @@ -117,7 +117,7 @@ static void main(unsigned long bist) #endif disable_watchdogs(); // dump_ipmi_registers(); -// mainboard_set_e7520_leds(); +// mainboard_set_e7520_leds(); sdram_initialize(ARRAY_SIZE(mch), mch); #if 0 dump_pci_devices(); @@ -127,7 +127,7 @@ static void main(unsigned long bist) //dump_bar14(PCI_DEV(0, 0x00, 0)); #endif -#if 0 // temporarily disabled +#if 0 // temporarily disabled /* Check the first 1M */ // ram_check(0x00000000, 0x000100000); // ram_check(0x00000000, 0x000a0000); @@ -138,8 +138,8 @@ static void main(unsigned long bist) #if 0 ram_check(0x00000000, 0x02000000); #endif - -#if 0 + +#if 0 while(1) { hlt(); } diff --git a/src/mainboard/supermicro/x6dhe_g2/watchdog.c b/src/mainboard/supermicro/x6dhe_g2/watchdog.c index 17ec9621ad..a3c55c1543 100644 --- a/src/mainboard/supermicro/x6dhe_g2/watchdog.c +++ b/src/mainboard/supermicro/x6dhe_g2/watchdog.c @@ -31,17 +31,17 @@ static void disable_esb6300_watchdog(void) value = pci_read_config16(dev, 0x04); value |= (1 << 10); pci_write_config16(dev, 0x04, value); - + /* Set and enable acpibase */ pci_write_config32(dev, 0x40, ESB6300_WDBASE | 1); pci_write_config8(dev, 0x44, 0x10); base = ESB6300_WDBASE + 0x60; - + /* Set bit 11 in TCO1_CNT */ value = inw(base + 0x08); value |= 1 << 11; outw(value, base + 0x08); - + /* Clear TCO timeout status */ outw(0x0008, base + 0x04); outw(0x0002, base + 0x06); @@ -86,7 +86,7 @@ static void disable_jarell_frb3(void) outl(value, base + 0x38); value &= ~(1 << 16); outl(value, base + 0x38); -#endif +#endif } static void disable_watchdogs(void) diff --git a/src/mainboard/supermicro/x6dhe_g2/x6dhe_g2_fixups.c b/src/mainboard/supermicro/x6dhe_g2/x6dhe_g2_fixups.c index 82c070b0c1..cc3e41eb9f 100644 --- a/src/mainboard/supermicro/x6dhe_g2/x6dhe_g2_fixups.c +++ b/src/mainboard/supermicro/x6dhe_g2/x6dhe_g2_fixups.c @@ -9,13 +9,13 @@ static void mch_reset(void) static void mainboard_set_e7520_pll(unsigned bits) { - return; + return; } static void mainboard_set_e7520_leds(void) { - return; + return; } diff --git a/src/mainboard/supermicro/x6dhr_ig/debug.c b/src/mainboard/supermicro/x6dhr_ig/debug.c index b4f2a185b3..87c67b5964 100644 --- a/src/mainboard/supermicro/x6dhr_ig/debug.c +++ b/src/mainboard/supermicro/x6dhr_ig/debug.c @@ -5,7 +5,7 @@ static void print_reg(unsigned char index) { unsigned char data; - + outb(index, 0x2e); data = inb(0x2f); print_debug("0x"); @@ -15,7 +15,7 @@ static void print_reg(unsigned char index) print_debug("\n"); return; } - + static void xbus_en(void) { /* select the XBUS function in the SIO */ @@ -25,7 +25,7 @@ static void xbus_en(void) outb(0x01, 0x2f); return; } - + static void setup_func(unsigned char func) { /* select the function in the SIO */ @@ -43,27 +43,27 @@ static void setup_func(unsigned char func) print_reg(0x75); return; } - + static void siodump(void) { int i; unsigned char data; - + print_debug("\n*** SERVER I/O REGISTERS ***\n"); for (i=0x10; i<=0x2d; i++) { print_reg((unsigned char)i); } -#if 0 +#if 0 print_debug("\n*** XBUS REGISTERS ***\n"); setup_func(0x0f); for (i=0xf0; i<=0xff; i++) { print_reg((unsigned char)i); } - + print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); setup_func(0x03); print_reg(0xf0); - + print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); setup_func(0x02); print_reg(0xf0); @@ -82,13 +82,13 @@ static void siodump(void) print_debug("\nGPDI 4: 0x"); print_debug_hex8(data); print_debug("\n"); - -#if 0 - + +#if 0 + print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); setup_func(0x0a); print_reg(0xf0); - + print_debug("\n*** FAN CONTROL REGISTERS ***\n"); setup_func(0x09); print_reg(0xf0); @@ -103,11 +103,11 @@ static void siodump(void) print_reg(0xf7); print_reg(0xfe); print_reg(0xff); - + print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); setup_func(0x14); print_reg(0xf0); -#endif +#endif return; } @@ -124,8 +124,8 @@ static void print_debug_pci_dev(unsigned dev) static void print_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -144,7 +144,7 @@ static void dump_pci_device(unsigned dev) int i; print_debug_pci_dev(dev); print_debug("\n"); - + for(i = 0; i <= 255; i++) { unsigned char val; if ((i & 0x0f) == 0) { @@ -164,19 +164,19 @@ static void dump_bar14(unsigned dev) { int i; unsigned long bar; - + print_debug("BAR 14 Dump\n"); - + bar = pci_read_config32(dev, 0x14); for(i = 0; i <= 0x300; i+=4) { -#if 0 +#if 0 unsigned char val; if ((i & 0x0f) == 0) { print_debug_hex8(i); print_debug_char(':'); } val = pci_read_config8(dev, i); -#endif +#endif if((i%4)==0) { print_debug("\n"); print_debug_hex16(i); @@ -191,8 +191,8 @@ static void dump_bar14(unsigned dev) static void dump_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -215,8 +215,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel0[i]; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".0: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { @@ -241,8 +241,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel1[i]; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".1: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { @@ -278,7 +278,7 @@ void dump_spd_registers(void) print_debug("\n"); print_debug("dimm "); print_debug_hex8(device); - + for(i = 0; (i < 256) ; i++) { unsigned char byte; if ((i % 16) == 0) { @@ -291,7 +291,7 @@ void dump_spd_registers(void) print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); @@ -311,7 +311,7 @@ void dump_ipmi_registers(void) print_debug("\n"); print_debug("ipmi "); print_debug_hex8(device); - + for(i = 0; (i < 8) ; i++) { unsigned char byte; status = smbus_read_byte(device, 2); @@ -319,7 +319,7 @@ void dump_ipmi_registers(void) print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); @@ -327,4 +327,4 @@ void dump_ipmi_registers(void) device += SMBUS_MEM_DEVICE_INC; print_debug("\n"); } -} +} diff --git a/src/mainboard/supermicro/x6dhr_ig/devicetree.cb b/src/mainboard/supermicro/x6dhr_ig/devicetree.cb index 921c54fff5..b989e76e8a 100644 --- a/src/mainboard/supermicro/x6dhr_ig/devicetree.cb +++ b/src/mainboard/supermicro/x6dhr_ig/devicetree.cb @@ -1,21 +1,21 @@ chip northbridge/intel/e7520 # mch - device pci_domain 0 on + device pci_domain 0 on chip southbridge/intel/i82801ex # i82801er # USB ports device pci 1d.0 on end device pci 1d.1 on end - device pci 1d.2 on end + device pci 1d.2 on end device pci 1d.3 on end device pci 1d.7 on end - + # -> VGA device pci 1e.0 on end - + # -> IDE - device pci 1f.0 on + device pci 1f.0 on chip superio/winbond/w83627hf device pnp 2e.0 off end - device pnp 2e.2 on + device pnp 2e.2 on io 0x60 = 0x3f8 irq 0x70 = 4 end @@ -39,18 +39,18 @@ chip northbridge/intel/e7520 # mch register "pirq_a_d" = "0x0b070a05" register "pirq_e_h" = "0x0a808080" end - device pci 00.0 on end + device pci 00.0 on end device pci 00.1 on end - device pci 01.0 on end - device pci 02.0 on end - device pci 03.0 on + device pci 01.0 on end + device pci 02.0 on end + device pci 03.0 on chip southbridge/intel/pxhd # pxhd1 # Bus bridges and ioapics usually bus 2 device pci 0.0 on end device pci 0.1 on end - device pci 0.2 on + device pci 0.2 on # On board gig e1000 - chip drivers/generic/generic + chip drivers/generic/generic device pci 02.0 on end device pci 02.1 on end end @@ -58,7 +58,7 @@ chip northbridge/intel/e7520 # mch device pci 0.3 on end end end - device pci 04.0 on + device pci 04.0 on chip southbridge/intel/pxhd # pxhd2 # Bus bridges and ioapics usually bus 5 device pci 0.0 on end diff --git a/src/mainboard/supermicro/x6dhr_ig/mptable.c b/src/mainboard/supermicro/x6dhr_ig/mptable.c index b98ec52479..efc7abf22a 100644 --- a/src/mainboard/supermicro/x6dhr_ig/mptable.c +++ b/src/mainboard/supermicro/x6dhr_ig/mptable.c @@ -36,7 +36,7 @@ static void *smp_write_config_table(void *v) mc->reserved = 0; smp_write_processors(mc); - + { device_t dev; @@ -98,9 +98,9 @@ static void *smp_write_config_table(void *v) bus_pxhd_4 = 7; } - + } - + /* define bus and isa numbers */ for(bus_num = 0; bus_num < bus_isa; bus_num++) { smp_write_bus(mc, bus_num, "PCI "); @@ -159,7 +159,7 @@ static void *smp_write_config_table(void *v) } } - + /* ISA backward compatibility interrupts */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x00, 0x02, 0x00); diff --git a/src/mainboard/supermicro/x6dhr_ig/romstage.c b/src/mainboard/supermicro/x6dhr_ig/romstage.c index 77c9eba0fb..16f0ac7337 100644 --- a/src/mainboard/supermicro/x6dhr_ig/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig/romstage.c @@ -54,8 +54,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void main(unsigned long bist) { /* - * - * + * + * */ static const struct mem_controller mch[] = { { @@ -117,7 +117,7 @@ static void main(unsigned long bist) #endif disable_watchdogs(); // dump_ipmi_registers(); - mainboard_set_e7520_leds(); + mainboard_set_e7520_leds(); sdram_initialize(ARRAY_SIZE(mch), mch); #if 1 dump_pci_devices(); @@ -127,7 +127,7 @@ static void main(unsigned long bist) dump_bar14(PCI_DEV(0, 0x00, 0)); #endif -#if 0 // temporarily disabled +#if 0 // temporarily disabled /* Check the first 1M */ // ram_check(0x00000000, 0x000100000); // ram_check(0x00000000, 0x000a0000); @@ -139,8 +139,8 @@ static void main(unsigned long bist) #if 0 ram_check(0x00000000, 0x02000000); #endif - -#if 0 + +#if 0 while(1) { hlt(); } diff --git a/src/mainboard/supermicro/x6dhr_ig/watchdog.c b/src/mainboard/supermicro/x6dhr_ig/watchdog.c index a4c1eec04f..44cfd10b73 100644 --- a/src/mainboard/supermicro/x6dhr_ig/watchdog.c +++ b/src/mainboard/supermicro/x6dhr_ig/watchdog.c @@ -31,17 +31,17 @@ static void disable_ich5_watchdog(void) value = pci_read_config16(dev, 0x04); value |= (1 << 10); pci_write_config16(dev, 0x04, value); - + /* Set and enable acpibase */ pci_write_config32(dev, 0x40, ICH5_WDBASE | 1); pci_write_config8(dev, 0x44, 0x10); base = ICH5_WDBASE + 0x60; - + /* Set bit 11 in TCO1_CNT */ value = inw(base + 0x08); value |= 1 << 11; outw(value, base + 0x08); - + /* Clear TCO timeout status */ outw(0x0008, base + 0x04); outw(0x0002, base + 0x06); @@ -86,7 +86,7 @@ static void disable_jarell_frb3(void) outl(value, base + 0x38); value &= ~(1 << 16); outl(value, base + 0x38); -#endif +#endif } static void disable_watchdogs(void) diff --git a/src/mainboard/supermicro/x6dhr_ig/x6dhr_fixups.c b/src/mainboard/supermicro/x6dhr_ig/x6dhr_fixups.c index 82c070b0c1..cc3e41eb9f 100644 --- a/src/mainboard/supermicro/x6dhr_ig/x6dhr_fixups.c +++ b/src/mainboard/supermicro/x6dhr_ig/x6dhr_fixups.c @@ -9,13 +9,13 @@ static void mch_reset(void) static void mainboard_set_e7520_pll(unsigned bits) { - return; + return; } static void mainboard_set_e7520_leds(void) { - return; + return; } diff --git a/src/mainboard/supermicro/x6dhr_ig2/debug.c b/src/mainboard/supermicro/x6dhr_ig2/debug.c index b4f2a185b3..87c67b5964 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/debug.c +++ b/src/mainboard/supermicro/x6dhr_ig2/debug.c @@ -5,7 +5,7 @@ static void print_reg(unsigned char index) { unsigned char data; - + outb(index, 0x2e); data = inb(0x2f); print_debug("0x"); @@ -15,7 +15,7 @@ static void print_reg(unsigned char index) print_debug("\n"); return; } - + static void xbus_en(void) { /* select the XBUS function in the SIO */ @@ -25,7 +25,7 @@ static void xbus_en(void) outb(0x01, 0x2f); return; } - + static void setup_func(unsigned char func) { /* select the function in the SIO */ @@ -43,27 +43,27 @@ static void setup_func(unsigned char func) print_reg(0x75); return; } - + static void siodump(void) { int i; unsigned char data; - + print_debug("\n*** SERVER I/O REGISTERS ***\n"); for (i=0x10; i<=0x2d; i++) { print_reg((unsigned char)i); } -#if 0 +#if 0 print_debug("\n*** XBUS REGISTERS ***\n"); setup_func(0x0f); for (i=0xf0; i<=0xff; i++) { print_reg((unsigned char)i); } - + print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); setup_func(0x03); print_reg(0xf0); - + print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); setup_func(0x02); print_reg(0xf0); @@ -82,13 +82,13 @@ static void siodump(void) print_debug("\nGPDI 4: 0x"); print_debug_hex8(data); print_debug("\n"); - -#if 0 - + +#if 0 + print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); setup_func(0x0a); print_reg(0xf0); - + print_debug("\n*** FAN CONTROL REGISTERS ***\n"); setup_func(0x09); print_reg(0xf0); @@ -103,11 +103,11 @@ static void siodump(void) print_reg(0xf7); print_reg(0xfe); print_reg(0xff); - + print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); setup_func(0x14); print_reg(0xf0); -#endif +#endif return; } @@ -124,8 +124,8 @@ static void print_debug_pci_dev(unsigned dev) static void print_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -144,7 +144,7 @@ static void dump_pci_device(unsigned dev) int i; print_debug_pci_dev(dev); print_debug("\n"); - + for(i = 0; i <= 255; i++) { unsigned char val; if ((i & 0x0f) == 0) { @@ -164,19 +164,19 @@ static void dump_bar14(unsigned dev) { int i; unsigned long bar; - + print_debug("BAR 14 Dump\n"); - + bar = pci_read_config32(dev, 0x14); for(i = 0; i <= 0x300; i+=4) { -#if 0 +#if 0 unsigned char val; if ((i & 0x0f) == 0) { print_debug_hex8(i); print_debug_char(':'); } val = pci_read_config8(dev, i); -#endif +#endif if((i%4)==0) { print_debug("\n"); print_debug_hex16(i); @@ -191,8 +191,8 @@ static void dump_bar14(unsigned dev) static void dump_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -215,8 +215,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel0[i]; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".0: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { @@ -241,8 +241,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel1[i]; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".1: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { @@ -278,7 +278,7 @@ void dump_spd_registers(void) print_debug("\n"); print_debug("dimm "); print_debug_hex8(device); - + for(i = 0; (i < 256) ; i++) { unsigned char byte; if ((i % 16) == 0) { @@ -291,7 +291,7 @@ void dump_spd_registers(void) print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); @@ -311,7 +311,7 @@ void dump_ipmi_registers(void) print_debug("\n"); print_debug("ipmi "); print_debug_hex8(device); - + for(i = 0; (i < 8) ; i++) { unsigned char byte; status = smbus_read_byte(device, 2); @@ -319,7 +319,7 @@ void dump_ipmi_registers(void) print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); @@ -327,4 +327,4 @@ void dump_ipmi_registers(void) device += SMBUS_MEM_DEVICE_INC; print_debug("\n"); } -} +} diff --git a/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb b/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb index 318d492b9f..ed3fa65219 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb +++ b/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb @@ -1,21 +1,21 @@ chip northbridge/intel/e7520 # mch - device pci_domain 0 on + device pci_domain 0 on chip southbridge/intel/i82801ex # i82801er # USB ports device pci 1d.0 on end device pci 1d.1 on end - device pci 1d.2 on end + device pci 1d.2 on end device pci 1d.3 on end device pci 1d.7 on end - + # -> Bridge device pci 1e.0 on end - + # -> ISA - device pci 1f.0 on + device pci 1f.0 on chip superio/winbond/w83627hf device pnp 2e.0 off end - device pnp 2e.2 on + device pnp 2e.2 on io 0x60 = 0x3f8 irq 0x70 = 4 end @@ -34,22 +34,22 @@ chip northbridge/intel/e7520 # mch end # -> IDE device pci 1f.1 on end - # -> SATA + # -> SATA device pci 1f.2 on end device pci 1f.3 on end register "pirq_a_d" = "0x0b070a05" register "pirq_e_h" = "0x0a808080" end - device pci 00.0 on end + device pci 00.0 on end device pci 00.1 on end - device pci 01.0 on end - device pci 02.0 on + device pci 01.0 on end + device pci 02.0 on chip southbridge/intel/pxhd # pxhd1 # Bus bridges and ioapics usually bus 1 - device pci 0.0 on + device pci 0.0 on # On board gig e1000 - chip drivers/generic/generic + chip drivers/generic/generic device pci 03.0 on end device pci 03.1 on end end diff --git a/src/mainboard/supermicro/x6dhr_ig2/mptable.c b/src/mainboard/supermicro/x6dhr_ig2/mptable.c index 78a863c7a1..3e95e108d1 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/mptable.c +++ b/src/mainboard/supermicro/x6dhr_ig2/mptable.c @@ -36,7 +36,7 @@ static void *smp_write_config_table(void *v) mc->reserved = 0; smp_write_processors(mc); - + { device_t dev; @@ -98,9 +98,9 @@ static void *smp_write_config_table(void *v) bus_pxhd_4 = 6; } - + } - + /* define bus and isa numbers */ for(bus_num = 0; bus_num < bus_isa; bus_num++) { smp_write_bus(mc, bus_num, "PCI "); @@ -135,7 +135,7 @@ static void *smp_write_config_table(void *v) else { printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n"); } - } + } /* ISA backward compatibility interrupts */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x00, 0x02, 0x00); diff --git a/src/mainboard/supermicro/x6dhr_ig2/romstage.c b/src/mainboard/supermicro/x6dhr_ig2/romstage.c index d2b845eac6..8f5ca7930e 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig2/romstage.c @@ -54,8 +54,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void main(unsigned long bist) { /* - * - * + * + * */ static const struct mem_controller mch[] = { { @@ -117,7 +117,7 @@ static void main(unsigned long bist) #endif disable_watchdogs(); // dump_ipmi_registers(); - mainboard_set_e7520_leds(); + mainboard_set_e7520_leds(); sdram_initialize(ARRAY_SIZE(mch), mch); #if 0 dump_pci_devices(); @@ -127,7 +127,7 @@ static void main(unsigned long bist) dump_bar14(PCI_DEV(0, 0x00, 0)); #endif -#if 0 // temporarily disabled +#if 0 // temporarily disabled /* Check the first 1M */ // ram_check(0x00000000, 0x000100000); // ram_check(0x00000000, 0x000a0000); @@ -139,8 +139,8 @@ static void main(unsigned long bist) #if 0 ram_check(0x00000000, 0x02000000); #endif - -#if 0 + +#if 0 while(1) { hlt(); } diff --git a/src/mainboard/supermicro/x6dhr_ig2/watchdog.c b/src/mainboard/supermicro/x6dhr_ig2/watchdog.c index a4c1eec04f..44cfd10b73 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/watchdog.c +++ b/src/mainboard/supermicro/x6dhr_ig2/watchdog.c @@ -31,17 +31,17 @@ static void disable_ich5_watchdog(void) value = pci_read_config16(dev, 0x04); value |= (1 << 10); pci_write_config16(dev, 0x04, value); - + /* Set and enable acpibase */ pci_write_config32(dev, 0x40, ICH5_WDBASE | 1); pci_write_config8(dev, 0x44, 0x10); base = ICH5_WDBASE + 0x60; - + /* Set bit 11 in TCO1_CNT */ value = inw(base + 0x08); value |= 1 << 11; outw(value, base + 0x08); - + /* Clear TCO timeout status */ outw(0x0008, base + 0x04); outw(0x0002, base + 0x06); @@ -86,7 +86,7 @@ static void disable_jarell_frb3(void) outl(value, base + 0x38); value &= ~(1 << 16); outl(value, base + 0x38); -#endif +#endif } static void disable_watchdogs(void) diff --git a/src/mainboard/supermicro/x6dhr_ig2/x6dhr2_fixups.c b/src/mainboard/supermicro/x6dhr_ig2/x6dhr2_fixups.c index 82c070b0c1..cc3e41eb9f 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/x6dhr2_fixups.c +++ b/src/mainboard/supermicro/x6dhr_ig2/x6dhr2_fixups.c @@ -9,13 +9,13 @@ static void mch_reset(void) static void mainboard_set_e7520_pll(unsigned bits) { - return; + return; } static void mainboard_set_e7520_leds(void) { - return; + return; } diff --git a/src/mainboard/technexion/Kconfig b/src/mainboard/technexion/Kconfig index c0bf041034..da13c340eb 100644 --- a/src/mainboard/technexion/Kconfig +++ b/src/mainboard/technexion/Kconfig @@ -1,7 +1,7 @@ choice prompt "Mainboard model" depends on VENDOR_TECHNEXION - + source "src/mainboard/technexion/tim8690/Kconfig" source "src/mainboard/technexion/tim5690/Kconfig" diff --git a/src/mainboard/technexion/tim5690/mainboard.c b/src/mainboard/technexion/tim5690/mainboard.c index 11bb4248e7..924d09e55f 100644 --- a/src/mainboard/technexion/tim5690/mainboard.c +++ b/src/mainboard/technexion/tim5690/mainboard.c @@ -184,7 +184,7 @@ static void mb_gpio_init(u16 *iobase) it8712f_enter_conf(); outb(IT8712F_CONFIG_REG_LDN, SIO_INDEX); outb(IT8712F_GPIO, SIO_DATA); - outb(0x62, SIO_INDEX); + outb(0x62, SIO_INDEX); outb((*iobase >> 8), SIO_DATA); outb(0x63, SIO_INDEX); outb((*iobase & 0xff), SIO_DATA); diff --git a/src/mainboard/technexion/tim5690/speaker.c b/src/mainboard/technexion/tim5690/speaker.c index ae11b3eb63..b7f18647d3 100644 --- a/src/mainboard/technexion/tim5690/speaker.c +++ b/src/mainboard/technexion/tim5690/speaker.c @@ -54,7 +54,7 @@ void speaker_init(uint8_t time) { * CounterSelect, bit[7:6]=10b, Select counter 2. */ outb(0xb6, 0x43); - + /* SB600 RRG. * TimerCh2- RW - 8 bits - [IO_Reg: 42h]. diff --git a/src/mainboard/technexion/tim8690/mainboard.c b/src/mainboard/technexion/tim8690/mainboard.c index 294c0f2590..664372d879 100644 --- a/src/mainboard/technexion/tim8690/mainboard.c +++ b/src/mainboard/technexion/tim8690/mainboard.c @@ -48,7 +48,7 @@ uint64_t uma_memory_base, uma_memory_size; /*************************************************** * This board, the TIM-8690 has two Marvel 88e5056 PCI-E -* 10/100/1000 chips on board. +* 10/100/1000 chips on board. * Both of their pin PERSTn pins are connected to GPIO 5 of the * SB600 southbridge. ****************************************************/ diff --git a/src/mainboard/technologic/Kconfig b/src/mainboard/technologic/Kconfig index 32967fd3e5..5756361863 100644 --- a/src/mainboard/technologic/Kconfig +++ b/src/mainboard/technologic/Kconfig @@ -1,7 +1,7 @@ choice prompt "Mainboard model" depends on VENDOR_TECHNOLOGIC - + source "src/mainboard/technologic/ts5300/Kconfig" endchoice diff --git a/src/mainboard/technologic/ts5300/chip.h b/src/mainboard/technologic/ts5300/chip.h index 97f92dd915..ceb8af100a 100644 --- a/src/mainboard/technologic/ts5300/chip.h +++ b/src/mainboard/technologic/ts5300/chip.h @@ -1,5 +1,5 @@ extern struct chip_operations mainboard_ops; struct mainboard_config { - + }; diff --git a/src/mainboard/technologic/ts5300/devicetree.cb b/src/mainboard/technologic/ts5300/devicetree.cb index 65809cb2f4..a0f05791af 100644 --- a/src/mainboard/technologic/ts5300/devicetree.cb +++ b/src/mainboard/technologic/ts5300/devicetree.cb @@ -1,7 +1,7 @@ chip cpu/amd/sc520 - device pci_domain 0 on + device pci_domain 0 on device pci 0.0 on end - + # register "com1" = "{1}" # register "com1" = "{1, 0, 0x3f8, 4}" end diff --git a/src/mainboard/technologic/ts5300/irq_tables.c b/src/mainboard/technologic/ts5300/irq_tables.c index 9b49747ead..22d5820a62 100644 --- a/src/mainboard/technologic/ts5300/irq_tables.c +++ b/src/mainboard/technologic/ts5300/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up * diff --git a/src/mainboard/technologic/ts5300/mainboard.c b/src/mainboard/technologic/ts5300/mainboard.c index 4b9ce16bf8..58333b8f88 100644 --- a/src/mainboard/technologic/ts5300/mainboard.c +++ b/src/mainboard/technologic/ts5300/mainboard.c @@ -17,10 +17,10 @@ static void irqdump(void) int i; int irqlist[] = {0xd00, 0xd02, 0xd03, 0xd04, 0xd08, 0xd0a, 0xd14, 0xd18, 0xd1a, 0xd1b, 0xd1c, - 0xd20, 0xd21, 0xd22, 0xd28, 0xd29, + 0xd20, 0xd21, 0xd22, 0xd28, 0xd29, 0xd30, 0xd31, 0xd32, 0xd33, - 0xd40, 0xd41, 0xd42, 0xd43,0xd44, 0xd45, 0xd46, - 0xd50, 0xd51, 0xd52, 0xd53,0xd54, 0xd55, 0xd56, 0xd57,0xd58, 0xd59, 0xd5a, + 0xd40, 0xd41, 0xd42, 0xd43,0xd44, 0xd45, 0xd46, + 0xd50, 0xd51, 0xd52, 0xd53,0xd54, 0xd55, 0xd56, 0xd57,0xd58, 0xd59, 0xd5a, -1}; mmcr = (void *) 0xfffef000; @@ -44,7 +44,7 @@ static void enable_dev(struct device *dev) { /* from fuctory bios */ /* NOTE: the following interrupt settings made interrupts work - * for hard drive, and serial, but not for ethernet + * for hard drive, and serial, but not for ethernet */ printk(BIOS_ERR, "Setting up PIC\n"); @@ -63,7 +63,7 @@ static void enable_dev(struct device *dev) { mmcr->pic.rtcmap = 0x03; mmcr->pic.ferrmap = 0x00; mmcr->pic.intpinpol = 0x100; - + mmcr->pic.gp0imap = 0x00; mmcr->pic.gp1imap = 0x02; mmcr->pic.gp2imap = 0x07; @@ -83,7 +83,7 @@ static void enable_dev(struct device *dev) { mmcr->sysarb.ctl = 0x00; mmcr->sysarb.menb = 0x1f; mmcr->sysarb.prictl = 0x40000f0f; - + /* this is bios setting, depends on sysarb above */ mmcr->hostbridge.ctl = 0x0; mmcr->hostbridge.tgtirqctl = 0x0; @@ -125,7 +125,7 @@ static void enable_dev(struct device *dev) { mmcr->gpctl.gprdoff = 0x02; mmcr->gpctl.gpwrw = 0x07; mmcr->gpctl.gpwroff = 0x02; - + //mmcr->reset.sysinfo = 0xdf; //mmcr->reset.rescfg = 0x5; /* their IRQ table is wrong. Just hardwire it */ diff --git a/src/mainboard/technologic/ts5300/romstage.c b/src/mainboard/technologic/ts5300/romstage.c index 4379c2457d..d0f0d4c61c 100644 --- a/src/mainboard/technologic/ts5300/romstage.c +++ b/src/mainboard/technologic/ts5300/romstage.c @@ -52,7 +52,7 @@ void setup_pars(void) static void identify_ts9500(void) { unsigned i, val; - + TS9500_LED_ON; print_err("TS-9500 add-on found:\n"); @@ -61,23 +61,23 @@ static void identify_ts9500(void) print_err(" DIP"); print_err_char(i+0x31); print_err(": "); - if((val&(1<<i))!=0) - print_err("on\n"); + if((val&(1<<i))!=0) + print_err("on\n"); else - print_err("off\n"); + print_err("off\n"); } print_err("\n"); - + val=inb(0x19a); - + for (i=6; i<8; i++) { print_err(" JP"); print_err_char(i+0x30-5); print_err(": "); - if((val&(1<<i))!=0) - print_err("on\n"); + if((val&(1<<i))!=0) + print_err("on\n"); else - print_err("off\n"); + print_err("off\n"); } print_err("\n"); @@ -103,33 +103,33 @@ static void identify_system(void) print_err(" SRAM option: "); if((val&1)==0) print_err("not "); print_err("installed\n"); - + print_err(" RS-485 option: "); if((val&2)==0) print_err("not "); print_err("installed\n"); val=inb(0x76); print_err(" Temp. range: "); - if((val&2)==0) print_err("commercial\n"); + if((val&2)==0) print_err("commercial\n"); else print_err("industrial\n"); - + print_err("\n"); - + val=inb(0x77); for (i=1; i<8; i++) { print_err(" JP"); print_err_char(i+0x30); print_err(": "); - if((val&(1<<i))!=0) - print_err("on\n"); + if((val&(1<<i))!=0) + print_err("on\n"); else - print_err("off\n"); + print_err("off\n"); } print_err("\n"); /* Detect TS-9500 */ val=inb(0x19d); - if(val==0x5f) + if(val==0x5f) identify_ts9500(); } @@ -144,18 +144,18 @@ static void main(unsigned long bist) { volatile int i; unsigned val; - + TS5300_LED_ON; - + // Let the hardware settle a bit. for(i = 0; i < 100; i++) ; - + setupsc520(); uart_init(); console_init(); - - + + print_err("Technologic Systems TS5300 - http://www.embeddedx86.com/\n"); staticmem(); print_err("Memory initialized: 32MB\n"); @@ -170,7 +170,7 @@ static void main(unsigned long bist) ram_check(0x00000000, 0x000a0000); ram_check(0x000b0000, 0x02000000); #endif - + TS5300_LED_OFF; } diff --git a/src/mainboard/thomson/Kconfig b/src/mainboard/thomson/Kconfig index 936ad3e71d..eb2caa09ff 100644 --- a/src/mainboard/thomson/Kconfig +++ b/src/mainboard/thomson/Kconfig @@ -1,7 +1,7 @@ choice prompt "Mainboard model" depends on VENDOR_THOMSON - + source "src/mainboard/thomson/ip1000/Kconfig" endchoice diff --git a/src/mainboard/thomson/ip1000/gpio.c b/src/mainboard/thomson/ip1000/gpio.c index 6a69bb539d..1c5125a253 100644 --- a/src/mainboard/thomson/ip1000/gpio.c +++ b/src/mainboard/thomson/ip1000/gpio.c @@ -61,13 +61,13 @@ static void mb_gpio_init(void) outl(0x01, PME_IO_BASE_ADDR + 0x2c); /* GP30 - FAN2_TACH */ - outl(0x05, PME_IO_BASE_ADDR + 0x33); + outl(0x05, PME_IO_BASE_ADDR + 0x33); /* GP31 - FAN1_TACH */ outl(0x05, PME_IO_BASE_ADDR + 0x34); /* GP32 - FAN2_CTRL */ - outl(0x04, PME_IO_BASE_ADDR + 0x35); + outl(0x04, PME_IO_BASE_ADDR + 0x35); /* GP33 - FAN1_CTRL */ outl(0x04, PME_IO_BASE_ADDR + 0x36); @@ -82,7 +82,7 @@ static void mb_gpio_init(void) outl(0x00, PME_IO_BASE_ADDR + 0x3a); /* GP42 - GPIO_PME_OUT */ - outl(0x00, PME_IO_BASE_ADDR + 0x3d); + outl(0x00, PME_IO_BASE_ADDR + 0x3d); /* GP50 - SER2_RI */ outl(0x05, PME_IO_BASE_ADDR + 0x3f); diff --git a/src/mainboard/thomson/ip1000/mainboard.c b/src/mainboard/thomson/ip1000/mainboard.c index c78a710321..f6eee68440 100644 --- a/src/mainboard/thomson/ip1000/mainboard.c +++ b/src/mainboard/thomson/ip1000/mainboard.c @@ -62,13 +62,13 @@ static void parport_gpios(void) printk(BIOS_DEBUG, "IP1000 GPIOs:\n"); printk(BIOS_DEBUG, " GPIO mask: %02x\n", pp_gpios); - printk(BIOS_DEBUG, " green led: %s\n", + printk(BIOS_DEBUG, " green led: %s\n", (pp_gpios & PARPORT_GPIO_LED_GREEN) ? "off" : "on"); - printk(BIOS_DEBUG, " orange led: %s\n", + printk(BIOS_DEBUG, " orange led: %s\n", (pp_gpios & PARPORT_GPIO_LED_ORANGE) ? "off" : "on"); - printk(BIOS_DEBUG, " red led: %s\n", + printk(BIOS_DEBUG, " red led: %s\n", (pp_gpios & PARPORT_GPIO_LED_RED) ? "off" : "on"); - printk(BIOS_DEBUG, " IR port: %s\n", + printk(BIOS_DEBUG, " IR port: %s\n", (pp_gpios & PARPORT_GPIO_IR_PORT) ? "off" : "on"); } @@ -77,7 +77,7 @@ static void flash_gpios(void) u8 manufacturer_id = read8(0xffbc0000); u8 device_id = read8(0xffbc0001); - if ((manufacturer_id == 0x20) && + if ((manufacturer_id == 0x20) && ((device_id == 0x2c) || (device_id == 0x2d))) { printk(BIOS_DEBUG, "Detected ST M50FW0%c0 flash:\n", (device_id==0x2c)?'4':'8'); diff --git a/src/mainboard/thomson/ip1000/romstage.c b/src/mainboard/thomson/ip1000/romstage.c index bf78a1d2d1..66b92d14bd 100644 --- a/src/mainboard/thomson/ip1000/romstage.c +++ b/src/mainboard/thomson/ip1000/romstage.c @@ -89,7 +89,7 @@ static void mb_early_setup(void) /* CPU Frequency Strap */ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd5, 0x02); /* ACPI base address and enable Resource Indicator */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, (PMBASE_ADDR | 1)); + pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, (PMBASE_ADDR | 1)); /* Enable the SMBUS */ enable_smbus(); /* ACPI Enable */ diff --git a/src/mainboard/tyan/Kconfig b/src/mainboard/tyan/Kconfig index 93b6d9d4c2..cd9646b38c 100644 --- a/src/mainboard/tyan/Kconfig +++ b/src/mainboard/tyan/Kconfig @@ -21,7 +21,7 @@ choice prompt "Mainboard model" depends on VENDOR_TYAN - + source "src/mainboard/tyan/s1846/Kconfig" source "src/mainboard/tyan/s2735/Kconfig" source "src/mainboard/tyan/s2850/Kconfig" diff --git a/src/mainboard/tyan/s2735/Kconfig b/src/mainboard/tyan/s2735/Kconfig index a0f739c071..a387d1a4ba 100644 --- a/src/mainboard/tyan/s2735/Kconfig +++ b/src/mainboard/tyan/s2735/Kconfig @@ -26,12 +26,12 @@ config DCACHE_RAM_BASE hex default 0xcf000 depends on BOARD_TYAN_S2735 - + config DCACHE_RAM_SIZE hex default 0x1000 depends on BOARD_TYAN_S2735 - + config MAINBOARD_PART_NUMBER string default "S2735" diff --git a/src/mainboard/tyan/s2735/cmos.layout b/src/mainboard/tyan/s2735/cmos.layout index ccda70c808..608f02867c 100644 --- a/src/mainboard/tyan/s2735/cmos.layout +++ b/src/mainboard/tyan/s2735/cmos.layout @@ -30,8 +30,8 @@ entries 388 4 r 0 reboot_bits 392 3 e 5 baud_rate 395 1 e 2 hyper_threading -396 1 e 1 thermal_monitoring -397 1 e 1 remap_memory_high +396 1 e 1 thermal_monitoring +397 1 e 1 remap_memory_high 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first diff --git a/src/mainboard/tyan/s2735/devicetree.cb b/src/mainboard/tyan/s2735/devicetree.cb index 8ad5e0ecac..1e8b12a790 100644 --- a/src/mainboard/tyan/s2735/devicetree.cb +++ b/src/mainboard/tyan/s2735/devicetree.cb @@ -5,7 +5,7 @@ chip northbridge/intel/e7501 device pci 2.0 on chip southbridge/intel/i82870 device pci 1c.0 on end - device pci 1d.0 on + device pci 1d.0 on device pci 1.0 on end # intel lan device pci 1.1 on end end @@ -20,7 +20,7 @@ chip northbridge/intel/e7501 device pci 1d.2 on end device pci 1d.3 on end device pci 1d.7 on end - device pci 1e.0 on + device pci 1e.0 on device pci 1.0 on end # intel lan 10/100 device pci 2.0 on end # ati end @@ -56,7 +56,7 @@ chip northbridge/intel/e7501 io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 - end + end device pnp 2e.8 off end # GPIO2 device pnp 2e.9 off end # GPIO3 device pnp 2e.a off end # ACPI diff --git a/src/mainboard/tyan/s2735/irq_tables.c b/src/mainboard/tyan/s2735/irq_tables.c index 4f6eb306dc..036b8d0cb0 100644 --- a/src/mainboard/tyan/s2735/irq_tables.c +++ b/src/mainboard/tyan/s2735/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up diff --git a/src/mainboard/tyan/s2735/mptable.c b/src/mainboard/tyan/s2735/mptable.c index 6a73c6dc88..cde5c4e3b4 100644 --- a/src/mainboard/tyan/s2735/mptable.c +++ b/src/mainboard/tyan/s2735/mptable.c @@ -48,18 +48,18 @@ static void *smp_write_config_table(void *v) res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, 0x09, 0x20, res->base); - } + } } dev = dev_find_slot(1, PCI_DEVFN(0x1c,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, 0x0a, 0x20, res->base); - } + } } } /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# -*/ +*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x0, 0x8, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x1, 0x8, 0x1); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x0, 0x8, 0x2); @@ -149,7 +149,7 @@ Compatibility Bus Address predefined range: 0x00000000-- Compatibility Bus Address bus ID: 0 address modifier: add - predefined range: 0x00000001 // There is no extension information... + predefined range: 0x00000001 // There is no extension information... */ /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); diff --git a/src/mainboard/tyan/s2735/romstage.c b/src/mainboard/tyan/s2735/romstage.c index f581de431e..de3124cb90 100644 --- a/src/mainboard/tyan/s2735/romstage.c +++ b/src/mainboard/tyan/s2735/romstage.c @@ -1,4 +1,4 @@ - + #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -50,7 +50,7 @@ void main(unsigned long bist) .channel1 = { (0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, 0 }, }, }; - + if (bist == 0) { enable_lapic(); } diff --git a/src/mainboard/tyan/s2850/devicetree.cb b/src/mainboard/tyan/s2850/devicetree.cb index 264f8c7df6..98e6a28746 100644 --- a/src/mainboard/tyan/s2850/devicetree.cb +++ b/src/mainboard/tyan/s2850/devicetree.cb @@ -1,9 +1,9 @@ chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on - chip cpu/amd/socket_940 - device apic 0 on end - end - end + device apic_cluster 0 on + chip cpu/amd/socket_940 + device apic 0 on end + end + end device pci_domain 0 on chip northbridge/amd/amdk8 device pci 18.0 on # LDT0 @@ -51,7 +51,7 @@ chip northbridge/amd/amdk8/root_complex io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 - end + end device pnp 2e.8 off end # GPIO2 device pnp 2e.9 off end # GPIO3 device pnp 2e.a off end # ACPI @@ -63,7 +63,7 @@ chip northbridge/amd/amdk8/root_complex end device pci 1.1 on end device pci 1.2 on end - device pci 1.3 on + device pci 1.3 on chip drivers/generic/generic #dimm 0-0-0 device i2c 50 on end end @@ -82,14 +82,14 @@ chip northbridge/amd/amdk8/root_complex register "ide0_enable" = "1" register "ide1_enable" = "1" end - end # device pci 18.0 + end # device pci 18.0 device pci 18.0 on end device pci 18.0 on end - + device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end end - end + end end diff --git a/src/mainboard/tyan/s2850/irq_tables.c b/src/mainboard/tyan/s2850/irq_tables.c index 8c7e681ec2..d1179dcfae 100644 --- a/src/mainboard/tyan/s2850/irq_tables.c +++ b/src/mainboard/tyan/s2850/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up diff --git a/src/mainboard/tyan/s2850/mptable.c b/src/mainboard/tyan/s2850/mptable.c index 0d4d6f9bc1..51c060126f 100644 --- a/src/mainboard/tyan/s2850/mptable.c +++ b/src/mainboard/tyan/s2850/mptable.c @@ -29,7 +29,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) dst_node = (config_map >> 4) & 7; dst_link = (config_map >> 8) & 3; bus_base = (config_map >> 16) & 0xff; -#if 0 +#if 0 printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", dst_node, dst_link, bus_base, reg, config_map); @@ -90,8 +90,8 @@ static void *smp_write_config_table(void *v) bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa++; - } - else { + } + else { printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n"); bus_8111_1 = 2; @@ -110,12 +110,12 @@ static void *smp_write_config_table(void *v) #if CONFIG_LOGICAL_CPUS==1 apicid_base = get_apicid_base(1); #else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif - apicid_8111 = apicid_base+0; + apicid_8111 = apicid_base+0; smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000); - + /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_8111, 0x0); @@ -133,7 +133,7 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chain_0, (2<<2)|3, apicid_8111, 0x13); - + //On Board AMD USB smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13); diff --git a/src/mainboard/tyan/s2850/romstage.c b/src/mainboard/tyan/s2850/romstage.c index 6fbafa90cb..4e75e36832 100644 --- a/src/mainboard/tyan/s2850/romstage.c +++ b/src/mainboard/tyan/s2850/romstage.c @@ -1,4 +1,4 @@ - + #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -114,7 +114,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } // post_code(0x32); - + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -125,7 +125,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_default_resource_map(); needs_reset = setup_coherent_ht_domain(); - + #if CONFIG_LOGICAL_CPUS==1 // It is said that we should start core1 after all core0 launched start_other_cores(); diff --git a/src/mainboard/tyan/s2875/devicetree.cb b/src/mainboard/tyan/s2875/devicetree.cb index badb881777..edd4f6f784 100644 --- a/src/mainboard/tyan/s2875/devicetree.cb +++ b/src/mainboard/tyan/s2875/devicetree.cb @@ -6,7 +6,7 @@ chip northbridge/amd/amdk8/root_complex end device pci_domain 0 on chip northbridge/amd/amdk8 - device pci 18.0 on # northbridge + device pci 18.0 on # northbridge # devices on link 0, link 0 == LDT 0 chip southbridge/amd/amd8151 # the on/off keyword is mandatory @@ -55,7 +55,7 @@ chip northbridge/amd/amdk8/root_complex io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 - end + end device pnp 2e.8 off end # GPIO2 device pnp 2e.9 off end # GPIO3 device pnp 2e.a off end # ACPI @@ -73,15 +73,15 @@ chip northbridge/amd/amdk8/root_complex register "ide0_enable" = "1" register "ide1_enable" = "1" end - end # device pci 18.0 - + end # device pci 18.0 + device pci 18.0 on end device pci 18.0 on end - + device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end end - end + end end diff --git a/src/mainboard/tyan/s2875/irq_tables.c b/src/mainboard/tyan/s2875/irq_tables.c index db30d686c8..d08aa6ca09 100644 --- a/src/mainboard/tyan/s2875/irq_tables.c +++ b/src/mainboard/tyan/s2875/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up diff --git a/src/mainboard/tyan/s2875/mptable.c b/src/mainboard/tyan/s2875/mptable.c index 77afde6abf..c2a7012f13 100644 --- a/src/mainboard/tyan/s2875/mptable.c +++ b/src/mainboard/tyan/s2875/mptable.c @@ -28,7 +28,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) dst_node = (config_map >> 4) & 7; dst_link = (config_map >> 8) & 3; bus_base = (config_map >> 16) & 0xff; -#if 0 +#if 0 printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", dst_node, dst_link, bus_base, reg, config_map); @@ -104,15 +104,15 @@ static void *smp_write_config_table(void *v) if (dev) { bus_8151_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); printk(BIOS_DEBUG, "bus_8151_1=%d\n",bus_8151_1); - + } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n"); bus_8151_1 = 2; } - - + + } /*Bus: Bus ID Type*/ @@ -126,11 +126,11 @@ static void *smp_write_config_table(void *v) #if CONFIG_LOGICAL_CPUS==1 apicid_base = get_apicid_base(1); #else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif - apicid_8111 = apicid_base+0; + apicid_8111 = apicid_base+0; smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000); - + /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_8111, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_8111, 0x1); @@ -156,7 +156,7 @@ static void *smp_write_config_table(void *v) // AGP Display Adapter smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8151_1, 0x0, apicid_8111, 0x10); -// Onboard Serial ATA +// Onboard Serial ATA smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x05<<2)|0, apicid_8111, 0x13); //Onboard Firewire smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|0, apicid_8111, 0x11); diff --git a/src/mainboard/tyan/s2875/romstage.c b/src/mainboard/tyan/s2875/romstage.c index 274f8dc7ca..ead3655fae 100644 --- a/src/mainboard/tyan/s2875/romstage.c +++ b/src/mainboard/tyan/s2875/romstage.c @@ -1,4 +1,4 @@ - + #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -135,7 +135,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_default_resource_map(); needs_reset = setup_coherent_ht_domain(); - + #if CONFIG_LOGICAL_CPUS==1 // It is said that we should start core1 after all core0 launched start_other_cores(); diff --git a/src/mainboard/tyan/s2880/devicetree.cb b/src/mainboard/tyan/s2880/devicetree.cb index 122648e137..97dcae866a 100644 --- a/src/mainboard/tyan/s2880/devicetree.cb +++ b/src/mainboard/tyan/s2880/devicetree.cb @@ -6,7 +6,7 @@ chip northbridge/amd/amdk8/root_complex end device pci_domain 0 on chip northbridge/amd/amdk8 - device pci 18.0 on # northbridge + device pci 18.0 on # northbridge # devices on link 0, link 0 == LDT 0 chip southbridge/amd/amd8131 # the on/off keyword is mandatory @@ -66,7 +66,7 @@ chip northbridge/amd/amdk8/root_complex io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 - end + end device pnp 2e.8 off end # GPIO2 device pnp 2e.9 off end # GPIO3 device pnp 2e.a off end # ACPI @@ -84,15 +84,15 @@ chip northbridge/amd/amdk8/root_complex register "ide0_enable" = "1" register "ide1_enable" = "1" end - end # device pci 18.0 - + end # device pci 18.0 + device pci 18.0 on end device pci 18.0 on end - + device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end end - end + end end diff --git a/src/mainboard/tyan/s2880/irq_tables.c b/src/mainboard/tyan/s2880/irq_tables.c index 78c12016b4..19149df142 100644 --- a/src/mainboard/tyan/s2880/irq_tables.c +++ b/src/mainboard/tyan/s2880/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up @@ -37,5 +37,5 @@ const struct irq_routing_table intel_irq_routing_table = { }; unsigned long write_pirq_routing_table(unsigned long addr) { - return copy_pirq_routing_table(addr); + return copy_pirq_routing_table(addr); } diff --git a/src/mainboard/tyan/s2880/mptable.c b/src/mainboard/tyan/s2880/mptable.c index a8f3859d7b..94a150b031 100644 --- a/src/mainboard/tyan/s2880/mptable.c +++ b/src/mainboard/tyan/s2880/mptable.c @@ -29,7 +29,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) dst_node = (config_map >> 4) & 7; dst_link = (config_map >> 8) & 3; bus_base = (config_map >> 16) & 0xff; -#if 0 +#if 0 printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", dst_node, dst_link, bus_base, reg, config_map); @@ -60,7 +60,7 @@ static void *smp_write_config_table(void *v) unsigned apicid_8111; unsigned apicid_8131_1; unsigned apicid_8131_2; - + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); @@ -89,14 +89,14 @@ static void *smp_write_config_table(void *v) printk(BIOS_DEBUG, "ERROR - cound not find bus for node 0 chain 0, using defaults\n"); bus_chain_0 = 1; } - + /* 8111 */ dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0)); if (dev) { bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_isa++; - } + bus_isa++; + } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n"); @@ -134,14 +134,14 @@ static void *smp_write_config_table(void *v) } smp_write_bus(mc, bus_isa, "ISA "); - + /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS==1 apicid_base = get_apicid_base(3); #else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif - apicid_8111 = apicid_base+0; + apicid_8111 = apicid_base+0; apicid_8131_1 = apicid_base+1; apicid_8131_2 = apicid_base+2; smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000); @@ -165,7 +165,7 @@ static void *smp_write_config_table(void *v) } } - + /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_8111, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_8111, 0x1); @@ -179,7 +179,7 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, apicid_8111, 0xd); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_8111, 0xe); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_8111, 0xf); - + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chain_0, (4<<2)|0, apicid_8111, 0x13); @@ -205,7 +205,7 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|2, apicid_8131_1, 0x1);// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|3, apicid_8131_1, 0x2);// -//Slot 4 PCIX 100/66 +//Slot 4 PCIX 100/66 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|0, apicid_8131_1, 0x2); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|1, apicid_8131_1, 0x3);// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|2, apicid_8131_1, 0x0);// diff --git a/src/mainboard/tyan/s2880/romstage.c b/src/mainboard/tyan/s2880/romstage.c index 7c0e4f2a2c..f75c541b9c 100644 --- a/src/mainboard/tyan/s2880/romstage.c +++ b/src/mainboard/tyan/s2880/romstage.c @@ -1,4 +1,4 @@ - + #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -125,7 +125,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) init_cpus(cpu_init_detectedx); } - + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -136,7 +136,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_default_resource_map(); needs_reset = setup_coherent_ht_domain(); - + #if CONFIG_LOGICAL_CPUS==1 // It is said that we should start core1 after all core0 launched start_other_cores(); diff --git a/src/mainboard/tyan/s2881/devicetree.cb b/src/mainboard/tyan/s2881/devicetree.cb index 3c1f5bc276..47b5d37775 100644 --- a/src/mainboard/tyan/s2881/devicetree.cb +++ b/src/mainboard/tyan/s2881/devicetree.cb @@ -8,11 +8,11 @@ chip northbridge/amd/amdk8/root_complex chip northbridge/amd/amdk8 device pci 18.0 on end # LDT0 device pci 18.0 on end # LDT1 - device pci 18.0 on # northbridge + device pci 18.0 on # northbridge # devices on link 2, link 2 == LDT 2 chip southbridge/amd/amd8131 # the on/off keyword is mandatory - device pci 0.0 on + device pci 0.0 on device pci 9.0 on end # Broadcom 5704 device pci 9.1 on end device pci a.0 on end # Adaptic @@ -65,7 +65,7 @@ chip northbridge/amd/amdk8/root_complex io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 - end + end device pnp 2e.8 off end # GPIO2 device pnp 2e.9 off end # GPIO3 device pnp 2e.a off end # ACPI @@ -77,13 +77,13 @@ chip northbridge/amd/amdk8/root_complex end device pci 1.1 on end device pci 1.2 on end - device pci 1.3 on + device pci 1.3 on chip drivers/generic/generic #dimm 0-0-0 device i2c 50 on end end chip drivers/generic/generic #dimm 0-0-1 device i2c 51 on end - end + end chip drivers/generic/generic #dimm 0-1-0 device i2c 52 on end end @@ -120,12 +120,12 @@ chip northbridge/amd/amdk8/root_complex register "ide0_enable" = "1" register "ide1_enable" = "1" end - end # device pci 18.0 - + end # device pci 18.0 + device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end end - end + end end diff --git a/src/mainboard/tyan/s2881/get_bus_conf.c b/src/mainboard/tyan/s2881/get_bus_conf.c index 758e3d809d..562ba935d8 100644 --- a/src/mainboard/tyan/s2881/get_bus_conf.c +++ b/src/mainboard/tyan/s2881/get_bus_conf.c @@ -23,7 +23,7 @@ unsigned apicid_8111 ; unsigned apicid_8131_1; unsigned apicid_8131_2; -unsigned pci1234x[] = +unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail 0x0000ff0, @@ -35,7 +35,7 @@ unsigned pci1234x[] = // 0x0000ff0, // 0x0000ff0 }; -unsigned hcdnx[] = +unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, // 0x20202020, @@ -71,7 +71,7 @@ void get_bus_conf(void) } get_sblk_pci1234(); - + sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff; sbdn3 = sysconf.hcdn[0] & 0xff; @@ -119,8 +119,8 @@ void get_bus_conf(void) /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS==1 apicid_base = get_apicid_base(3); -#else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; +#else + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif apicid_8111 = apicid_base+0; apicid_8131_1 = apicid_base+1; diff --git a/src/mainboard/tyan/s2881/irq_tables.c b/src/mainboard/tyan/s2881/irq_tables.c index af66ba9730..b53a9923a7 100644 --- a/src/mainboard/tyan/s2881/irq_tables.c +++ b/src/mainboard/tyan/s2881/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up @@ -12,11 +12,11 @@ #include <cpu/amd/amdk8_sysconf.h> -static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, +static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; + pirq_info->bus = bus; pirq_info->devfn = devfn; pirq_info->irq[0].link = link0; pirq_info->irq[0].bitmap = bitmap0; @@ -62,22 +62,22 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq = (void *)(addr); v = (uint8_t *)(addr); - + pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - + pirq->rtr_bus = bus_8111_0; pirq->rtr_devfn = ((sysconf.sbdn+1)<<3)|0; pirq->exclusive_irqs = 0; - + pirq->rtr_vendor = 0x1022; pirq->rtr_device = 0x746b; pirq->miniport_data = 0; memset(pirq->rfu, 0, sizeof(pirq->rfu)); - + pirq_info = (void *) ( &pirq->checksum + 1); slot_num = 0; //pci bridge @@ -88,11 +88,11 @@ unsigned long write_pirq_routing_table(unsigned long addr) // pirq_info++; slot_num++; pirq_info++; slot_num++; - - pirq->size = 32 + 16 * slot_num; + + pirq->size = 32 + 16 * slot_num; for (i = 0; i < pirq->size; i++) - sum += v[i]; + sum += v[i]; sum = pirq->checksum - sum; diff --git a/src/mainboard/tyan/s2881/mainboard.c b/src/mainboard/tyan/s2881/mainboard.c index 5866577ce4..773f2540a4 100644 --- a/src/mainboard/tyan/s2881/mainboard.c +++ b/src/mainboard/tyan/s2881/mainboard.c @@ -59,7 +59,7 @@ static void adt7463_init(device_t dev) result = smbus_write_byte(adt7463, 0x5e, 0xc2); /* Make sure that our fans never stop when temp. falls below Tmin, - * but rather keep going at minimum duty cycle (applies to automatic + * but rather keep going at minimum duty cycle (applies to automatic * fan control mode only). */ result = smbus_write_byte(adt7463, 0x62, 0xc0); diff --git a/src/mainboard/tyan/s2881/mptable.c b/src/mainboard/tyan/s2881/mptable.c index ca75c51a93..a51384c641 100644 --- a/src/mainboard/tyan/s2881/mptable.c +++ b/src/mainboard/tyan/s2881/mptable.c @@ -30,7 +30,7 @@ static void *smp_write_config_table(void *v) unsigned char bus_num; int i; - + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); @@ -51,7 +51,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); get_bus_conf(); - + /*Bus: Bus ID Type*/ /* define bus and isa numbers */ @@ -60,7 +60,7 @@ static void *smp_write_config_table(void *v) } smp_write_bus(mc, bus_isa, "ISA "); - + /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000); { @@ -82,7 +82,7 @@ static void *smp_write_config_table(void *v) } } - + /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_8111, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_8111, 0x1); @@ -96,7 +96,7 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, apicid_8111, 0xd); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_8111, 0xe); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_8111, 0xf); - + //8111 LPC ???? smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sysconf.sbdn+1)<<2)|0, apicid_8111, 0x13); diff --git a/src/mainboard/tyan/s2881/resourcemap.c b/src/mainboard/tyan/s2881/resourcemap.c index cecb790795..23ab936a5b 100644 --- a/src/mainboard/tyan/s2881/resourcemap.c +++ b/src/mainboard/tyan/s2881/resourcemap.c @@ -144,7 +144,7 @@ static void setup_s2881_resource_map(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, @@ -200,7 +200,7 @@ static void setup_s2881_resource_map(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -208,7 +208,7 @@ static void setup_s2881_resource_map(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003, diff --git a/src/mainboard/tyan/s2881/romstage.c b/src/mainboard/tyan/s2881/romstage.c index 1310c8e99b..0a63486ffb 100644 --- a/src/mainboard/tyan/s2881/romstage.c +++ b/src/mainboard/tyan/s2881/romstage.c @@ -3,7 +3,7 @@ #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 #endif - + #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -117,7 +117,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } // post_code(0x32); - + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/tyan/s2882/devicetree.cb b/src/mainboard/tyan/s2882/devicetree.cb index d563232b2d..b8cbce2858 100644 --- a/src/mainboard/tyan/s2882/devicetree.cb +++ b/src/mainboard/tyan/s2882/devicetree.cb @@ -7,7 +7,7 @@ chip northbridge/amd/amdk8/root_complex device pci_domain 0 on chip northbridge/amd/amdk8 - device pci 18.0 on # northbridge + device pci 18.0 on # northbridge # devices on link 0, link 0 == LDT 0 chip southbridge/amd/amd8131 # the on/off keyword is mandatory @@ -67,7 +67,7 @@ chip northbridge/amd/amdk8/root_complex io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 - end + end device pnp 2e.8 off end # GPIO2 device pnp 2e.9 off end # GPIO3 device pnp 2e.a off end # ACPI @@ -80,13 +80,13 @@ chip northbridge/amd/amdk8/root_complex device pci 1.1 on end device pci 1.2 on end device pci 1.3 on end - device pci 1.3 on + device pci 1.3 on # chip drivers/generic/generic #dimm 0-0-0 # device i2c 50 on end # end # chip drivers/generic/generic #dimm 0-0-1 # device i2c 51 on end -# end +# end # chip drivers/generic/generic #dimm 0-1-0 # device i2c 52 on end # end @@ -111,11 +111,11 @@ chip northbridge/amd/amdk8/root_complex register "ide0_enable" = "1" register "ide1_enable" = "1" end - end # device pci 18.0 - + end # device pci 18.0 + device pci 18.0 on end device pci 18.0 on end - + device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end diff --git a/src/mainboard/tyan/s2882/irq_tables.c b/src/mainboard/tyan/s2882/irq_tables.c index 3107ac8a87..4ddd63eecb 100644 --- a/src/mainboard/tyan/s2882/irq_tables.c +++ b/src/mainboard/tyan/s2882/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up @@ -63,7 +63,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) dst_node = (config_map >> 4) & 7; dst_link = (config_map >> 8) & 3; bus_base = (config_map >> 16) & 0xff; -#if 0 +#if 0 printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", dst_node, dst_link, bus_base, reg, config_map); @@ -76,11 +76,11 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) return 0; } -static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, +static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; + pirq_info->bus = bus; pirq_info->devfn = devfn; pirq_info->irq[0].link = link0; pirq_info->irq[0].bitmap = bitmap0; @@ -162,15 +162,15 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq = (void *)(addr); v = (uint8_t *)(addr); - + pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - + pirq->rtr_bus = bus_chain_0; pirq->rtr_devfn = (4<<3)|3; pirq->exclusive_irqs = 0; - + pirq->rtr_vendor = 0x1022; pirq->rtr_device = 0x746b; @@ -186,7 +186,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x04,3)); if (dev) { /* initialize PCI interupts - these assignments depend - on the PCB routing of PINTA-D + on the PCB routing of PINTA-D PINTA = IRQ5 PINTB = IRQ9 @@ -202,7 +202,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pci_assign_irqs(bus_chain_0, 4, slotIrqs_1_4); write_pirq_info(pirq_info, bus_chain_0,(4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; - + printk(BIOS_DEBUG, "setting Onboard AMD USB \n"); static const unsigned char slotIrqs_8111_1_0[4] = { 0, 0, 0, 10 }; pci_assign_irqs(bus_8111_1, 0, slotIrqs_8111_1_0); @@ -279,16 +279,16 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq_info++; slot_num++; #endif -#if 0 +#if 0 //?? what's this? write_pirq_info(pirq_info, bus_8131_2,(5<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 0x7, 0); pirq_info++; slot_num++; #endif - - pirq->size = 32 + 16 * slot_num; + + pirq->size = 32 + 16 * slot_num; for (i = 0; i < pirq->size; i++) - sum += v[i]; + sum += v[i]; sum = pirq->checksum - sum; diff --git a/src/mainboard/tyan/s2882/mptable.c b/src/mainboard/tyan/s2882/mptable.c index f1d7a27179..43ccef6276 100644 --- a/src/mainboard/tyan/s2882/mptable.c +++ b/src/mainboard/tyan/s2882/mptable.c @@ -30,7 +30,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) dst_node = (config_map >> 4) & 7; dst_link = (config_map >> 8) & 3; bus_base = (config_map >> 16) & 0xff; -#if 0 +#if 0 printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", dst_node, dst_link, bus_base, reg, config_map); @@ -60,7 +60,7 @@ static void *smp_write_config_table(void *v) unsigned apicid_8111; unsigned apicid_8131_1; unsigned apicid_8131_2; - + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); @@ -95,8 +95,8 @@ static void *smp_write_config_table(void *v) bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa++; - } - else { + } + else { printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n"); bus_8111_1 = 4; @@ -137,9 +137,9 @@ static void *smp_write_config_table(void *v) #if CONFIG_LOGICAL_CPUS==1 apicid_base = get_apicid_base(3); #else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif - apicid_8111 = apicid_base+0; + apicid_8111 = apicid_base+0; apicid_8131_1 = apicid_base+1; apicid_8131_2 = apicid_base+2; @@ -163,7 +163,7 @@ static void *smp_write_config_table(void *v) } } - + /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_8111, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_8111, 0x1); @@ -180,7 +180,7 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chain_0, (4<<2)|3, apicid_8111, 0x13); - + //On Board AMD USB smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13); @@ -209,7 +209,7 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|2, apicid_8131_1, 0x1);// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|3, apicid_8131_1, 0x2);// -//Slot 4 PCIX 100/66 +//Slot 4 PCIX 100/66 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|0, apicid_8131_1, 0x2); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|1, apicid_8131_1, 0x3);// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|2, apicid_8131_1, 0x0);// diff --git a/src/mainboard/tyan/s2882/romstage.c b/src/mainboard/tyan/s2882/romstage.c index c49dff9f10..d8816d4cff 100644 --- a/src/mainboard/tyan/s2882/romstage.c +++ b/src/mainboard/tyan/s2882/romstage.c @@ -1,4 +1,4 @@ - + #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -129,7 +129,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) init_cpus(cpu_init_detectedx); } - + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -140,7 +140,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_default_resource_map(); needs_reset = setup_coherent_ht_domain(); - + #if CONFIG_LOGICAL_CPUS==1 // It is said that we should start core1 after all core0 launched start_other_cores(); diff --git a/src/mainboard/tyan/s2885/devicetree.cb b/src/mainboard/tyan/s2885/devicetree.cb index f8dc2215d9..7cdc728fbb 100644 --- a/src/mainboard/tyan/s2885/devicetree.cb +++ b/src/mainboard/tyan/s2885/devicetree.cb @@ -14,11 +14,11 @@ chip northbridge/amd/amdk8/root_complex end end device pci 18.0 on end # LDT1 - device pci 18.0 on # northbridge + device pci 18.0 on # northbridge # devices on link 2, link 2 == LDT 2 chip southbridge/amd/amd8131 # the on/off keyword is mandatory - device pci 0.0 on + device pci 0.0 on device pci 9.0 on end # broadcom 5703 end device pci 0.1 on end @@ -67,7 +67,7 @@ chip northbridge/amd/amdk8/root_complex io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 - end + end device pnp 2e.8 off end # GPIO2 device pnp 2e.9 off end # GPIO3 device pnp 2e.a off end # ACPI @@ -82,36 +82,36 @@ chip northbridge/amd/amdk8/root_complex device pci 1.3 on chip drivers/generic/generic #dimm 0-0-0 device i2c 50 on end - end + end chip drivers/generic/generic #dimm 0-0-1 device i2c 51 on end - end + end chip drivers/generic/generic #dimm 0-1-0 device i2c 52 on end - end + end chip drivers/generic/generic #dimm 0-1-1 device i2c 53 on end - end + end chip drivers/generic/generic #dimm 1-0-0 device i2c 54 on end - end + end chip drivers/generic/generic #dimm 1-0-1 device i2c 55 on end end chip drivers/generic/generic #dimm 1-1-0 device i2c 56 on end - end + end chip drivers/generic/generic #dimm 1-1-1 device i2c 57 on end - end + end end # acpi device pci 1.5 on end device pci 1.6 off end register "ide0_enable" = "1" register "ide1_enable" = "1" end - end # device pci 18.0 - + end # device pci 18.0 + device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end @@ -119,9 +119,9 @@ chip northbridge/amd/amdk8/root_complex end #pci_domain -# chip drivers/generic/debug +# chip drivers/generic/debug # device pnp 0.0 off end -# device pnp 0.1 off end +# device pnp 0.1 off end # device pnp 0.2 off end # device pnp 0.3 off end # device pnp 0.4 off end diff --git a/src/mainboard/tyan/s2885/get_bus_conf.c b/src/mainboard/tyan/s2885/get_bus_conf.c index de4deb23d3..a511afa395 100644 --- a/src/mainboard/tyan/s2885/get_bus_conf.c +++ b/src/mainboard/tyan/s2885/get_bus_conf.c @@ -24,7 +24,7 @@ unsigned apicid_8111 ; unsigned apicid_8131_1; unsigned apicid_8131_2; -unsigned pci1234x[] = +unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail 0x0000ff0, @@ -36,7 +36,7 @@ unsigned pci1234x[] = // 0x0000ff0, // 0x0000ff0 }; -unsigned hcdnx[] = +unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, 0x20202020, @@ -73,7 +73,7 @@ void get_bus_conf(void) } get_sblk_pci1234(); - + sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff; sbdn3 = sysconf.hcdn[0] & 0xff; sbdn5 = sysconf.hcdn[1] & 0xff; @@ -135,8 +135,8 @@ void get_bus_conf(void) /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS==1 apicid_base = get_apicid_base(3); -#else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; +#else + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif apicid_8111 = apicid_base+0; apicid_8131_1 = apicid_base+1; diff --git a/src/mainboard/tyan/s2885/irq_tables.c b/src/mainboard/tyan/s2885/irq_tables.c index f9a358e125..b272fda532 100644 --- a/src/mainboard/tyan/s2885/irq_tables.c +++ b/src/mainboard/tyan/s2885/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up @@ -12,11 +12,11 @@ #include <cpu/amd/amdk8_sysconf.h> -static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, +static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; + pirq_info->bus = bus; pirq_info->devfn = devfn; pirq_info->irq[0].link = link0; pirq_info->irq[0].bitmap = bitmap0; @@ -65,22 +65,22 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq = (void *)(addr); v = (uint8_t *)(addr); - + pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - + pirq->rtr_bus = bus_8111_0; pirq->rtr_devfn = ((sysconf.sbdn+1)<<3)|0; pirq->exclusive_irqs = 0; - + pirq->rtr_vendor = 0x1022; pirq->rtr_device = 0x746b; pirq->miniport_data = 0; memset(pirq->rfu, 0, sizeof(pirq->rfu)); - + pirq_info = (void *) ( &pirq->checksum + 1); slot_num = 0; //pci bridge @@ -90,14 +90,14 @@ unsigned long write_pirq_routing_table(unsigned long addr) // write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); // pirq_info++; slot_num++; //agp bridge - write_pirq_info(pirq_info, bus_8151_0, (sbdn5<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); + write_pirq_info(pirq_info, bus_8151_0, (sbdn5<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; - - pirq->size = 32 + 16 * slot_num; + + pirq->size = 32 + 16 * slot_num; for (i = 0; i < pirq->size; i++) - sum += v[i]; + sum += v[i]; sum = pirq->checksum - sum; diff --git a/src/mainboard/tyan/s2885/mptable.c b/src/mainboard/tyan/s2885/mptable.c index d096b07905..87c812fb13 100644 --- a/src/mainboard/tyan/s2885/mptable.c +++ b/src/mainboard/tyan/s2885/mptable.c @@ -83,7 +83,7 @@ static void *smp_write_config_table(void *v) } } } - + /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_8111, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_8111, 0x1); @@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_8111, 0xf); //??? What smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sysconf.sbdn+1)<<2)|3, apicid_8111, 0x13); -//Onboard AMD AC97 Audio +//Onboard AMD AC97 Audio smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sysconf.sbdn+1)<<2)|1, apicid_8111, 0x11); // Onboard AMD USB smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13); @@ -108,7 +108,7 @@ static void *smp_write_config_table(void *v) // AGP Display Adapter smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8151_1, 0x0, apicid_8111, 0x10); -//Onboard Serial ATA +//Onboard Serial ATA smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0b<<2)|0, apicid_8111, 0x11); //Onboard Firewire smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0c<<2)|0, apicid_8111, 0x13); @@ -127,7 +127,7 @@ static void *smp_write_config_table(void *v) } -//Slot 4 PCIX 100/66 +//Slot 4 PCIX 100/66 for(i=0;i<4;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|i, apicid_8131_1, (2+i)%4); //26 } diff --git a/src/mainboard/tyan/s2885/resourcemap.c b/src/mainboard/tyan/s2885/resourcemap.c index 4a686020c8..af0ccabeb8 100644 --- a/src/mainboard/tyan/s2885/resourcemap.c +++ b/src/mainboard/tyan/s2885/resourcemap.c @@ -144,7 +144,7 @@ static void setup_s2885_resource_map(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, @@ -200,7 +200,7 @@ static void setup_s2885_resource_map(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -208,7 +208,7 @@ static void setup_s2885_resource_map(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003, diff --git a/src/mainboard/tyan/s2885/romstage.c b/src/mainboard/tyan/s2885/romstage.c index 7513c14e1b..f7ea579f6e 100644 --- a/src/mainboard/tyan/s2885/romstage.c +++ b/src/mainboard/tyan/s2885/romstage.c @@ -1,4 +1,4 @@ - + #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -71,7 +71,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" /* tyan does not want the default */ -#include "resourcemap.c" +#include "resourcemap.c" #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 @@ -119,13 +119,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } // post_code(0x32); - + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - + /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/tyan/s2891/resourcemap.c b/src/mainboard/tyan/s2891/resourcemap.c index f7929b96c0..d76f1d6f47 100644 --- a/src/mainboard/tyan/s2891/resourcemap.c +++ b/src/mainboard/tyan/s2891/resourcemap.c @@ -144,7 +144,7 @@ static void setup_s2891_resource_map(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, @@ -182,7 +182,7 @@ static void setup_s2891_resource_map(void) * [31:25] Reserved */ // PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000, - PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, @@ -200,7 +200,7 @@ static void setup_s2891_resource_map(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -208,7 +208,7 @@ static void setup_s2891_resource_map(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033, @@ -254,8 +254,8 @@ static void setup_s2891_resource_map(void) */ // PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, /* link 0 of cpu 0 --> Nvidia CK 804 Pro */ // PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, /* link 2 of cpu 0 --> AMD8131 */ - PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, }; diff --git a/src/mainboard/tyan/s2892/dsdt.asl b/src/mainboard/tyan/s2892/dsdt.asl index 63a94bb932..d4242c3dc2 100644 --- a/src/mainboard/tyan/s2892/dsdt.asl +++ b/src/mainboard/tyan/s2892/dsdt.asl @@ -6,22 +6,22 @@ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * + * the Free Software Foundation; version 2 of the License. + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - + /* * ISA portions taken from QEMU acpi-dsdt.dsl. */ - + DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1) { #include "northbridge/amd/amdk8/amdk8_util.asl" diff --git a/src/mainboard/tyan/s2895/dsdt.asl b/src/mainboard/tyan/s2895/dsdt.asl index 268929fd9d..b3ac536d28 100644 --- a/src/mainboard/tyan/s2895/dsdt.asl +++ b/src/mainboard/tyan/s2895/dsdt.asl @@ -6,22 +6,22 @@ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * + * the Free Software Foundation; version 2 of the License. + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - + /* * ISA portions taken from QEMU acpi-dsdt.dsl. */ - + DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1) { #include "northbridge/amd/amdk8/amdk8_util.asl" diff --git a/src/mainboard/tyan/s2912/Kconfig b/src/mainboard/tyan/s2912/Kconfig index 18fa5e2bc3..c2a7ed00dd 100644 --- a/src/mainboard/tyan/s2912/Kconfig +++ b/src/mainboard/tyan/s2912/Kconfig @@ -15,7 +15,7 @@ config BOARD_TYAN_S2912 select LIFT_BSP_APIC_ID select K8_REV_F_SUPPORT select BOARD_ROMSIZE_KB_512 - + config MAINBOARD_DIR string default tyan/s2912 @@ -25,7 +25,7 @@ config DCACHE_RAM_BASE hex default 0xc8000 depends on BOARD_TYAN_S2912 - + config DCACHE_RAM_SIZE hex default 0x08000 @@ -37,7 +37,7 @@ config DCACHE_RAM_GLOBAL_VAR_SIZE depends on BOARD_TYAN_S2912 config APIC_ID_OFFSET - hex + hex default 0x10 depends on BOARD_TYAN_S2912 @@ -77,7 +77,7 @@ config MAX_PHYSICAL_CPUS depends on BOARD_TYAN_S2912 config HW_MEM_HOLE_SIZE_AUTO_INC - bool + bool default n depends on BOARD_TYAN_S2912 @@ -87,12 +87,12 @@ config HT_CHAIN_UNITID_BASE depends on BOARD_TYAN_S2912 config HT_CHAIN_END_UNITID_BASE - hex + hex default 0x20 depends on BOARD_TYAN_S2912 config SERIAL_CPU_INIT - bool + bool default n depends on BOARD_TYAN_S2912 diff --git a/src/mainboard/tyan/s2912/ap_romstage.c b/src/mainboard/tyan/s2912/ap_romstage.c index a477b6891d..41a4a6ee8d 100644 --- a/src/mainboard/tyan/s2912/ap_romstage.c +++ b/src/mainboard/tyan/s2912/ap_romstage.c @@ -25,7 +25,7 @@ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 -#define SET_NB_CFG_54 1 +#define SET_NB_CFG_54 1 //used by raminit #define QRANK_DIMM_SUPPORT 1 diff --git a/src/mainboard/tyan/s2912/get_bus_conf.c b/src/mainboard/tyan/s2912/get_bus_conf.c index b21b1af4a7..9ff59d24ab 100644 --- a/src/mainboard/tyan/s2912/get_bus_conf.c +++ b/src/mainboard/tyan/s2912/get_bus_conf.c @@ -35,7 +35,7 @@ struct mb_sysconf_t mb_sysconf; unsigned pci1234x[] = -{ +{ // Here you only need to set value in pci1234 for HT-IO that could be // installed or not. // You may need to preset pci1234 for HTIO board, please refer to @@ -50,7 +50,7 @@ unsigned pci1234x[] = // 0x0000ff0 }; unsigned hcdnx[] = -{ +{ // HT Chain device num, actually it is unit id base of every ht device // in chain, assume every chain only have 4 ht device at most 0x20202020, diff --git a/src/mainboard/tyan/s2912/mb_sysconf.h b/src/mainboard/tyan/s2912/mb_sysconf.h index 83f9dbab28..a2e6fc7ade 100644 --- a/src/mainboard/tyan/s2912/mb_sysconf.h +++ b/src/mainboard/tyan/s2912/mb_sysconf.h @@ -26,7 +26,7 @@ struct mb_sysconf_t { unsigned char bus_isa; unsigned char bus_mcp55[8]; //1 unsigned apicid_mcp55; - unsigned bus_type[256]; + unsigned bus_type[256]; }; diff --git a/src/mainboard/tyan/s2912_fam10/irq_tables.c b/src/mainboard/tyan/s2912_fam10/irq_tables.c index bb14f3310b..a1de4c4f57 100644 --- a/src/mainboard/tyan/s2912_fam10/irq_tables.c +++ b/src/mainboard/tyan/s2912_fam10/irq_tables.c @@ -19,7 +19,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! * (but if you do, please run checkpir on it to verify) * Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up @@ -34,11 +34,11 @@ #include <cpu/amd/amdfam10_sysconf.h> #include "mb_sysconf.h" -static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, +static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; + pirq_info->bus = bus; pirq_info->devfn = devfn; pirq_info->irq[0].link = link0; pirq_info->irq[0].bitmap = bitmap0; @@ -80,15 +80,15 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq = (void *)(addr); v = (uint8_t *)(addr); - + pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - + pirq->rtr_bus = m->bus_mcp55[0]; pirq->rtr_devfn = ((sbdn+6)<<3)|0; pirq->exclusive_irqs = 0; - + pirq->rtr_vendor = 0x10de; pirq->rtr_device = 0x0370; @@ -101,7 +101,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) //pci bridge write_pirq_info(pirq_info, m->bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; - + for(i=1; i< sysconf.hc_possible_num; i++) { if(!(sysconf.pci1234[i] & 0x1) ) continue; unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff; @@ -120,10 +120,10 @@ unsigned long write_pirq_routing_table(unsigned long addr) } #endif - pirq->size = 32 + 16 * slot_num; + pirq->size = 32 + 16 * slot_num; for (i = 0; i < pirq->size; i++) - sum += v[i]; + sum += v[i]; sum = pirq->checksum - sum; diff --git a/src/mainboard/tyan/s2912_fam10/mb_sysconf.h b/src/mainboard/tyan/s2912_fam10/mb_sysconf.h index 83f9dbab28..a2e6fc7ade 100644 --- a/src/mainboard/tyan/s2912_fam10/mb_sysconf.h +++ b/src/mainboard/tyan/s2912_fam10/mb_sysconf.h @@ -26,7 +26,7 @@ struct mb_sysconf_t { unsigned char bus_isa; unsigned char bus_mcp55[8]; //1 unsigned apicid_mcp55; - unsigned bus_type[256]; + unsigned bus_type[256]; }; diff --git a/src/mainboard/tyan/s4880/devicetree.cb b/src/mainboard/tyan/s4880/devicetree.cb index 4a08e45d1b..4c2f2b59f4 100644 --- a/src/mainboard/tyan/s4880/devicetree.cb +++ b/src/mainboard/tyan/s4880/devicetree.cb @@ -9,7 +9,7 @@ chip northbridge/amd/amdk8/root_complex chip northbridge/amd/amdk8 device pci 18.0 on end # LDT0 device pci 18.0 on end # LDT1 - device pci 18.0 on # northbridge + device pci 18.0 on # northbridge # devices on link 2, link 2 == LDT 2 chip southbridge/amd/amd8131 # the on/off keyword is mandatory @@ -68,7 +68,7 @@ chip northbridge/amd/amdk8/root_complex io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 - end + end device pnp 2e.8 off end # GPIO2 device pnp 2e.9 off end # GPIO3 device pnp 2e.a off end # ACPI @@ -86,8 +86,8 @@ chip northbridge/amd/amdk8/root_complex register "ide0_enable" = "1" register "ide1_enable" = "1" end - end # device pci 18.0 - + end # device pci 18.0 + device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end diff --git a/src/mainboard/tyan/s4880/irq_tables.c b/src/mainboard/tyan/s4880/irq_tables.c index e95038dc37..352a7411e1 100644 --- a/src/mainboard/tyan/s4880/irq_tables.c +++ b/src/mainboard/tyan/s4880/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up diff --git a/src/mainboard/tyan/s4880/mptable.c b/src/mainboard/tyan/s4880/mptable.c index 746d2a5d5e..a5094ba042 100644 --- a/src/mainboard/tyan/s4880/mptable.c +++ b/src/mainboard/tyan/s4880/mptable.c @@ -28,7 +28,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) dst_node = (config_map >> 4) & 7; dst_link = (config_map >> 8) & 3; bus_base = (config_map >> 16) & 0xff; -#if 0 +#if 0 printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", dst_node, dst_link, bus_base, reg, config_map); @@ -58,7 +58,7 @@ static void *smp_write_config_table(void *v) unsigned apicid_8111; unsigned apicid_8131_1; unsigned apicid_8131_2; - + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); @@ -78,7 +78,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); - + { device_t dev; @@ -88,14 +88,14 @@ static void *smp_write_config_table(void *v) printk(BIOS_DEBUG, "ERROR - cound not find bus for node 0 chain 0, using defaults\n"); bus_chain_0 = 1; } - + /* 8111 */ dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0)); if (dev) { bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_isa++; - } + bus_isa++; + } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n"); @@ -133,14 +133,14 @@ static void *smp_write_config_table(void *v) } smp_write_bus(mc, bus_isa, "ISA "); - + /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS==1 apicid_base = get_apicid_base(3); -#else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; +#else + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif - apicid_8111 = apicid_base+0; + apicid_8111 = apicid_base+0; apicid_8131_1 = apicid_base+1; apicid_8131_2 = apicid_base+2; @@ -164,7 +164,7 @@ static void *smp_write_config_table(void *v) } } - + /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_8111, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_8111, 0x1); @@ -182,7 +182,7 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, apicid_8111, 0xd); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_8111, 0xe); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_8111, 0xf); - + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chain_0, (4<<2)|0, apicid_8111, 0x13); @@ -214,7 +214,7 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|2, apicid_8131_1, 0x1);// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|3, apicid_8131_1, 0x2);// -//Slot 3 PCIX 100/66 +//Slot 3 PCIX 100/66 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|0, apicid_8131_1, 0x2); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|1, apicid_8131_1, 0x3);// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|2, apicid_8131_1, 0x0);// diff --git a/src/mainboard/tyan/s4880/resourcemap.c b/src/mainboard/tyan/s4880/resourcemap.c index cf45d55532..5fa85784ab 100644 --- a/src/mainboard/tyan/s4880/resourcemap.c +++ b/src/mainboard/tyan/s4880/resourcemap.c @@ -144,7 +144,7 @@ static void setup_s4880_resource_map(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, @@ -200,7 +200,7 @@ static void setup_s4880_resource_map(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -208,7 +208,7 @@ static void setup_s4880_resource_map(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003, diff --git a/src/mainboard/tyan/s4880/romstage.c b/src/mainboard/tyan/s4880/romstage.c index 9933303278..753328c062 100644 --- a/src/mainboard/tyan/s4880/romstage.c +++ b/src/mainboard/tyan/s4880/romstage.c @@ -1,4 +1,4 @@ - + #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -65,7 +65,7 @@ static inline void change_i2c_mux(unsigned device) { #define SMBUS_HUB 0x18 int ret; - print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n"); + print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n"); ret = smbus_write_byte(SMBUS_HUB, 0x01, device); print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n"); ret = smbus_write_byte(SMBUS_HUB, 0x03, 0); @@ -85,7 +85,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" /* tyan does not want the default */ -#include "resourcemap.c" +#include "resourcemap.c" #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 @@ -185,7 +185,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_s4880_resource_map(); needs_reset = setup_coherent_ht_domain(); - + #if CONFIG_LOGICAL_CPUS==1 // It is said that we should start core1 after all core0 launched start_other_cores(); diff --git a/src/mainboard/tyan/s4882/devicetree.cb b/src/mainboard/tyan/s4882/devicetree.cb index d2e5bbcf90..66f8c73e00 100644 --- a/src/mainboard/tyan/s4882/devicetree.cb +++ b/src/mainboard/tyan/s4882/devicetree.cb @@ -7,11 +7,11 @@ chip northbridge/amd/amdk8/root_complex device pci_domain 0 on chip northbridge/amd/amdk8 device pci 18.0 on end # LDT0 - device pci 18.0 on # northbridge + device pci 18.0 on # northbridge # devices on link 1, link 1 == LDT 1 chip southbridge/amd/amd8131 # the on/off keyword is mandatory - device pci 0.0 on + device pci 0.0 on # chip drivers/lsi/53c1030 # device pci 4.0 on end # device pci 4.1 on end @@ -69,7 +69,7 @@ chip northbridge/amd/amdk8/root_complex io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 - end + end device pnp 2e.8 off end # GPIO2 device pnp 2e.9 off end # GPIO3 device pnp 2e.a off end # ACPI @@ -81,12 +81,12 @@ chip northbridge/amd/amdk8/root_complex end device pci 1.1 on end device pci 1.2 on end - device pci 1.3 on + device pci 1.3 on # chip drivers/i2c/i2cmux # pca9556 smbus mux # device i2c 18 on #0 pca9516 2, 1 # chip drivers/i2c/lm63 #cpu0 temp # device i2c 4c on end -# end +# end # end # device i2c 18 on #1 pca9516 1, 1 # chip drivers/generic/generic #dimm 1-0-0 @@ -163,7 +163,7 @@ chip northbridge/amd/amdk8/root_complex # chip drivers/i2c/adm1027 # ADM1027 CPU1 vid and System FAN... # device i2c 2e on end # end -# chip drivers/generic/generic # Winbond HWM 0x54 CPU0 vid +# chip drivers/generic/generic # Winbond HWM 0x54 CPU0 vid # device i2c 2a on end # end # chip drivers/generic/generic # Winbond HWM 0x92 @@ -181,16 +181,16 @@ chip northbridge/amd/amdk8/root_complex register "ide0_enable" = "1" register "ide1_enable" = "1" end - end # device pci 18.0 - + end # device pci 18.0 + device pci 18.0 on end - + device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end end - end + end # chip drivers/generic/debug # device pnp 0.0 off end # chip name # device pnp 0.1 off end # pci_regs_all diff --git a/src/mainboard/tyan/s4882/irq_tables.c b/src/mainboard/tyan/s4882/irq_tables.c index 4552b1f69c..92695abf7b 100644 --- a/src/mainboard/tyan/s4882/irq_tables.c +++ b/src/mainboard/tyan/s4882/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up diff --git a/src/mainboard/tyan/s4882/mptable.c b/src/mainboard/tyan/s4882/mptable.c index 4022dbdde1..81364262b7 100644 --- a/src/mainboard/tyan/s4882/mptable.c +++ b/src/mainboard/tyan/s4882/mptable.c @@ -29,7 +29,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) dst_node = (config_map >> 4) & 7; dst_link = (config_map >> 8) & 3; bus_base = (config_map >> 16) & 0xff; -#if 0 +#if 0 printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", dst_node, dst_link, bus_base, reg, config_map); @@ -59,7 +59,7 @@ static void *smp_write_config_table(void *v) unsigned apicid_8111; unsigned apicid_8131_1; unsigned apicid_8131_2; - + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); @@ -79,24 +79,24 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); - + { device_t dev; - + /* HT chain 0 */ bus_chain_0 = node_link_to_bus(0, 1); if (bus_chain_0 == 0) { printk(BIOS_DEBUG, "ERROR - cound not find bus for node 0 chain 0, using defaults\n"); bus_chain_0 = 1; } - + /* 8111 */ dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0)); if (dev) { bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_isa++; - } + bus_isa++; + } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n"); @@ -134,14 +134,14 @@ static void *smp_write_config_table(void *v) } smp_write_bus(mc, bus_isa, "ISA "); - + /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS==1 apicid_base = get_apicid_base(3); -#else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; +#else + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif - apicid_8111 = apicid_base+0; + apicid_8111 = apicid_base+0; apicid_8131_1 = apicid_base+1; apicid_8131_2 = apicid_base+2; smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000); @@ -164,7 +164,7 @@ static void *smp_write_config_table(void *v) } } - + /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_8111, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_8111, 0x1); @@ -182,7 +182,7 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, apicid_8111, 0xd); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_8111, 0xe); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_8111, 0xf); - + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chain_0, (4<<2)|0, apicid_8111, 0x13); @@ -214,7 +214,7 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|2, apicid_8131_1, 0x1);// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|3, apicid_8131_1, 0x2);// -//Slot 3 PCIX 100/66 +//Slot 3 PCIX 100/66 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|0, apicid_8131_1, 0x2); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|1, apicid_8131_1, 0x3);// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|2, apicid_8131_1, 0x0);// diff --git a/src/mainboard/tyan/s4882/resourcemap.c b/src/mainboard/tyan/s4882/resourcemap.c index 0e5be61a7c..2ee274960d 100644 --- a/src/mainboard/tyan/s4882/resourcemap.c +++ b/src/mainboard/tyan/s4882/resourcemap.c @@ -144,7 +144,7 @@ static void setup_s4882_resource_map(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, @@ -200,7 +200,7 @@ static void setup_s4882_resource_map(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -208,7 +208,7 @@ static void setup_s4882_resource_map(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003, diff --git a/src/mainboard/tyan/s4882/romstage.c b/src/mainboard/tyan/s4882/romstage.c index e1931fc2d4..9bec9de58b 100644 --- a/src/mainboard/tyan/s4882/romstage.c +++ b/src/mainboard/tyan/s4882/romstage.c @@ -1,4 +1,4 @@ - + #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -70,7 +70,7 @@ static inline void change_i2c_mux(unsigned device) { #define SMBUS_HUB 0x18 int ret, i; - print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n"); + print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n"); i=2; do { ret = smbus_write_byte(SMBUS_HUB, 0x01, device); @@ -93,7 +93,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" /* tyan does not want the default */ -#include "resourcemap.c" +#include "resourcemap.c" #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 @@ -155,7 +155,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) bsp_apicid = init_cpus(cpu_init_detectedx); } - + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -187,7 +187,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) nodes = get_nodes(); //It's the time to set ctrl now; fill_mem_ctrl(nodes, ctrl, spd_addr); - + enable_smbus(); memreset_setup(); diff --git a/src/mainboard/via/epia-cn/romstage.c b/src/mainboard/via/epia-cn/romstage.c index 74cd29a5f4..6d37e6bdf9 100644 --- a/src/mainboard/via/epia-cn/romstage.c +++ b/src/mainboard/via/epia-cn/romstage.c @@ -47,7 +47,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void enable_mainboard_devices(void) { device_t dev; - + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); if (dev == PCI_DEV_INVALID) die("Southbridge not found!!!\n"); diff --git a/src/mainboard/via/epia-m/acpi_tables.c b/src/mainboard/via/epia-m/acpi_tables.c index 69c526c1fe..9e42bc25a5 100644 --- a/src/mainboard/via/epia-m/acpi_tables.c +++ b/src/mainboard/via/epia-m/acpi_tables.c @@ -1,7 +1,7 @@ /* * coreboot ACPI Table support * written by Stefan Reinauer <stepan@openbios.org> - * ACPI FADT, FACS, and DSDT table support added by + * ACPI FADT, FACS, and DSDT table support added by * Nick Barker <nick.barker9@btinternet.com>, and those portions * (C) Copyright 2004 Nick Barker * (C) Copyright 2005 Stefan Reinauer @@ -45,11 +45,11 @@ unsigned long write_acpi_tables(unsigned long start) acpi_fadt_t *fadt; acpi_facs_t *facs; acpi_header_t *dsdt; - + /* Align ACPI tables to 16byte */ start = ( start + 0x0f ) & -0x10; current = start; - + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); /* We need at least an RSDP and an RSDT Table */ @@ -60,10 +60,10 @@ unsigned long write_acpi_tables(unsigned long start) /* clear all table memory */ memset((void *)start, 0, current - start); - + acpi_write_rsdp(rsdp, rsdt, NULL); acpi_write_rsdt(rsdt); - + /* * We explicitly add these tables later on: */ diff --git a/src/mainboard/via/epia-m/devicetree.cb b/src/mainboard/via/epia-m/devicetree.cb index e49090e789..ed543a21aa 100644 --- a/src/mainboard/via/epia-m/devicetree.cb +++ b/src/mainboard/via/epia-m/devicetree.cb @@ -2,7 +2,7 @@ chip northbridge/via/vt8623 device apic_cluster 0 on chip cpu/via/model_c3 - device apic 0 on end + device apic 0 on end end end @@ -44,7 +44,7 @@ chip northbridge/via/vt8623 end end - + device pci 11.1 on end # IDE # 2-4 non existant? device pci 11.5 on end # AC97 Audio @@ -55,7 +55,7 @@ chip northbridge/via/vt8623 chip southbridge/ricoh/rl5c476 register "enable_cf" = "1" device pci 0a.0 on end - device pci 0a.1 on end + device pci 0a.1 on end end end end diff --git a/src/mainboard/via/epia-m/dsdt.asl b/src/mainboard/via/epia-m/dsdt.asl index b1b791d5f2..cbc8d24e41 100644 --- a/src/mainboard/via/epia-m/dsdt.asl +++ b/src/mainboard/via/epia-m/dsdt.asl @@ -2,12 +2,12 @@ * Minimalist ACPI DSDT table for EPIA-M / MII * (C) Copyright 2004 Nick Barker <Nick.Barker9@btinternet.com> * - * + * */ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) { - /* + /* * Define the main processor */ Scope (\_PR) @@ -26,7 +26,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) /* Root of the bus hierarchy */ Scope (\_SB) { - /* Define how interrupt Link A is plumbed in */ + /* Define how interrupt Link A is plumbed in */ Device (LNKA) { Name (_HID, EisaId ("PNP0C0F")) @@ -36,7 +36,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) { Return (0x0B) } - /* Current Resources - return irq set up in BIOS */ + /* Current Resources - return irq set up in BIOS */ Method (_CRS, 0, NotSerialized) { Name (BUFF, ResourceTemplate () @@ -47,7 +47,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) } /* Possible Resources - return the range of irqs * we are using for PCI - only here to keep Linux ACPI - * happy + * happy */ Method (_PRS, 0, NotSerialized) { @@ -59,16 +59,16 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) } /* Set Resources - dummy function to keep Linux ACPI happy * Linux is more than happy not to tinker with irq - * assignments as long as the CRS and STA functions + * assignments as long as the CRS and STA functions * return good values */ Method (_SRS, 1, NotSerialized ) {} /* Disable - dummy function to keep Linux ACPI happy */ Method (_DIS, 0, NotSerialized ) {} - - } // End of LNKA - /* Define how interrupt Link B is plumbed in */ + } // End of LNKA + + /* Define how interrupt Link B is plumbed in */ Device (LNKB) { Name (_HID, EisaId ("PNP0C0F")) @@ -78,7 +78,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) { Return (0x0B) } - /* Current Resources - return irq set up in BIOS */ + /* Current Resources - return irq set up in BIOS */ Method (_CRS, 0, NotSerialized) { Name (BUFF, ResourceTemplate () @@ -89,7 +89,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) } /* Possible Resources - return the range of irqs * we are using for PCI - only here to keep Linux ACPI - * happy + * happy */ Method (_PRS, 0, NotSerialized) { @@ -101,16 +101,16 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) } /* Set Resources - dummy function to keep Linux ACPI happy * Linux is more than happy not to tinker with irq - * assignments as long as the CRS and STA functions + * assignments as long as the CRS and STA functions * return good values */ Method (_SRS, 1, NotSerialized ) {} /* Disable - dummy function to keep Linux ACPI happy */ Method (_DIS, 0, NotSerialized ) {} - + } // End of LNKB - /* Define how interrupt Link C is plumbed in */ + /* Define how interrupt Link C is plumbed in */ Device (LNKC) { Name (_HID, EisaId ("PNP0C0F")) @@ -120,7 +120,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) { Return (0x0B) } - /* Current Resources - return irq set up in BIOS */ + /* Current Resources - return irq set up in BIOS */ Method (_CRS, 0, NotSerialized) { Name (BUFF, ResourceTemplate () @@ -131,7 +131,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) } /* Possible Resources - return the range of irqs * we are using for PCI - only here to keep Linux ACPI - * happy + * happy */ Method (_PRS, 0, NotSerialized) { @@ -143,16 +143,16 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) } /* Set Resources - dummy function to keep Linux ACPI happy * Linux is more than happy not to tinker with irq - * assignments as long as the CRS and STA functions + * assignments as long as the CRS and STA functions * return good values */ Method (_SRS, 1, NotSerialized ) {} /* Disable - dummy function to keep Linux ACPI happy */ Method (_DIS, 0, NotSerialized ) {} - + } // End of LNKC - /* Define how interrupt Link D is plumbed in */ + /* Define how interrupt Link D is plumbed in */ Device (LNKD) { Name (_HID, EisaId ("PNP0C0F")) @@ -162,7 +162,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) { Return (0x0B) } - /* Current Resources - return irq set up in BIOS */ + /* Current Resources - return irq set up in BIOS */ Method (_CRS, 0, NotSerialized) { Name (BUFF, ResourceTemplate () @@ -173,7 +173,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) } /* Possible Resources - return the range of irqs * we are using for PCI - only here to keep Linux ACPI - * happy + * happy */ Method (_PRS, 0, NotSerialized) { @@ -185,16 +185,16 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) } /* Set Resources - dummy function to keep Linux ACPI happy * Linux is more than happy not to tinker with irq - * assignments as long as the CRS and STA functions + * assignments as long as the CRS and STA functions * return good values */ Method (_SRS, 1, NotSerialized ) {} /* Disable - dummy function to keep Linux ACPI happy */ Method (_DIS, 0, NotSerialized ) {} - - } // End of LNKD - + } // End of LNKD + + /* top PCI device */ Device (PCI0) { @@ -226,12 +226,12 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) Package () {0x0011FFFF, 0x02, LNKC, 0x00}, // vt8623 Link C Package () {0x0011FFFF, 0x03, LNKD, 0x00}, // vt8623 Link D - Package () {0x0012FFFF, 0x00, LNKA, 0x00}, // LAN Link A + Package () {0x0012FFFF, 0x00, LNKA, 0x00}, // LAN Link A Package () {0x0012FFFF, 0x01, LNKB, 0x00}, // LAN Link B Package () {0x0012FFFF, 0x02, LNKC, 0x00}, // LAN Link C Package () {0x0012FFFF, 0x03, LNKD, 0x00}, // LAN Link D - Package () {0x0013FFFF, 0x00, LNKA, 0x00}, // Riser slot LinkA + Package () {0x0013FFFF, 0x00, LNKA, 0x00}, // Riser slot LinkA Package () {0x0013FFFF, 0x01, LNKB, 0x00}, // Riser slot LinkB Package () {0x0013FFFF, 0x02, LNKC, 0x00}, // Riser slot LinkC Package () {0x0013FFFF, 0x03, LNKD, 0x00}, // Riser slot LinkD @@ -240,7 +240,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) Package () {0x0014FFFF, 0x01, LNKC, 0x00}, // Slot 1, Link C Package () {0x0014FFFF, 0x02, LNKD, 0x00}, // Slot 1, Link D Package () {0x0014FFFF, 0x03, LNKA, 0x00}, // Slot 1, Link A - + Package () {0x0001FFFF, 0x00, LNKA, 0x00}, // VGA Link A Package () {0x0001FFFF, 0x01, LNKB, 0x00}, // VGA Link B Package () {0x0001FFFF, 0x02, LNKC, 0x00}, // VGA Link C diff --git a/src/mainboard/via/epia-m/dsdt.c b/src/mainboard/via/epia-m/dsdt.c index fa878250f5..ca40651973 100644 --- a/src/mainboard/via/epia-m/dsdt.c +++ b/src/mainboard/via/epia-m/dsdt.c @@ -1,12 +1,12 @@ /* - * + * * Intel ACPI Component Architecture * ASL Optimizing Compiler version 20060127 [Apr 23 2006] * Copyright (C) 2000 - 2006 Intel Corporation * Supports ACPI Specification Revision 3.0a - * + * * Compilation of "dsdt.asl" - Wed Sep 6 11:36:08 2006 - * + * * C source code output * */ diff --git a/src/mainboard/via/epia-m/irq_tables.c b/src/mainboard/via/epia-m/irq_tables.c index 551db214a8..f7776f6d20 100644 --- a/src/mainboard/via/epia-m/irq_tables.c +++ b/src/mainboard/via/epia-m/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up * diff --git a/src/mainboard/via/epia-m/romstage.c b/src/mainboard/via/epia-m/romstage.c index 6a8446ac04..54feb26552 100644 --- a/src/mainboard/via/epia-m/romstage.c +++ b/src/mainboard/via/epia-m/romstage.c @@ -26,27 +26,27 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/via/vt8623/raminit.c" -static void enable_mainboard_devices(void) +static void enable_mainboard_devices(void) { device_t dev; - + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235), 0); - + if (dev == PCI_DEV_INVALID) { die("Southbridge not found!!!\n"); } pci_write_config8(dev, 0x50, 0x80); pci_write_config8(dev, 0x51, 0x1f); #if 0 - // This early setup switches IDE into compatibility mode before PCI gets + // This early setup switches IDE into compatibility mode before PCI gets // a chance to assign I/Os // movl $CONFIG_ADDR(0, 0x89, 0x42), %eax // // movb $0x09, %dl // movb $0x00, %dl // PCI_WRITE_CONFIG_BYTE #endif - /* we do this here as in V2, we can not yet do raw operations + /* we do this here as in V2, we can not yet do raw operations * to pci! */ dev += 0x100; /* ICKY */ @@ -58,7 +58,7 @@ static void enable_mainboard_devices(void) pci_write_config8(dev, 0x3d, 0); } -static void enable_shadow_ram(void) +static void enable_shadow_ram(void) { device_t dev = 0; /* no need to look up 0:0.0 */ unsigned char shadowreg; @@ -108,7 +108,7 @@ static void main(unsigned long bist) enable_shadow_ram(); ddr_ram_setup((const struct mem_controller *)0); - + /* Check all of memory */ #if 0 static const struct { @@ -129,7 +129,7 @@ static void main(unsigned long bist) } //dump_pci_devices(); - + print_spew("Leaving romstage.c:main()\n"); } diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c index 2e51c958d0..ac2e202d6a 100644 --- a/src/mainboard/via/epia-m700/romstage.c +++ b/src/mainboard/via/epia-m700/romstage.c @@ -547,7 +547,7 @@ void main(unsigned long bist) /* * For coreboot most time of S3 resume is the same as normal boot, * so some memory area under 1M become dirty, so before this happen, - * I need to backup the content of mem to top-mem. + * I need to backup the content of mem to top-mem. * * I will reserve the 1M top-men in LBIO table in coreboot_table.c * and recovery the content of 1M-mem in wakeup.c. @@ -628,7 +628,7 @@ void main(unsigned long bist) ); #endif - /* + /* * WAKE_MEM_INFO is inited in get_set_top_available_mem() * in tables.c these two memcpy() not not be enabled if set * the MTRR around this two lines. diff --git a/src/mainboard/via/epia-n/acpi_tables.c b/src/mainboard/via/epia-n/acpi_tables.c index 1944b18de6..7cfa15114c 100644 --- a/src/mainboard/via/epia-n/acpi_tables.c +++ b/src/mainboard/via/epia-n/acpi_tables.c @@ -1,7 +1,7 @@ /* * coreboot ACPI Table support * written by Stefan Reinauer <stepan@openbios.org> - * ACPI FADT, FACS, and DSDT table support added by + * ACPI FADT, FACS, and DSDT table support added by * Nick Barker <nick.barker9@btinternet.com>, and those portions * (C) Copyright 2004 Nick Barker * (C) Copyright 2005 Stefan Reinauer @@ -130,11 +130,11 @@ unsigned long write_acpi_tables(unsigned long start) acpi_fadt_t *fadt; acpi_facs_t *facs; acpi_header_t *dsdt; - + /* Align ACPI tables to 16byte */ start = ( start + 0x0f ) & -0x10; current = start; - + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); /* We need at least an RSDP and an RSDT Table */ @@ -145,10 +145,10 @@ unsigned long write_acpi_tables(unsigned long start) /* clear all table memory */ memset((void *)start, 0, current - start); - + acpi_write_rsdp(rsdp, rsdt, NULL); acpi_write_rsdt(rsdt); - + /* * We explicitly add these tables later on: */ diff --git a/src/mainboard/via/epia-n/dsdt.asl b/src/mainboard/via/epia-n/dsdt.asl index 90731501ed..e50ee6b50c 100644 --- a/src/mainboard/via/epia-n/dsdt.asl +++ b/src/mainboard/via/epia-n/dsdt.asl @@ -3,7 +3,7 @@ * (C) Copyright 2009 Jon Harrison <jon.harrison@blueyonder.co.uk> * Heavily based on EPIA-M dstd.asl * (C) Copyright 2004 Nick Barker <Nick.Barker9@btinternet.com> - * + * */ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CBT-V2", "CBT-DSDT", 1) { diff --git a/src/mainboard/via/epia-n/romstage.c b/src/mainboard/via/epia-n/romstage.c index 6ca72f293e..df9f82ea9b 100644 --- a/src/mainboard/via/epia-n/romstage.c +++ b/src/mainboard/via/epia-n/romstage.c @@ -41,8 +41,8 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) /* - * NOOB :: - * d0f0 - Device 0 Function 0 etc. + * NOOB :: + * d0f0 - Device 0 Function 0 etc. */ static const struct mem_controller ctrl = { .d0f0 = 0x0000, @@ -65,7 +65,7 @@ static void enable_mainboard_devices(void) { device_t dev; u8 reg; - + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); if (dev == PCI_DEV_INVALID) die("Southbridge not found!!!\n"); @@ -95,10 +95,10 @@ static void enable_mainboard_devices(void) pci_write_config8(dev, 0x51, 0x9d); } -static void enable_shadow_ram(void) +static void enable_shadow_ram(void) { unsigned char shadowreg; - + shadowreg = pci_read_config8(ctrl.d0f3, 0x82); /* 0xf0000-0xfffff Read/Write*/ shadowreg |= 0x30; @@ -133,10 +133,10 @@ static void main(unsigned long bist) print_debug("Enable F-ROM Shadow RAM\n"); enable_shadow_ram(); - + /* setup cpu */ print_debug("Setup CPU Interface\n"); - c3_cpu_setup(ctrl.d0f2); + c3_cpu_setup(ctrl.d0f2); ddr_ram_setup(); @@ -144,7 +144,7 @@ static void main(unsigned long bist) print_debug("doing early_mtrr\n"); early_mtrr_init(); } - + //ram_check(0, 640 * 1024); print_spew("Leaving romstage.c:main()\n"); diff --git a/src/mainboard/via/epia/irq_tables.c b/src/mainboard/via/epia/irq_tables.c index f3978d5e81..8b4352d25a 100644 --- a/src/mainboard/via/epia/irq_tables.c +++ b/src/mainboard/via/epia/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up diff --git a/src/mainboard/via/epia/romstage.c b/src/mainboard/via/epia/romstage.c index 202b117a42..66a8d203ed 100644 --- a/src/mainboard/via/epia/romstage.c +++ b/src/mainboard/via/epia/romstage.c @@ -27,13 +27,13 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" */ -static void enable_mainboard_devices(void) +static void enable_mainboard_devices(void) { device_t dev; /* dev 0 for southbridge */ - + dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0); - + if (dev == PCI_DEV_INVALID) { die("Southbridge not found!!!\n"); } @@ -41,7 +41,7 @@ static void enable_mainboard_devices(void) pci_write_config8(dev, 0x50, 7); pci_write_config8(dev, 0x51, 0xff); #if 0 - // This early setup switches IDE into compatibility mode before PCI gets + // This early setup switches IDE into compatibility mode before PCI gets // a chance to assign I/Os // movl $CONFIG_ADDR(0, 0x89, 0x42), %eax // movb $0x09, %dl @@ -49,7 +49,7 @@ static void enable_mainboard_devices(void) // PCI_WRITE_CONFIG_BYTE // #endif - /* we do this here as in V2, we can not yet do raw operations + /* we do this here as in V2, we can not yet do raw operations * to pci! */ /* changed this to work correctly on later revisions of LB. @@ -64,7 +64,7 @@ static void enable_mainboard_devices(void) pci_write_config8(dev, 0x42, 0); } -static void enable_shadow_ram(void) +static void enable_shadow_ram(void) { device_t dev = 0; unsigned char shadowreg; @@ -86,7 +86,7 @@ static void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - + enable_mainboard_devices(); enable_smbus(); enable_shadow_ram(); @@ -98,7 +98,7 @@ static void main(unsigned long bist) sdram_set_registers((const struct mem_controller *) 0); sdram_set_spd_registers((const struct mem_controller *) 0); sdram_enable(0, (const struct mem_controller *) 0); - + /* Check all of memory */ #if 0 ram_check(0x00000000, msr.lo); diff --git a/src/mainboard/via/vt8454c/acpi/irq-p2p-bridge.asl b/src/mainboard/via/vt8454c/acpi/irq-p2p-bridge.asl index 4a294bcbaa..1505683563 100644 --- a/src/mainboard/via/vt8454c/acpi/irq-p2p-bridge.asl +++ b/src/mainboard/via/vt8454c/acpi/irq-p2p-bridge.asl @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or @@ -22,67 +22,67 @@ Name (PICM, Package () { // _ADR PIN SRC IDX - Package () { 0x0003FFFF, 0x00, LNKA, 0x00 }, - Package () { 0x0003FFFF, 0x01, LNKB, 0x00 }, - Package () { 0x0003FFFF, 0x02, LNKC, 0x00 }, - Package () { 0x0003FFFF, 0x03, LNKD, 0x00 }, - - Package () { 0x0004FFFF, 0x00, LNKB, 0x00 }, - Package () { 0x0004FFFF, 0x01, LNKC, 0x00 }, - Package () { 0x0004FFFF, 0x02, LNKD, 0x00 }, - Package () { 0x0004FFFF, 0x03, LNKA, 0x00 }, - - Package () { 0x0005FFFF, 0x00, LNKC, 0x00 }, - Package () { 0x0005FFFF, 0x01, LNKD, 0x00 }, - Package () { 0x0005FFFF, 0x02, LNKA, 0x00 }, - Package () { 0x0005FFFF, 0x03, LNKB, 0x00 }, - - Package () { 0x0006FFFF, 0x00, LNKD, 0x00 }, - Package () { 0x0006FFFF, 0x01, LNKA, 0x00 }, - Package () { 0x0006FFFF, 0x02, LNKB, 0x00 }, - Package () { 0x0006FFFF, 0x03, LNKC, 0x00 }, - - Package () { 0x0007FFFF, 0x00, LNKA, 0x00 }, - Package () { 0x0007FFFF, 0x01, LNKB, 0x00 }, - Package () { 0x0007FFFF, 0x02, LNKC, 0x00 }, - Package () { 0x0007FFFF, 0x03, LNKD, 0x00 }, - - Package () { 0x0008FFFF, 0x00, LNKB, 0x00 }, - Package () { 0x0008FFFF, 0x01, LNKC, 0x00 }, - Package () { 0x0008FFFF, 0x02, LNKD, 0x00 }, - Package () { 0x0008FFFF, 0x03, LNKA, 0x00 }, + Package () { 0x0003FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0003FFFF, 0x01, LNKB, 0x00 }, + Package () { 0x0003FFFF, 0x02, LNKC, 0x00 }, + Package () { 0x0003FFFF, 0x03, LNKD, 0x00 }, + + Package () { 0x0004FFFF, 0x00, LNKB, 0x00 }, + Package () { 0x0004FFFF, 0x01, LNKC, 0x00 }, + Package () { 0x0004FFFF, 0x02, LNKD, 0x00 }, + Package () { 0x0004FFFF, 0x03, LNKA, 0x00 }, + + Package () { 0x0005FFFF, 0x00, LNKC, 0x00 }, + Package () { 0x0005FFFF, 0x01, LNKD, 0x00 }, + Package () { 0x0005FFFF, 0x02, LNKA, 0x00 }, + Package () { 0x0005FFFF, 0x03, LNKB, 0x00 }, + + Package () { 0x0006FFFF, 0x00, LNKD, 0x00 }, + Package () { 0x0006FFFF, 0x01, LNKA, 0x00 }, + Package () { 0x0006FFFF, 0x02, LNKB, 0x00 }, + Package () { 0x0006FFFF, 0x03, LNKC, 0x00 }, + + Package () { 0x0007FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0007FFFF, 0x01, LNKB, 0x00 }, + Package () { 0x0007FFFF, 0x02, LNKC, 0x00 }, + Package () { 0x0007FFFF, 0x03, LNKD, 0x00 }, + + Package () { 0x0008FFFF, 0x00, LNKB, 0x00 }, + Package () { 0x0008FFFF, 0x01, LNKC, 0x00 }, + Package () { 0x0008FFFF, 0x02, LNKD, 0x00 }, + Package () { 0x0008FFFF, 0x03, LNKA, 0x00 }, }) Name (APIC, Package () { - Package () { 0x0003FFFF, 0x00, 0x00, 0x10 }, - Package () { 0x0003FFFF, 0x01, 0x00, 0x11 }, - Package () { 0x0003FFFF, 0x02, 0x00, 0x12 }, - Package () { 0x0003FFFF, 0x03, 0x00, 0x13 }, + Package () { 0x0003FFFF, 0x00, 0x00, 0x10 }, + Package () { 0x0003FFFF, 0x01, 0x00, 0x11 }, + Package () { 0x0003FFFF, 0x02, 0x00, 0x12 }, + Package () { 0x0003FFFF, 0x03, 0x00, 0x13 }, - Package () { 0x0004FFFF, 0x00, 0x00, 0x11 }, - Package () { 0x0004FFFF, 0x01, 0x00, 0x12 }, - Package () { 0x0004FFFF, 0x02, 0x00, 0x13 }, - Package () { 0x0004FFFF, 0x03, 0x00, 0x10 }, + Package () { 0x0004FFFF, 0x00, 0x00, 0x11 }, + Package () { 0x0004FFFF, 0x01, 0x00, 0x12 }, + Package () { 0x0004FFFF, 0x02, 0x00, 0x13 }, + Package () { 0x0004FFFF, 0x03, 0x00, 0x10 }, - Package () { 0x0005FFFF, 0x00, 0x00, 0x12 }, - Package () { 0x0005FFFF, 0x01, 0x00, 0x13 }, - Package () { 0x0005FFFF, 0x02, 0x00, 0x10 }, - Package () { 0x0005FFFF, 0x03, 0x00, 0x11 }, + Package () { 0x0005FFFF, 0x00, 0x00, 0x12 }, + Package () { 0x0005FFFF, 0x01, 0x00, 0x13 }, + Package () { 0x0005FFFF, 0x02, 0x00, 0x10 }, + Package () { 0x0005FFFF, 0x03, 0x00, 0x11 }, - Package () { 0x0006FFFF, 0x00, 0x00, 0x13 }, - Package () { 0x0006FFFF, 0x01, 0x00, 0x10 }, - Package () { 0x0006FFFF, 0x02, 0x00, 0x11 }, - Package () { 0x0006FFFF, 0x03, 0x00, 0x12 }, + Package () { 0x0006FFFF, 0x00, 0x00, 0x13 }, + Package () { 0x0006FFFF, 0x01, 0x00, 0x10 }, + Package () { 0x0006FFFF, 0x02, 0x00, 0x11 }, + Package () { 0x0006FFFF, 0x03, 0x00, 0x12 }, - Package () { 0x0007FFFF, 0x00, 0x00, 0x10 }, - Package () { 0x0007FFFF, 0x01, 0x00, 0x11 }, - Package () { 0x0007FFFF, 0x02, 0x00, 0x12 }, - Package () { 0x0007FFFF, 0x03, 0x00, 0x13 }, + Package () { 0x0007FFFF, 0x00, 0x00, 0x10 }, + Package () { 0x0007FFFF, 0x01, 0x00, 0x11 }, + Package () { 0x0007FFFF, 0x02, 0x00, 0x12 }, + Package () { 0x0007FFFF, 0x03, 0x00, 0x13 }, - Package () { 0x0008FFFF, 0x00, 0x00, 0x11 }, - Package () { 0x0008FFFF, 0x01, 0x00, 0x12 }, - Package () { 0x0008FFFF, 0x02, 0x00, 0x13 }, - Package () { 0x0008FFFF, 0x03, 0x00, 0x10 }, + Package () { 0x0008FFFF, 0x00, 0x00, 0x11 }, + Package () { 0x0008FFFF, 0x01, 0x00, 0x12 }, + Package () { 0x0008FFFF, 0x02, 0x00, 0x13 }, + Package () { 0x0008FFFF, 0x03, 0x00, 0x10 }, }) diff --git a/src/mainboard/via/vt8454c/acpi/irq.asl b/src/mainboard/via/vt8454c/acpi/irq.asl index 63e64e61c0..a0bc380b78 100644 --- a/src/mainboard/via/vt8454c/acpi/irq.asl +++ b/src/mainboard/via/vt8454c/acpi/irq.asl @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or @@ -22,122 +22,122 @@ Name (PICM, Package () { // _ADR PIN SRC IDX - Package () { 0x0001FFFF, 0x00, LNKA, 0x00 }, - Package () { 0x0001FFFF, 0x01, LNKB, 0x00 }, - Package () { 0x0001FFFF, 0x02, LNKC, 0x00 }, - Package () { 0x0001FFFF, 0x03, LNKD, 0x00 }, - - Package () { 0x0008FFFF, 0x00, LNKB, 0x00 }, - Package () { 0x0008FFFF, 0x01, LNKC, 0x00 }, - Package () { 0x0008FFFF, 0x02, LNKD, 0x00 }, - Package () { 0x0008FFFF, 0x03, LNKA, 0x00 }, - - Package () { 0x0009FFFF, 0x00, LNKC, 0x00 }, - Package () { 0x0009FFFF, 0x01, LNKD, 0x00 }, - Package () { 0x0009FFFF, 0x02, LNKA, 0x00 }, - Package () { 0x0009FFFF, 0x03, LNKB, 0x00 }, - - Package () { 0x000AFFFF, 0x00, LNKD, 0x00 }, - Package () { 0x000AFFFF, 0x01, LNKA, 0x00 }, - Package () { 0x000AFFFF, 0x02, LNKB, 0x00 }, - Package () { 0x000AFFFF, 0x03, LNKC, 0x00 }, - - Package () { 0x000BFFFF, 0x00, LNKD, 0x00 }, - Package () { 0x000BFFFF, 0x01, LNKA, 0x00 }, - Package () { 0x000BFFFF, 0x02, LNKB, 0x00 }, - Package () { 0x000BFFFF, 0x03, LNKC, 0x00 }, - - Package () { 0x000CFFFF, 0x00, LNKA, 0x00 }, - Package () { 0x000CFFFF, 0x01, LNKB, 0x00 }, - Package () { 0x000CFFFF, 0x02, LNKC, 0x00 }, - Package () { 0x000CFFFF, 0x03, LNKD, 0x00 }, - - Package () { 0x000DFFFF, 0x00, LNKA, 0x00 }, - Package () { 0x000DFFFF, 0x01, LNKB, 0x00 }, - Package () { 0x000DFFFF, 0x02, LNKC, 0x00 }, - Package () { 0x000DFFFF, 0x03, LNKD, 0x00 }, - - Package () { 0x000FFFFF, 0x00, LNKA, 0x00 }, - Package () { 0x000FFFFF, 0x01, LNKB, 0x00 }, - Package () { 0x000FFFFF, 0x02, LNKC, 0x00 }, + Package () { 0x0001FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0001FFFF, 0x01, LNKB, 0x00 }, + Package () { 0x0001FFFF, 0x02, LNKC, 0x00 }, + Package () { 0x0001FFFF, 0x03, LNKD, 0x00 }, + + Package () { 0x0008FFFF, 0x00, LNKB, 0x00 }, + Package () { 0x0008FFFF, 0x01, LNKC, 0x00 }, + Package () { 0x0008FFFF, 0x02, LNKD, 0x00 }, + Package () { 0x0008FFFF, 0x03, LNKA, 0x00 }, + + Package () { 0x0009FFFF, 0x00, LNKC, 0x00 }, + Package () { 0x0009FFFF, 0x01, LNKD, 0x00 }, + Package () { 0x0009FFFF, 0x02, LNKA, 0x00 }, + Package () { 0x0009FFFF, 0x03, LNKB, 0x00 }, + + Package () { 0x000AFFFF, 0x00, LNKD, 0x00 }, + Package () { 0x000AFFFF, 0x01, LNKA, 0x00 }, + Package () { 0x000AFFFF, 0x02, LNKB, 0x00 }, + Package () { 0x000AFFFF, 0x03, LNKC, 0x00 }, + + Package () { 0x000BFFFF, 0x00, LNKD, 0x00 }, + Package () { 0x000BFFFF, 0x01, LNKA, 0x00 }, + Package () { 0x000BFFFF, 0x02, LNKB, 0x00 }, + Package () { 0x000BFFFF, 0x03, LNKC, 0x00 }, + + Package () { 0x000CFFFF, 0x00, LNKA, 0x00 }, + Package () { 0x000CFFFF, 0x01, LNKB, 0x00 }, + Package () { 0x000CFFFF, 0x02, LNKC, 0x00 }, + Package () { 0x000CFFFF, 0x03, LNKD, 0x00 }, + + Package () { 0x000DFFFF, 0x00, LNKA, 0x00 }, + Package () { 0x000DFFFF, 0x01, LNKB, 0x00 }, + Package () { 0x000DFFFF, 0x02, LNKC, 0x00 }, + Package () { 0x000DFFFF, 0x03, LNKD, 0x00 }, + + Package () { 0x000FFFFF, 0x00, LNKA, 0x00 }, + Package () { 0x000FFFFF, 0x01, LNKB, 0x00 }, + Package () { 0x000FFFFF, 0x02, LNKC, 0x00 }, Package () { 0x000FFFFF, 0x03, LNKD, 0x00 }, - + /* USB controller */ - Package () { 0x0010FFFF, 0x00, LNKA, 0x00 }, - Package () { 0x0010FFFF, 0x01, LNKB, 0x00 }, - Package () { 0x0010FFFF, 0x02, LNKC, 0x00 }, - Package () { 0x0010FFFF, 0x03, LNKD, 0x00 }, - - Package () { 0x0011FFFF, 0x00, LNKA, 0x00 }, - Package () { 0x0011FFFF, 0x01, LNKB, 0x00 }, - Package () { 0x0011FFFF, 0x02, LNKC, 0x00 }, - Package () { 0x0011FFFF, 0x03, LNKD, 0x00 }, - - Package () { 0x0012FFFF, 0x00, LNKA, 0x00 }, - Package () { 0x0012FFFF, 0x01, LNKB, 0x00 }, - Package () { 0x0012FFFF, 0x02, LNKC, 0x00 }, - Package () { 0x0012FFFF, 0x03, LNKD, 0x00 } + Package () { 0x0010FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0010FFFF, 0x01, LNKB, 0x00 }, + Package () { 0x0010FFFF, 0x02, LNKC, 0x00 }, + Package () { 0x0010FFFF, 0x03, LNKD, 0x00 }, + + Package () { 0x0011FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0011FFFF, 0x01, LNKB, 0x00 }, + Package () { 0x0011FFFF, 0x02, LNKC, 0x00 }, + Package () { 0x0011FFFF, 0x03, LNKD, 0x00 }, + + Package () { 0x0012FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0012FFFF, 0x01, LNKB, 0x00 }, + Package () { 0x0012FFFF, 0x02, LNKC, 0x00 }, + Package () { 0x0012FFFF, 0x03, LNKD, 0x00 } }) Name (APIC, Package () { - Package () { 0x0001FFFF, 0x00, 0x00, 0x10 }, - Package () { 0x0001FFFF, 0x01, 0x00, 0x11 }, - Package () { 0x0001FFFF, 0x02, 0x00, 0x12 }, - Package () { 0x0001FFFF, 0x03, 0x00, 0x13 }, - - Package () { 0x0008FFFF, 0x00, 0x00, 0x11 }, - Package () { 0x0008FFFF, 0x01, 0x00, 0x12 }, - Package () { 0x0008FFFF, 0x02, 0x00, 0x13 }, - Package () { 0x0008FFFF, 0x03, 0x00, 0x10 }, - - Package () { 0x0009FFFF, 0x00, 0x00, 0x12 }, - Package () { 0x0009FFFF, 0x01, 0x00, 0x13 }, - Package () { 0x0009FFFF, 0x02, 0x00, 0x10 }, - Package () { 0x0009FFFF, 0x03, 0x00, 0x11 }, - - Package () { 0x000AFFFF, 0x00, 0x00, 0x13 }, - Package () { 0x000AFFFF, 0x01, 0x00, 0x10 }, - Package () { 0x000AFFFF, 0x02, 0x00, 0x11 }, - Package () { 0x000AFFFF, 0x03, 0x00, 0x12 }, - - Package () { 0x000BFFFF, 0x00, 0x00, 0x13 }, - Package () { 0x000BFFFF, 0x01, 0x00, 0x10 }, - Package () { 0x000BFFFF, 0x02, 0x00, 0x11 }, - Package () { 0x000BFFFF, 0x03, 0x00, 0x12 }, - - Package () { 0x000CFFFF, 0x00, 0x00, 0x10 }, - Package () { 0x000CFFFF, 0x01, 0x00, 0x11 }, - Package () { 0x000CFFFF, 0x02, 0x00, 0x12 }, - Package () { 0x000CFFFF, 0x03, 0x00, 0x13 }, - - Package () { 0x000DFFFF, 0x00, 0x00, 0x10 }, - Package () { 0x000DFFFF, 0x01, 0x00, 0x11 }, - Package () { 0x000DFFFF, 0x02, 0x00, 0x12 }, - Package () { 0x000DFFFF, 0x03, 0x00, 0x13 }, - - Package () { 0x000FFFFF, 0x00, LNKA, 0x00 }, - Package () { 0x000FFFFF, 0x01, LNKA, 0x00 }, - Package () { 0x000FFFFF, 0x02, LNKA, 0x00 }, + Package () { 0x0001FFFF, 0x00, 0x00, 0x10 }, + Package () { 0x0001FFFF, 0x01, 0x00, 0x11 }, + Package () { 0x0001FFFF, 0x02, 0x00, 0x12 }, + Package () { 0x0001FFFF, 0x03, 0x00, 0x13 }, + + Package () { 0x0008FFFF, 0x00, 0x00, 0x11 }, + Package () { 0x0008FFFF, 0x01, 0x00, 0x12 }, + Package () { 0x0008FFFF, 0x02, 0x00, 0x13 }, + Package () { 0x0008FFFF, 0x03, 0x00, 0x10 }, + + Package () { 0x0009FFFF, 0x00, 0x00, 0x12 }, + Package () { 0x0009FFFF, 0x01, 0x00, 0x13 }, + Package () { 0x0009FFFF, 0x02, 0x00, 0x10 }, + Package () { 0x0009FFFF, 0x03, 0x00, 0x11 }, + + Package () { 0x000AFFFF, 0x00, 0x00, 0x13 }, + Package () { 0x000AFFFF, 0x01, 0x00, 0x10 }, + Package () { 0x000AFFFF, 0x02, 0x00, 0x11 }, + Package () { 0x000AFFFF, 0x03, 0x00, 0x12 }, + + Package () { 0x000BFFFF, 0x00, 0x00, 0x13 }, + Package () { 0x000BFFFF, 0x01, 0x00, 0x10 }, + Package () { 0x000BFFFF, 0x02, 0x00, 0x11 }, + Package () { 0x000BFFFF, 0x03, 0x00, 0x12 }, + + Package () { 0x000CFFFF, 0x00, 0x00, 0x10 }, + Package () { 0x000CFFFF, 0x01, 0x00, 0x11 }, + Package () { 0x000CFFFF, 0x02, 0x00, 0x12 }, + Package () { 0x000CFFFF, 0x03, 0x00, 0x13 }, + + Package () { 0x000DFFFF, 0x00, 0x00, 0x10 }, + Package () { 0x000DFFFF, 0x01, 0x00, 0x11 }, + Package () { 0x000DFFFF, 0x02, 0x00, 0x12 }, + Package () { 0x000DFFFF, 0x03, 0x00, 0x13 }, + + Package () { 0x000FFFFF, 0x00, LNKA, 0x00 }, + Package () { 0x000FFFFF, 0x01, LNKA, 0x00 }, + Package () { 0x000FFFFF, 0x02, LNKA, 0x00 }, Package () { 0x000FFFFF, 0x03, LNKA, 0x00 }, /* USB controller. Hardwired in internal APIC mode, see PM pg. 137, "miscellaneous controls", footnote to "IDE interrupt select" */ - Package () { 0x0010FFFF, 0x00, 0x00, 0x14 }, - Package () { 0x0010FFFF, 0x01, 0x00, 0x16 }, - Package () { 0x0010FFFF, 0x02, 0x00, 0x15 }, - Package () { 0x0010FFFF, 0x03, 0x00, 0x17 }, - - Package () { 0x0011FFFF, 0x00, LNKA, 0x00 }, - Package () { 0x0011FFFF, 0x01, LNKB, 0x00 }, - Package () { 0x0011FFFF, 0x02, LNKC, 0x00 }, - Package () { 0x0011FFFF, 0x03, LNKD, 0x00 }, - - Package () { 0x0012FFFF, 0x00, LNKD, 0x00 }, - Package () { 0x0012FFFF, 0x01, LNKD, 0x00 }, - Package () { 0x0012FFFF, 0x02, LNKD, 0x00 }, - Package () { 0x0012FFFF, 0x03, LNKD, 0x00 }, + Package () { 0x0010FFFF, 0x00, 0x00, 0x14 }, + Package () { 0x0010FFFF, 0x01, 0x00, 0x16 }, + Package () { 0x0010FFFF, 0x02, 0x00, 0x15 }, + Package () { 0x0010FFFF, 0x03, 0x00, 0x17 }, + + Package () { 0x0011FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0011FFFF, 0x01, LNKB, 0x00 }, + Package () { 0x0011FFFF, 0x02, LNKC, 0x00 }, + Package () { 0x0011FFFF, 0x03, LNKD, 0x00 }, + + Package () { 0x0012FFFF, 0x00, LNKD, 0x00 }, + Package () { 0x0012FFFF, 0x01, LNKD, 0x00 }, + Package () { 0x0012FFFF, 0x02, LNKD, 0x00 }, + Package () { 0x0012FFFF, 0x03, LNKD, 0x00 }, }) diff --git a/src/mainboard/via/vt8454c/acpi_tables.c b/src/mainboard/via/vt8454c/acpi_tables.c index d31d8c55eb..737a5c8b12 100644 --- a/src/mainboard/via/vt8454c/acpi_tables.c +++ b/src/mainboard/via/vt8454c/acpi_tables.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or diff --git a/src/mainboard/via/vt8454c/dsdt.asl b/src/mainboard/via/vt8454c/dsdt.asl index ada6c95690..d0ec7db2d0 100644 --- a/src/mainboard/via/vt8454c/dsdt.asl +++ b/src/mainboard/via/vt8454c/dsdt.asl @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com> * Copyright (C) 2007-2009 coresystems GmbH * @@ -22,7 +22,7 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) { - /* + /* * Define the main processor */ Scope (\_PR) @@ -38,18 +38,18 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) Name (\_S0, Package () {0x00, 0x00, 0x00, 0x00 }) Name (\_S5, Package () {0x02, 0x02, 0x00, 0x00 }) - Scope (\) { - Name (PICF , 0) // Global flag indicating whether to use PIC or APIC mode + Scope (\) { + Name (PICF , 0) // Global flag indicating whether to use PIC or APIC mode Method ( _PIC,1) // The OS is calling this { Store( Arg0 , PICF) } - } // end of \ scope + } // end of \ scope /* Root of the bus hierarchy */ Scope (\_SB) { - /* Define how interrupt Link A is plumbed in */ + /* Define how interrupt Link A is plumbed in */ Device (LNKA) { Name (_HID, EisaId ("PNP0C0F")) @@ -61,7 +61,7 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) Return (0x0B) } - /* Current Resources - return irq set up in BIOS */ + /* Current Resources - return irq set up in BIOS */ Method (_CRS, 0, NotSerialized) { Name (CRSP, ResourceTemplate () { @@ -79,7 +79,7 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) } /* Possible Resources - return the range of irqs * we are using for PCI - only here to keep Linux ACPI - * happy + * happy */ Method (_PRS, 0, NotSerialized) { @@ -99,16 +99,16 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) } /* Set Resources - dummy function to keep Linux ACPI happy * Linux is more than happy not to tinker with irq - * assignments as long as the CRS and STA functions + * assignments as long as the CRS and STA functions * return good values */ Method (_SRS, 1, NotSerialized ) {} /* Disable - dummy function to keep Linux ACPI happy */ Method (_DIS, 0, NotSerialized ) {} - - } // End of LNKA - /* Define how interrupt Link B is plumbed in */ + } // End of LNKA + + /* Define how interrupt Link B is plumbed in */ Device (LNKB) { Name (_HID, EisaId ("PNP0C0F")) @@ -120,7 +120,7 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) Return (0x0B) } - /* Current Resources - return irq set up in BIOS */ + /* Current Resources - return irq set up in BIOS */ Method (_CRS, 0, NotSerialized) { Name (CRSP, ResourceTemplate () { @@ -138,7 +138,7 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) } /* Possible Resources - return the range of irqs * we are using for PCI - only here to keep Linux ACPI - * happy + * happy */ Method (_PRS, 0, NotSerialized) { @@ -159,16 +159,16 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) /* Set Resources - dummy function to keep Linux ACPI happy * Linux is more than happy not to tinker with irq - * assignments as long as the CRS and STA functions + * assignments as long as the CRS and STA functions * return good values */ Method (_SRS, 1, NotSerialized ) {} /* Disable - dummy function to keep Linux ACPI happy */ Method (_DIS, 0, NotSerialized ) {} - + } // End of LNKB - /* Define how interrupt Link C is plumbed in */ + /* Define how interrupt Link C is plumbed in */ Device (LNKC) { Name (_HID, EisaId ("PNP0C0F")) @@ -180,7 +180,7 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) Return (0x0B) } - /* Current Resources - return irq set up in BIOS */ + /* Current Resources - return irq set up in BIOS */ Method (_CRS, 0, NotSerialized) { Name (CRSP, ResourceTemplate () { @@ -198,7 +198,7 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) } /* Possible Resources - return the range of irqs * we are using for PCI - only here to keep Linux ACPI - * happy + * happy */ Method (_PRS, 0, NotSerialized) { @@ -219,16 +219,16 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) /* Set Resources - dummy function to keep Linux ACPI happy * Linux is more than happy not to tinker with irq - * assignments as long as the CRS and STA functions + * assignments as long as the CRS and STA functions * return good values */ Method (_SRS, 1, NotSerialized ) {} /* Disable - dummy function to keep Linux ACPI happy */ Method (_DIS, 0, NotSerialized ) {} - + } // End of LNKC - /* Define how interrupt Link D is plumbed in */ + /* Define how interrupt Link D is plumbed in */ Device (LNKD) { Name (_HID, EisaId ("PNP0C0F")) @@ -240,7 +240,7 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) Return (0x0B) } - /* Current Resources - return irq set up in BIOS */ + /* Current Resources - return irq set up in BIOS */ Method (_CRS, 0, NotSerialized) { Name (CRSP, ResourceTemplate () { @@ -258,7 +258,7 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) } /* Possible Resources - return the range of irqs * we are using for PCI - only here to keep Linux ACPI - * happy + * happy */ Method (_PRS, 0, NotSerialized) { @@ -279,14 +279,14 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) /* Set Resources - dummy function to keep Linux ACPI happy * Linux is more than happy not to tinker with irq - * assignments as long as the CRS and STA functions + * assignments as long as the CRS and STA functions * return good values */ Method (_SRS, 1, NotSerialized ) {} /* Disable - dummy function to keep Linux ACPI happy */ Method (_DIS, 0, NotSerialized ) {} - - } // End of LNKD + + } // End of LNKD /* PCI Root Bridge */ Device (PCI0) diff --git a/src/mainboard/via/vt8454c/romstage.c b/src/mainboard/via/vt8454c/romstage.c index dea85bc234..1a1efbf8f6 100644 --- a/src/mainboard/via/vt8454c/romstage.c +++ b/src/mainboard/via/vt8454c/romstage.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or @@ -49,7 +49,7 @@ static void enable_mainboard_devices(void) if (dev == PCI_DEV_INVALID) { die("LPC bridge not found!!!\n"); } - // Disable GP3 + // Disable GP3 pci_write_config8(dev, 0x98, 0x00); // Disable mc97 diff --git a/src/mainboard/winent/pl6064/devicetree.cb b/src/mainboard/winent/pl6064/devicetree.cb index 7f5a53fc29..713849a098 100644 --- a/src/mainboard/winent/pl6064/devicetree.cb +++ b/src/mainboard/winent/pl6064/devicetree.cb @@ -20,7 +20,7 @@ chip northbridge/amd/lx register "com2_address" = "0x2F8" register "com2_irq" = "3" register "unwanted_vpci[0]" = "0" # End of list has a zero - + device pci d.0 on end # Ethernet 4 device pci a.0 on end # Ethernet 1 device pci b.0 on end # Ethernet 2 |