diff options
Diffstat (limited to 'src/mainboard')
53 files changed, 66 insertions, 65 deletions
diff --git a/src/mainboard/asus/mew-am/Kconfig b/src/mainboard/asus/mew-am/Kconfig index 7f16c5b6be..37317815ea 100644 --- a/src/mainboard/asus/mew-am/Kconfig +++ b/src/mainboard/asus/mew-am/Kconfig @@ -23,7 +23,7 @@ config BOARD_ASUS_MEW_AM select ARCH_X86 select CPU_INTEL_SOCKET_PGA370 select NORTHBRIDGE_INTEL_I82810 - select SOUTHBRIDGE_INTEL_I82801XX + select SOUTHBRIDGE_INTEL_I82801AX select SUPERIO_SMSC_SMSCSUPERIO select ROMCC select HAVE_PIRQ_TABLE diff --git a/src/mainboard/asus/mew-am/devicetree.cb b/src/mainboard/asus/mew-am/devicetree.cb index 2ca0e68cda..016f6dbc51 100644 --- a/src/mainboard/asus/mew-am/devicetree.cb +++ b/src/mainboard/asus/mew-am/devicetree.cb @@ -7,7 +7,7 @@ chip northbridge/intel/i82810 # Northbridge device pci_domain 0 on # PCI domain device pci 0.0 on end # Graphics Memory Controller Hub (GMCH) device pci 1.0 on end # Chipset Graphics Controller (CGC) - chip southbridge/intel/i82801xx # Southbridge + chip southbridge/intel/i82801ax # Southbridge register "ide0_enable" = "1" register "ide1_enable" = "1" diff --git a/src/mainboard/asus/mew-am/romstage.c b/src/mainboard/asus/mew-am/romstage.c index a7f74c42f4..8751e0ec28 100644 --- a/src/mainboard/asus/mew-am/romstage.c +++ b/src/mainboard/asus/mew-am/romstage.c @@ -31,7 +31,7 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" -#include "southbridge/intel/i82801xx/i82801xx_early_smbus.c" +#include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" #include "northbridge/intel/i82810/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" diff --git a/src/mainboard/asus/mew-vm/Kconfig b/src/mainboard/asus/mew-vm/Kconfig index 616fb4bdde..f5cefd0df8 100644 --- a/src/mainboard/asus/mew-vm/Kconfig +++ b/src/mainboard/asus/mew-vm/Kconfig @@ -23,7 +23,7 @@ config BOARD_ASUS_MEW_VM select ARCH_X86 select CPU_INTEL_SOCKET_PGA370 select NORTHBRIDGE_INTEL_I82810 - select SOUTHBRIDGE_INTEL_I82801XX + select SOUTHBRIDGE_INTEL_I82801AX select SUPERIO_SMSC_LPC47B272 select ROMCC select HAVE_PIRQ_TABLE diff --git a/src/mainboard/asus/mew-vm/devicetree.cb b/src/mainboard/asus/mew-vm/devicetree.cb index 0dc4b6f468..a5415a2bfe 100644 --- a/src/mainboard/asus/mew-vm/devicetree.cb +++ b/src/mainboard/asus/mew-vm/devicetree.cb @@ -4,7 +4,7 @@ chip northbridge/intel/i82810 device pci 1.0 on # Onboard Video # device pci 1.0 on end end - chip southbridge/intel/i82801xx # Southbridge + chip southbridge/intel/i82801ax # Southbridge register "ide0_enable" = "1" register "ide1_enable" = "1" diff --git a/src/mainboard/asus/mew-vm/romstage.c b/src/mainboard/asus/mew-vm/romstage.c index d9473a5880..703cd87de5 100644 --- a/src/mainboard/asus/mew-vm/romstage.c +++ b/src/mainboard/asus/mew-vm/romstage.c @@ -38,7 +38,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, LPC47B272_SP1) -#include "southbridge/intel/i82801xx/i82801xx_early_smbus.c" +#include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" diff --git a/src/mainboard/dell/s1850/Kconfig b/src/mainboard/dell/s1850/Kconfig index 3f14662be4..aeb14a008a 100644 --- a/src/mainboard/dell/s1850/Kconfig +++ b/src/mainboard/dell/s1850/Kconfig @@ -3,7 +3,7 @@ config BOARD_DELL_S1850 select ARCH_X86 select CPU_INTEL_SOCKET_MPGA604 select NORTHBRIDGE_INTEL_E7520 - select SOUTHBRIDGE_INTEL_I82801ER + select SOUTHBRIDGE_INTEL_I82801EX select SOUTHBRIDGE_INTEL_PXHD select SUPERIO_NSC_PC8374 select ROMCC diff --git a/src/mainboard/dell/s1850/devicetree.cb b/src/mainboard/dell/s1850/devicetree.cb index 4e93a3aefb..ab95e54a7b 100644 --- a/src/mainboard/dell/s1850/devicetree.cb +++ b/src/mainboard/dell/s1850/devicetree.cb @@ -1,6 +1,6 @@ chip northbridge/intel/e7520 # mch device pci_domain 0 on - chip southbridge/intel/i82801er # i82801er + chip southbridge/intel/i82801ex # i82801er # USB ports device pci 1d.0 on end device pci 1d.1 on end diff --git a/src/mainboard/dell/s1850/romstage.c b/src/mainboard/dell/s1850/romstage.c index 5f62ce80a8..952c37c1cf 100644 --- a/src/mainboard/dell/s1850/romstage.c +++ b/src/mainboard/dell/s1850/romstage.c @@ -12,7 +12,7 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" -#include "southbridge/intel/i82801er/i82801er_early_smbus.c" +#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" #include "superio/nsc/pc8374/pc8374_early_init.c" #include "cpu/x86/lapic/boot_cpu.c" diff --git a/src/mainboard/digitallogic/adl855pc/Kconfig b/src/mainboard/digitallogic/adl855pc/Kconfig index fd109e9d64..58b9f6f034 100644 --- a/src/mainboard/digitallogic/adl855pc/Kconfig +++ b/src/mainboard/digitallogic/adl855pc/Kconfig @@ -3,7 +3,7 @@ config BOARD_DIGITALLOGIC_ADL855PC select ARCH_X86 select CPU_INTEL_SOCKET_MPGA479M select NORTHBRIDGE_INTEL_I855 - select SOUTHBRIDGE_INTEL_I82801DBM + select SOUTHBRIDGE_INTEL_I82801DX select SUPERIO_WINBOND_W83627HF select ROMCC select HAVE_PIRQ_TABLE diff --git a/src/mainboard/digitallogic/adl855pc/devicetree.cb b/src/mainboard/digitallogic/adl855pc/devicetree.cb index 0f600ac8f1..6846b4e59c 100644 --- a/src/mainboard/digitallogic/adl855pc/devicetree.cb +++ b/src/mainboard/digitallogic/adl855pc/devicetree.cb @@ -2,7 +2,7 @@ chip northbridge/intel/i855 device pci_domain 0 on device pci 0.0 on end device pci 1.0 on end - chip southbridge/intel/i82801dbm + chip southbridge/intel/i82801dx # pci 11.0 on end # pci 11.1 on end # pci 11.2 on end diff --git a/src/mainboard/digitallogic/adl855pc/romstage.c b/src/mainboard/digitallogic/adl855pc/romstage.c index 16d9195d38..8903876057 100644 --- a/src/mainboard/digitallogic/adl855pc/romstage.c +++ b/src/mainboard/digitallogic/adl855pc/romstage.c @@ -16,7 +16,8 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" -#include "southbridge/intel/i82801dbm/i82801dbm_early_smbus.c" +#include "southbridge/intel/i82801dx/i82801dx.h" +#include "southbridge/intel/i82801dx/i82801dx_early_smbus.c" #include "northbridge/intel/i855/raminit.h" #if 0 diff --git a/src/mainboard/hp/e_vectra_p2706t/Kconfig b/src/mainboard/hp/e_vectra_p2706t/Kconfig index 676d3eb5d8..755b3ac904 100644 --- a/src/mainboard/hp/e_vectra_p2706t/Kconfig +++ b/src/mainboard/hp/e_vectra_p2706t/Kconfig @@ -26,7 +26,7 @@ config BOARD_HP_E_VECTRA_P2706T select ARCH_X86 select CPU_INTEL_SOCKET_PGA370 select NORTHBRIDGE_INTEL_I82810 - select SOUTHBRIDGE_INTEL_I82801XX + select SOUTHBRIDGE_INTEL_I82801AX select SUPERIO_NSC_PC87360 select ROMCC select HAVE_PIRQ_TABLE diff --git a/src/mainboard/hp/e_vectra_p2706t/devicetree.cb b/src/mainboard/hp/e_vectra_p2706t/devicetree.cb index 82209d4317..7ea1f299e7 100644 --- a/src/mainboard/hp/e_vectra_p2706t/devicetree.cb +++ b/src/mainboard/hp/e_vectra_p2706t/devicetree.cb @@ -8,7 +8,7 @@ chip northbridge/intel/i82810 # Northbridge device pci_domain 0 on device pci 0.0 on end # Host bridge device pci 1.0 on end # Onboard VGA - chip southbridge/intel/i82801xx # Southbridge + chip southbridge/intel/i82801ax # Southbridge register "ide0_enable" = "1" register "ide1_enable" = "1" diff --git a/src/mainboard/hp/e_vectra_p2706t/romstage.c b/src/mainboard/hp/e_vectra_p2706t/romstage.c index 50d8c447b4..f2c643c854 100644 --- a/src/mainboard/hp/e_vectra_p2706t/romstage.c +++ b/src/mainboard/hp/e_vectra_p2706t/romstage.c @@ -37,7 +37,7 @@ #include "northbridge/intel/i82810/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" -#include "southbridge/intel/i82801xx/i82801xx_early_smbus.c" +#include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" #include "pc80/udelay_io.c" #include "lib/debug.c" #include "northbridge/intel/i82810/raminit.c" diff --git a/src/mainboard/intel/jarrell/Kconfig b/src/mainboard/intel/jarrell/Kconfig index 7a17ea7782..fc70befafa 100644 --- a/src/mainboard/intel/jarrell/Kconfig +++ b/src/mainboard/intel/jarrell/Kconfig @@ -4,7 +4,7 @@ config BOARD_INTEL_JARRELL select CPU_INTEL_SOCKET_MPGA604 select NORTHBRIDGE_INTEL_E7520 select SOUTHBRIDGE_INTEL_PXHD - select SOUTHBRIDGE_INTEL_I82801ER + select SOUTHBRIDGE_INTEL_I82801EX select SUPERIO_NSC_PC87427 select ROMCC select HAVE_PIRQ_TABLE diff --git a/src/mainboard/intel/jarrell/devicetree.cb b/src/mainboard/intel/jarrell/devicetree.cb index e4cdbdeacb..32f70e3e85 100644 --- a/src/mainboard/intel/jarrell/devicetree.cb +++ b/src/mainboard/intel/jarrell/devicetree.cb @@ -17,7 +17,7 @@ chip northbridge/intel/e7520 end end device pci 06.0 on end - chip southbridge/intel/i82801er # i82801er + chip southbridge/intel/i82801ex # i82801er device pci 1d.0 on end device pci 1d.1 on end device pci 1d.2 on end diff --git a/src/mainboard/intel/jarrell/romstage.c b/src/mainboard/intel/jarrell/romstage.c index 462bd8e25d..d7b1bf40c7 100644 --- a/src/mainboard/intel/jarrell/romstage.c +++ b/src/mainboard/intel/jarrell/romstage.c @@ -12,7 +12,7 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" -#include "southbridge/intel/i82801er/i82801er_early_smbus.c" +#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" #include "superio/nsc/pc87427/pc87427.h" #include "cpu/x86/lapic/boot_cpu.c" diff --git a/src/mainboard/intel/xe7501devkit/Kconfig b/src/mainboard/intel/xe7501devkit/Kconfig index 72c1d94fb2..d2a9f4779f 100644 --- a/src/mainboard/intel/xe7501devkit/Kconfig +++ b/src/mainboard/intel/xe7501devkit/Kconfig @@ -4,7 +4,7 @@ config BOARD_INTEL_XE7501DEVKIT select CPU_INTEL_SOCKET_MPGA604 select NORTHBRIDGE_INTEL_E7501 select SOUTHBRIDGE_INTEL_I82870 - select SOUTHBRIDGE_INTEL_I82801CA + select SOUTHBRIDGE_INTEL_I82801CX select SUPERIO_SMSC_LPC47B272 select ROMCC select HAVE_PIRQ_TABLE diff --git a/src/mainboard/intel/xe7501devkit/devicetree.cb b/src/mainboard/intel/xe7501devkit/devicetree.cb index 00ed4eca84..efa0d88216 100644 --- a/src/mainboard/intel/xe7501devkit/devicetree.cb +++ b/src/mainboard/intel/xe7501devkit/devicetree.cb @@ -20,7 +20,7 @@ chip northbridge/intel/e7501 end end device pci 6.0 on end # E7501 Power management registers? (undocumented) - chip southbridge/intel/i82801ca + chip southbridge/intel/i82801cx device pci 1d.0 off end # USB (might not work, Southbridge code needs looking at) device pci 1d.1 off end # USB (not populated) device pci 1d.2 off end # USB (not populated) diff --git a/src/mainboard/intel/xe7501devkit/failover.c b/src/mainboard/intel/xe7501devkit/failover.c index 7aa9e405ed..9daf3b27d6 100644 --- a/src/mainboard/intel/xe7501devkit/failover.c +++ b/src/mainboard/intel/xe7501devkit/failover.c @@ -7,7 +7,7 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include "pc80/mc146818rtc_early.c" -#include "southbridge/intel/i82801ca/cmos_failover.c" +#include "southbridge/intel/i82801cx/cmos_failover.c" #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/intel/e7501/reset_test.c" diff --git a/src/mainboard/intel/xe7501devkit/reset.c b/src/mainboard/intel/xe7501devkit/reset.c index 8feaac64e5..7c8a729f5e 100644 --- a/src/mainboard/intel/xe7501devkit/reset.c +++ b/src/mainboard/intel/xe7501devkit/reset.c @@ -1,6 +1,6 @@ -void i82801ca_hard_reset(void); +void i82801cx_hard_reset(void); void hard_reset(void) { - i82801ca_hard_reset(); + i82801cx_hard_reset(); } diff --git a/src/mainboard/intel/xe7501devkit/romstage.c b/src/mainboard/intel/xe7501devkit/romstage.c index 7269fa8d43..0bedaf9431 100644 --- a/src/mainboard/intel/xe7501devkit/romstage.c +++ b/src/mainboard/intel/xe7501devkit/romstage.c @@ -14,7 +14,7 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" -#include "southbridge/intel/i82801ca/i82801ca_early_smbus.c" +#include "southbridge/intel/i82801cx/i82801cx_early_smbus.c" #include "northbridge/intel/e7501/raminit.h" #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/intel/e7501/debug.c" diff --git a/src/mainboard/mitac/6513wu/Kconfig b/src/mainboard/mitac/6513wu/Kconfig index 20559b24b0..64937ce1c5 100644 --- a/src/mainboard/mitac/6513wu/Kconfig +++ b/src/mainboard/mitac/6513wu/Kconfig @@ -23,7 +23,7 @@ config BOARD_MITAC_6513WU select ARCH_X86 select CPU_INTEL_SOCKET_PGA370 select NORTHBRIDGE_INTEL_I82810 - select SOUTHBRIDGE_INTEL_I82801XX + select SOUTHBRIDGE_INTEL_I82801AX select SUPERIO_SMSC_SMSCSUPERIO select ROMCC select HAVE_PIRQ_TABLE diff --git a/src/mainboard/mitac/6513wu/devicetree.cb b/src/mainboard/mitac/6513wu/devicetree.cb index 0369775c07..3cba778e10 100644 --- a/src/mainboard/mitac/6513wu/devicetree.cb +++ b/src/mainboard/mitac/6513wu/devicetree.cb @@ -27,7 +27,7 @@ chip northbridge/intel/i82810 # Northbridge device pci_domain 0 on # PCI domain device pci 0.0 on end # Graphics Memory Controller Hub (GMCH) device pci 1.0 on end - chip southbridge/intel/i82801xx # Southbridge + chip southbridge/intel/i82801ax # Southbridge register "pirqa_routing" = "0x03" register "pirqb_routing" = "0x05" register "pirqc_routing" = "0x09" diff --git a/src/mainboard/mitac/6513wu/romstage.c b/src/mainboard/mitac/6513wu/romstage.c index 6222ea8721..daa2e9660c 100644 --- a/src/mainboard/mitac/6513wu/romstage.c +++ b/src/mainboard/mitac/6513wu/romstage.c @@ -31,7 +31,7 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" -#include "southbridge/intel/i82801xx/i82801xx_early_smbus.c" +#include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" #include "northbridge/intel/i82810/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" diff --git a/src/mainboard/msi/ms6178/Kconfig b/src/mainboard/msi/ms6178/Kconfig index 16662da312..a6af3260d0 100644 --- a/src/mainboard/msi/ms6178/Kconfig +++ b/src/mainboard/msi/ms6178/Kconfig @@ -23,7 +23,7 @@ config BOARD_MSI_MS_6178 select ARCH_X86 select CPU_INTEL_SOCKET_PGA370 select NORTHBRIDGE_INTEL_I82810 - select SOUTHBRIDGE_INTEL_I82801XX + select SOUTHBRIDGE_INTEL_I82801AX select SUPERIO_WINBOND_W83627HF select ROMCC select HAVE_PIRQ_TABLE diff --git a/src/mainboard/msi/ms6178/devicetree.cb b/src/mainboard/msi/ms6178/devicetree.cb index baa0e040b8..4863957714 100644 --- a/src/mainboard/msi/ms6178/devicetree.cb +++ b/src/mainboard/msi/ms6178/devicetree.cb @@ -27,7 +27,7 @@ chip northbridge/intel/i82810 # Northbridge device pci_domain 0 on device pci 0.0 on end # Host bridge device pci 1.0 on end # Onboard VGA - chip southbridge/intel/i82801xx # Southbridge + chip southbridge/intel/i82801ax # Southbridge register "ide0_enable" = "1" register "ide1_enable" = "1" diff --git a/src/mainboard/msi/ms6178/romstage.c b/src/mainboard/msi/ms6178/romstage.c index a320dde763..976d24a56c 100644 --- a/src/mainboard/msi/ms6178/romstage.c +++ b/src/mainboard/msi/ms6178/romstage.c @@ -35,7 +35,7 @@ #include "northbridge/intel/i82810/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" -#include "southbridge/intel/i82801xx/i82801xx_early_smbus.c" +#include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" #include "pc80/udelay_io.c" #include "lib/debug.c" #include "northbridge/intel/i82810/raminit.c" diff --git a/src/mainboard/nec/powermate2000/Kconfig b/src/mainboard/nec/powermate2000/Kconfig index fa3532d028..7b818b45e1 100644 --- a/src/mainboard/nec/powermate2000/Kconfig +++ b/src/mainboard/nec/powermate2000/Kconfig @@ -23,7 +23,7 @@ config BOARD_NEC_POWERMATE_2000 select ARCH_X86 select CPU_INTEL_SOCKET_PGA370 select NORTHBRIDGE_INTEL_I82810 - select SOUTHBRIDGE_INTEL_I82801XX + select SOUTHBRIDGE_INTEL_I82801AX select SUPERIO_SMSC_SMSCSUPERIO select ROMCC select HAVE_PIRQ_TABLE diff --git a/src/mainboard/nec/powermate2000/devicetree.cb b/src/mainboard/nec/powermate2000/devicetree.cb index 0cb7e328b5..52cae5823c 100644 --- a/src/mainboard/nec/powermate2000/devicetree.cb +++ b/src/mainboard/nec/powermate2000/devicetree.cb @@ -7,7 +7,7 @@ chip northbridge/intel/i82810 # Northbridge device pci_domain 0 on device pci 0.0 on end # Host bridge device pci 1.0 off end # Onboard video - chip southbridge/intel/i82801xx # Southbridge + chip southbridge/intel/i82801ax # Southbridge register "ide0_enable" = "1" register "ide1_enable" = "1" diff --git a/src/mainboard/nec/powermate2000/romstage.c b/src/mainboard/nec/powermate2000/romstage.c index 701e312967..c923f9943a 100644 --- a/src/mainboard/nec/powermate2000/romstage.c +++ b/src/mainboard/nec/powermate2000/romstage.c @@ -35,7 +35,7 @@ #include "northbridge/intel/i82810/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" -#include "southbridge/intel/i82801xx/i82801xx_early_smbus.c" +#include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" #include "pc80/udelay_io.c" #include "northbridge/intel/i82810/raminit.c" diff --git a/src/mainboard/rca/rm4100/Kconfig b/src/mainboard/rca/rm4100/Kconfig index 1be2a752dc..cdca002ea3 100644 --- a/src/mainboard/rca/rm4100/Kconfig +++ b/src/mainboard/rca/rm4100/Kconfig @@ -3,7 +3,7 @@ config BOARD_RCA_RM4100 select ARCH_X86 select CPU_INTEL_SOCKET_PGA370 select NORTHBRIDGE_INTEL_I82830 - select SOUTHBRIDGE_INTEL_I82801XX + select SOUTHBRIDGE_INTEL_I82801DX select SUPERIO_SMSC_SMSCSUPERIO select ROMCC select HAVE_PIRQ_TABLE diff --git a/src/mainboard/rca/rm4100/devicetree.cb b/src/mainboard/rca/rm4100/devicetree.cb index 1844932114..2b04ad7d3a 100644 --- a/src/mainboard/rca/rm4100/devicetree.cb +++ b/src/mainboard/rca/rm4100/devicetree.cb @@ -2,7 +2,7 @@ chip northbridge/intel/i82830 # Northbridge device pci_domain 0 on # PCI domain device pci 0.0 on end # Host bridge device pci 2.0 on end # VGA (Intel 82830 CGC) - chip southbridge/intel/i82801xx # Southbridge + chip southbridge/intel/i82801dx # Southbridge register "pirqa_routing" = "0x05" register "pirqb_routing" = "0x06" register "pirqc_routing" = "0x07" diff --git a/src/mainboard/rca/rm4100/gpio.c b/src/mainboard/rca/rm4100/gpio.c index d51bc90e78..a27b7bb327 100644 --- a/src/mainboard/rca/rm4100/gpio.c +++ b/src/mainboard/rca/rm4100/gpio.c @@ -34,8 +34,8 @@ static void mb_gpio_init(void) dev = PCI_DEV(0x0, 0x1f, 0x0); /* Set the value for GPIO base address register and enable GPIO. */ - pci_write_config32(dev, GPIO_BASE_ICH0_5, (ICH_IO_BASE_ADDR | 1)); - pci_write_config8(dev, GPIO_CNTL_ICH0_5, 0x10); + pci_write_config32(dev, GPIO_BASE, (ICH_IO_BASE_ADDR | 1)); + pci_write_config8(dev, GPIO_CNTL, 0x10); /* Set GPIO23 to high, this enables the LAN controller. */ udelay(10); diff --git a/src/mainboard/rca/rm4100/romstage.c b/src/mainboard/rca/rm4100/romstage.c index 2f3892e3a0..cf7464442d 100644 --- a/src/mainboard/rca/rm4100/romstage.c +++ b/src/mainboard/rca/rm4100/romstage.c @@ -35,8 +35,8 @@ #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" #include "northbridge/intel/i82830/raminit.h" #include "northbridge/intel/i82830/memory_initialized.c" -#include "southbridge/intel/i82801xx/i82801xx.h" -#include "southbridge/intel/i82801xx/i82801xx_reset.c" +#include "southbridge/intel/i82801dx/i82801dx.h" +#include "southbridge/intel/i82801dx/i82801dx_reset.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "spd_table.h" @@ -44,7 +44,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) -#include "southbridge/intel/i82801xx/i82801xx_early_smbus.c" +#include "southbridge/intel/i82801dx/i82801dx_early_smbus.c" /** * The onboard 64MB PC133 memory does not have a SPD EEPROM so the @@ -127,4 +127,4 @@ static void main(unsigned long bist) /* Check RAM. */ /* ram_check(0, 640 * 1024); */ /* ram_check(64512 * 1024, 65536 * 1024); */ -}
\ No newline at end of file +} diff --git a/src/mainboard/supermicro/x6dhe_g2/Kconfig b/src/mainboard/supermicro/x6dhe_g2/Kconfig index eb3330c023..a456abea8a 100644 --- a/src/mainboard/supermicro/x6dhe_g2/Kconfig +++ b/src/mainboard/supermicro/x6dhe_g2/Kconfig @@ -3,7 +3,7 @@ config BOARD_SUPERMICRO_X6DHE_G2 select ARCH_X86 select CPU_INTEL_SOCKET_MPGA604 select NORTHBRIDGE_INTEL_E7520 - select SOUTHBRIDGE_INTEL_I82801ER + select SOUTHBRIDGE_INTEL_I82801EX select SOUTHBRIDGE_INTEL_PXHD select SUPERIO_NSC_PC87427 select ROMCC diff --git a/src/mainboard/supermicro/x6dhe_g2/devicetree.cb b/src/mainboard/supermicro/x6dhe_g2/devicetree.cb index 4bb720707c..e621594b93 100644 --- a/src/mainboard/supermicro/x6dhe_g2/devicetree.cb +++ b/src/mainboard/supermicro/x6dhe_g2/devicetree.cb @@ -6,7 +6,7 @@ chip northbridge/intel/e7520 # MCH device pnp 00.3 off end end device pci_domain 0 on - chip southbridge/intel/i82801er # ICH5R + chip southbridge/intel/i82801ex # ICH5R register "pirq_a_d" = "0x0b070a05" register "pirq_e_h" = "0x0a808080" diff --git a/src/mainboard/supermicro/x6dhe_g2/romstage.c b/src/mainboard/supermicro/x6dhe_g2/romstage.c index 4e9c1e270b..f38f4e9b07 100644 --- a/src/mainboard/supermicro/x6dhe_g2/romstage.c +++ b/src/mainboard/supermicro/x6dhe_g2/romstage.c @@ -12,7 +12,7 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" -#include "southbridge/intel/i82801er/i82801er_early_smbus.c" +#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" #include "superio/nsc/pc87427/pc87427.h" #include "cpu/x86/lapic/boot_cpu.c" diff --git a/src/mainboard/supermicro/x6dhr_ig/Kconfig b/src/mainboard/supermicro/x6dhr_ig/Kconfig index 759e6d14ba..56653adc9b 100644 --- a/src/mainboard/supermicro/x6dhr_ig/Kconfig +++ b/src/mainboard/supermicro/x6dhr_ig/Kconfig @@ -3,7 +3,7 @@ config BOARD_SUPERMICRO_X6DHR_IG select ARCH_X86 select CPU_INTEL_SOCKET_MPGA604 select NORTHBRIDGE_INTEL_E7520 - select SOUTHBRIDGE_INTEL_I82801ER + select SOUTHBRIDGE_INTEL_I82801EX select SOUTHBRIDGE_INTEL_PXHD select SUPERIO_WINBOND_W83627HF select ROMCC diff --git a/src/mainboard/supermicro/x6dhr_ig/devicetree.cb b/src/mainboard/supermicro/x6dhr_ig/devicetree.cb index 8a82ed7c40..921c54fff5 100644 --- a/src/mainboard/supermicro/x6dhr_ig/devicetree.cb +++ b/src/mainboard/supermicro/x6dhr_ig/devicetree.cb @@ -1,6 +1,6 @@ chip northbridge/intel/e7520 # mch device pci_domain 0 on - chip southbridge/intel/i82801er # i82801er + chip southbridge/intel/i82801ex # i82801er # USB ports device pci 1d.0 on end device pci 1d.1 on end diff --git a/src/mainboard/supermicro/x6dhr_ig/romstage.c b/src/mainboard/supermicro/x6dhr_ig/romstage.c index 314cc70325..0fd77d3a56 100644 --- a/src/mainboard/supermicro/x6dhr_ig/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig/romstage.c @@ -12,7 +12,7 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" -#include "southbridge/intel/i82801er/i82801er_early_smbus.c" +#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" #include "superio/winbond/w83627hf/w83627hf.h" #include "cpu/x86/lapic/boot_cpu.c" diff --git a/src/mainboard/supermicro/x6dhr_ig2/Kconfig b/src/mainboard/supermicro/x6dhr_ig2/Kconfig index e25f8bf7d0..126739be10 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/Kconfig +++ b/src/mainboard/supermicro/x6dhr_ig2/Kconfig @@ -3,7 +3,7 @@ config BOARD_SUPERMICRO_X6DHR_IG2 select ARCH_X86 select CPU_INTEL_SOCKET_MPGA604 select NORTHBRIDGE_INTEL_E7520 - select SOUTHBRIDGE_INTEL_I82801ER + select SOUTHBRIDGE_INTEL_I82801EX select SOUTHBRIDGE_INTEL_PXHD select SUPERIO_WINBOND_W83627HF select ROMCC diff --git a/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb b/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb index ab56509fd9..318d492b9f 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb +++ b/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb @@ -1,6 +1,6 @@ chip northbridge/intel/e7520 # mch device pci_domain 0 on - chip southbridge/intel/i82801er # i82801er + chip southbridge/intel/i82801ex # i82801er # USB ports device pci 1d.0 on end device pci 1d.1 on end diff --git a/src/mainboard/supermicro/x6dhr_ig2/romstage.c b/src/mainboard/supermicro/x6dhr_ig2/romstage.c index 3cb41ad037..7a9b696198 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig2/romstage.c @@ -12,7 +12,7 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" -#include "southbridge/intel/i82801er/i82801er_early_smbus.c" +#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" #include "superio/winbond/w83627hf/w83627hf.h" #include "cpu/x86/lapic/boot_cpu.c" diff --git a/src/mainboard/thomson/ip1000/Kconfig b/src/mainboard/thomson/ip1000/Kconfig index 6a87d0cfc8..b78a20e388 100644 --- a/src/mainboard/thomson/ip1000/Kconfig +++ b/src/mainboard/thomson/ip1000/Kconfig @@ -3,7 +3,7 @@ config BOARD_THOMSON_IP1000 select ARCH_X86 select CPU_INTEL_SOCKET_PGA370 select NORTHBRIDGE_INTEL_I82830 - select SOUTHBRIDGE_INTEL_I82801XX + select SOUTHBRIDGE_INTEL_I82801DX select SUPERIO_SMSC_SMSCSUPERIO select ROMCC select HAVE_PIRQ_TABLE @@ -28,4 +28,4 @@ config HAVE_OPTION_TABLE config IRQ_SLOT_COUNT int default 7 - depends on BOARD_THOMSON_IP1000
\ No newline at end of file + depends on BOARD_THOMSON_IP1000 diff --git a/src/mainboard/thomson/ip1000/devicetree.cb b/src/mainboard/thomson/ip1000/devicetree.cb index 7f5c42a8cf..f38c1c3e67 100644 --- a/src/mainboard/thomson/ip1000/devicetree.cb +++ b/src/mainboard/thomson/ip1000/devicetree.cb @@ -2,7 +2,7 @@ chip northbridge/intel/i82830 # Northbridge device pci_domain 0 on # PCI domain device pci 0.0 on end # Host bridge device pci 2.0 on end # VGA (Intel 82830 CGC) - chip southbridge/intel/i82801xx # Southbridge + chip southbridge/intel/i82801dx # Southbridge register "pirqa_routing" = "0x05" register "pirqb_routing" = "0x06" register "pirqc_routing" = "0x07" diff --git a/src/mainboard/thomson/ip1000/gpio.c b/src/mainboard/thomson/ip1000/gpio.c index ae2cd8eabf..6a69bb539d 100644 --- a/src/mainboard/thomson/ip1000/gpio.c +++ b/src/mainboard/thomson/ip1000/gpio.c @@ -34,8 +34,8 @@ static void mb_gpio_init(void) dev = PCI_DEV(0x0, 0x1f, 0x0); /* Set the value for GPIO base address register and enable GPIO. */ - pci_write_config32(dev, GPIO_BASE_ICH0_5, (ICH_IO_BASE_ADDR | 1)); - pci_write_config8(dev, GPIO_CNTL_ICH0_5, 0x10); + pci_write_config32(dev, GPIO_BASE, (ICH_IO_BASE_ADDR | 1)); + pci_write_config8(dev, GPIO_CNTL, 0x10); /* Set GPIO23 to high, this enables the LAN controller. */ udelay(10); diff --git a/src/mainboard/thomson/ip1000/romstage.c b/src/mainboard/thomson/ip1000/romstage.c index 2f3892e3a0..cf7464442d 100644 --- a/src/mainboard/thomson/ip1000/romstage.c +++ b/src/mainboard/thomson/ip1000/romstage.c @@ -35,8 +35,8 @@ #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" #include "northbridge/intel/i82830/raminit.h" #include "northbridge/intel/i82830/memory_initialized.c" -#include "southbridge/intel/i82801xx/i82801xx.h" -#include "southbridge/intel/i82801xx/i82801xx_reset.c" +#include "southbridge/intel/i82801dx/i82801dx.h" +#include "southbridge/intel/i82801dx/i82801dx_reset.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "spd_table.h" @@ -44,7 +44,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) -#include "southbridge/intel/i82801xx/i82801xx_early_smbus.c" +#include "southbridge/intel/i82801dx/i82801dx_early_smbus.c" /** * The onboard 64MB PC133 memory does not have a SPD EEPROM so the @@ -127,4 +127,4 @@ static void main(unsigned long bist) /* Check RAM. */ /* ram_check(0, 640 * 1024); */ /* ram_check(64512 * 1024, 65536 * 1024); */ -}
\ No newline at end of file +} diff --git a/src/mainboard/tyan/s2735/Kconfig b/src/mainboard/tyan/s2735/Kconfig index 8d516fe660..0c3f8a573d 100644 --- a/src/mainboard/tyan/s2735/Kconfig +++ b/src/mainboard/tyan/s2735/Kconfig @@ -4,7 +4,7 @@ config BOARD_TYAN_S2735 select CPU_INTEL_SOCKET_MPGA604 select NORTHBRIDGE_INTEL_E7501 select SOUTHBRIDGE_INTEL_I82870 - select SOUTHBRIDGE_INTEL_I82801ER + select SOUTHBRIDGE_INTEL_I82801EX select SUPERIO_WINBOND_W83627HF select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/tyan/s2735/devicetree.cb b/src/mainboard/tyan/s2735/devicetree.cb index 0fdd57814a..8ad5e0ecac 100644 --- a/src/mainboard/tyan/s2735/devicetree.cb +++ b/src/mainboard/tyan/s2735/devicetree.cb @@ -14,7 +14,7 @@ chip northbridge/intel/e7501 end end device pci 6.0 on end - chip southbridge/intel/i82801er + chip southbridge/intel/i82801ex device pci 1d.0 on end device pci 1d.1 on end device pci 1d.2 on end diff --git a/src/mainboard/tyan/s2735/reset.c b/src/mainboard/tyan/s2735/reset.c index 371920dca2..2601faa676 100644 --- a/src/mainboard/tyan/s2735/reset.c +++ b/src/mainboard/tyan/s2735/reset.c @@ -1,7 +1,7 @@ -void i82801er_hard_reset(void); +void i82801ex_hard_reset(void); /* FIXME: There's another hard_reset() in romstage.c. Why? */ void hard_reset(void) { - i82801er_hard_reset(); + i82801ex_hard_reset(); } diff --git a/src/mainboard/tyan/s2735/romstage.c b/src/mainboard/tyan/s2735/romstage.c index 99a38a9fb3..5e2678a047 100644 --- a/src/mainboard/tyan/s2735/romstage.c +++ b/src/mainboard/tyan/s2735/romstage.c @@ -25,7 +25,7 @@ static void post_code(uint8_t value) { } #endif -#include "southbridge/intel/i82801er/i82801er_early_smbus.c" +#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7501/raminit.h" #include "cpu/x86/lapic/boot_cpu.c" @@ -82,7 +82,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #if CONFIG_USE_FALLBACK_IMAGE == 1 -#include "southbridge/intel/i82801er/cmos_failover.c" +#include "southbridge/intel/i82801ex/cmos_failover.c" void real_main(unsigned long bist); |