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-rw-r--r--src/mainboard/supermicro/h8qme_fam10/Config.lb38
-rw-r--r--src/mainboard/supermicro/h8qme_fam10/Options.lb13
-rw-r--r--src/mainboard/supermicro/h8qme_fam10/apc_auto.c7
-rw-r--r--src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c22
-rw-r--r--src/mainboard/supermicro/h8qme_fam10/mainboard.c2
-rw-r--r--src/mainboard/supermicro/h8qme_fam10/mb_sysconf.h11
-rw-r--r--src/mainboard/supermicro/h8qme_fam10/mptable.c91
-rw-r--r--src/mainboard/supermicro/h8qme_fam10/spd_addr.h6
8 files changed, 84 insertions, 106 deletions
diff --git a/src/mainboard/supermicro/h8qme_fam10/Config.lb b/src/mainboard/supermicro/h8qme_fam10/Config.lb
index 9014c4f87d..863575b210 100644
--- a/src/mainboard/supermicro/h8qme_fam10/Config.lb
+++ b/src/mainboard/supermicro/h8qme_fam10/Config.lb
@@ -288,12 +288,12 @@ chip northbridge/amd/amdfam10/root_complex
device pci 5.0 on end # SATA 0
device pci 5.1 on end # SATA 1
device pci 5.2 on end # SATA 2
- device pci 6.1 off end # AZA
- device pci 7.0 on
- device pci 1.0 on end
- end
- device pci 8.0 off end
- device pci 9.0 off end
+ device pci 6.1 off end # AZA
+ device pci 7.0 on
+ device pci 1.0 on end
+ end
+ device pci 8.0 off end
+ device pci 9.0 off end
device pci a.0 on end # PCI E 5
device pci b.0 on end # PCI E 4
device pci c.0 on end # PCI E 3
@@ -312,20 +312,18 @@ chip northbridge/amd/amdfam10/root_complex
device pci 18.3 on end
device pci 18.4 on end
device pci 19.0 on end
- device pci 19.0 on end
- device pci 19.0 on
- chip southbridge/amd/amd8132
- device pci 0.0 on end
- device pci 0.1 on end
- device pci 1.0 on
- device pci 3.0 on end
- device pci 3.1 on end
- end
- device pci 1.1 on end
-
- end #amd8132
-
- end #device pci 19.0
+ device pci 19.0 on end
+ device pci 19.0 on
+ chip southbridge/amd/amd8132
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 1.0 on
+ device pci 3.0 on end
+ device pci 3.1 on end
+ end
+ device pci 1.1 on end
+ end #amd8132
+ end #device pci 19.0
device pci 19.1 on end
device pci 19.2 on end
device pci 19.3 on end
diff --git a/src/mainboard/supermicro/h8qme_fam10/Options.lb b/src/mainboard/supermicro/h8qme_fam10/Options.lb
index 3a4e5bd29a..279d8ac96e 100644
--- a/src/mainboard/supermicro/h8qme_fam10/Options.lb
+++ b/src/mainboard/supermicro/h8qme_fam10/Options.lb
@@ -141,6 +141,7 @@ default CONFIG_FAILOVER_SIZE=0x02000
#more 1M for pgtbl
default CONFIG_RAMTOP=16384*1024
#default CONFIG_RAMTOP=16384*8192
+
##
## Build code for the fallback boot
##
@@ -162,7 +163,6 @@ default CONFIG_IRQ_SLOT_COUNT=11
## Build code to export an x86 MP table
## Useful for specifying IRQ routing values
##
-##default CONFIG_GENERATE_MP_TABLE=1
default CONFIG_GENERATE_MP_TABLE=1
## ACPI tables will be included
@@ -272,10 +272,15 @@ default CONFIG_AMD_UCODE_PATCH_FILE="mc_patch_0100009f.h"
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default CONFIG_ROM_IMAGE_SIZE = 0x1e000
+##
+## Use a 64K stack
+##
+default CONFIG_STACK_SIZE=0x10000
-default CONFIG_STACK_SIZE=0x10000
-default CONFIG_HEAP_SIZE= 0xc000
-
+##
+## Use a 48K heap
+##
+default CONFIG_HEAP_SIZE=0xc000
##
## Only use the option table in a normal image
diff --git a/src/mainboard/supermicro/h8qme_fam10/apc_auto.c b/src/mainboard/supermicro/h8qme_fam10/apc_auto.c
index 9a7946ac15..c3aaf5195a 100644
--- a/src/mainboard/supermicro/h8qme_fam10/apc_auto.c
+++ b/src/mainboard/supermicro/h8qme_fam10/apc_auto.c
@@ -64,32 +64,25 @@ static void post_code(uint8_t value) {
#endif
#include <cpu/amd/model_fxx_rev.h>
-
-//#include "northbridge/amd/amdk8/raminit.h"
#include "northbridge/amd/amkfam10/raminit.h"
-
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
//#include "cpu/x86/lapic/boot_cpu.c"
-//#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdfam10/reset_test.c"
-//#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdfam10/debug.c"
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
-//#include "northbridge/amd/amdk8/amdk8_f.h"
#include "northbridge/amd/amdfam10/amdfam10.h"
#include "cpu/x86/mtrr.h"
#include "cpu/amd/mtrr.h"
#include "cpu/x86/tsc.h"
-//#include "northbridge/amd/amdk8/amdk8_f_pci.c"
#include "northbridge/amd/amdfam10/amdfam10_pci.c"
#include "northbridge/amd/amdk8/raminit_f_dqs.c"
diff --git a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c
index bfadeef0f6..effb614cf2 100644
--- a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c
+++ b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c
@@ -62,8 +62,7 @@ static unsigned hcdnx[] = {
0x20202020, 0x20202020,
};
-unsigned sbdn3;
-
+unsigned sbdn3;
extern void get_pci1234(void);
@@ -99,9 +98,8 @@ void get_bus_conf(void)
sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
m->bus_mcp55[0] = (sysconf.pci1234[0] >> 12) & 0xff;
-
- m->bus_8132_0 = (sysconf.pci1234[1] >> 12) & 0xff;
- sbdn3 =(sysconf.hcdn[1] & 0xff); // first byte of second chain
+ m->bus_8132_0 = (sysconf.pci1234[1] >> 12) & 0xff;
+ sbdn3 = (sysconf.hcdn[1] & 0xff); // first byte of second chain
/* MCP55 */
dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x06,0));
@@ -123,21 +121,21 @@ void get_bus_conf(void)
}
}
-/*8132_1*/
+ /* 8132_1 */
- dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(sbdn3,0));
- m->bus_8132_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(sbdn3, 0));
+ m->bus_8132_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
m->bus_8132_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
m->bus_8132_2++;
-/*8132_2*/
- dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(sbdn3+1,0));
+ /* 8132_2 */
+ dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(sbdn3 + 1, 0));
m->bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
m->bus_isa++;
for(i=0; i< sysconf.hc_possible_num; i++) {
- if(!(sysconf.pci1234[i] & 0x1) ) continue;
+ if(!(sysconf.pci1234[i] & 0x1) ) continue;
unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff;
unsigned busn_max = (sysconf.pci1234[i] >> 20) & 0xff;
@@ -155,6 +153,6 @@ void get_bus_conf(void)
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
#endif
m->apicid_mcp55 = apicid_base+0;
- m->apicid_8132_1 = apicid_base+1;
+ m->apicid_8132_1 = apicid_base+1;
m->apicid_8132_2 = apicid_base+2;
}
diff --git a/src/mainboard/supermicro/h8qme_fam10/mainboard.c b/src/mainboard/supermicro/h8qme_fam10/mainboard.c
index bc2feea309..209dca4eea 100644
--- a/src/mainboard/supermicro/h8qme_fam10/mainboard.c
+++ b/src/mainboard/supermicro/h8qme_fam10/mainboard.c
@@ -27,5 +27,5 @@
#include "chip.h"
struct chip_operations mainboard_ops = {
- CHIP_NAME("Supermicro H8QME Mainboard (Family 10)")
+ CHIP_NAME("Supermicro H8QME-2+ Mainboard (Family 10)")
};
diff --git a/src/mainboard/supermicro/h8qme_fam10/mb_sysconf.h b/src/mainboard/supermicro/h8qme_fam10/mb_sysconf.h
index 579afb8c72..42969bb71e 100644
--- a/src/mainboard/supermicro/h8qme_fam10/mb_sysconf.h
+++ b/src/mainboard/supermicro/h8qme_fam10/mb_sysconf.h
@@ -28,12 +28,11 @@ struct mb_sysconf_t {
unsigned apicid_mcp55;
unsigned bus_type[256];
-unsigned char bus_8132_0; //7
-unsigned char bus_8132_1; //8
-unsigned char bus_8132_2; //9
-unsigned apicid_8132_1;
-unsigned apicid_8132_2;
-
+ unsigned char bus_8132_0; //7
+ unsigned char bus_8132_1; //8
+ unsigned char bus_8132_2; //9
+ unsigned apicid_8132_1;
+ unsigned apicid_8132_2;
};
#endif
diff --git a/src/mainboard/supermicro/h8qme_fam10/mptable.c b/src/mainboard/supermicro/h8qme_fam10/mptable.c
index f250de530c..8cbf92cc6d 100644
--- a/src/mainboard/supermicro/h8qme_fam10/mptable.c
+++ b/src/mainboard/supermicro/h8qme_fam10/mptable.c
@@ -40,7 +40,6 @@ void *smp_write_config_table(void *v)
struct mp_config_table *mc;
struct mb_sysconf_t *m;
unsigned sbdn;
-
int i,j;
@@ -67,8 +66,6 @@ void *smp_write_config_table(void *v)
sbdn = sysconf.sbdn;
m = sysconf.mb;
-
-
/*Bus: Bus ID Type*/
/* define bus and isa numbers */
for(j= 0; j < 256 ; j++) {
@@ -77,22 +74,13 @@ void *smp_write_config_table(void *v)
}
smp_write_bus(mc, m->bus_isa, "ISA ");
-
-
-
-
-
/*I/O APICs: APIC ID Version State Address*/
{
device_t dev;
struct resource *res;
uint32_t dword;
-//void smp_write_ioapic(struct mp_config_table *mc, unsigned char id, unsigned char ver, unsigned long apicaddr);
-
dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
-
-
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
@@ -103,55 +91,52 @@ void *smp_write_config_table(void *v)
pci_write_config32(dev, 0x7c, dword);
dword = 0x5ab0a500;
- pci_write_config32(dev, 0x80, dword);
+ pci_write_config32(dev, 0x80, dword);
dword = 0xa000000b;
- dword = 0x10000002;
+ dword = 0x10000002;
pci_write_config32(dev, 0x84, dword);
}
- /* 8132_1*/
- dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(sbdn3,1));
- res = find_resource(dev,PCI_BASE_ADDRESS_0);
- smp_write_ioapic(mc, m->apicid_8132_1, 0x11, res->base);
-
- /* 8132_2*/
- dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(sbdn3+1,1));
- res = find_resource(dev,PCI_BASE_ADDRESS_0);
- smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res->base);
+ /* 8132_1 */
+ dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(sbdn3,1));
+ res = find_resource(dev,PCI_BASE_ADDRESS_0);
+ smp_write_ioapic(mc, m->apicid_8132_1, 0x11, res->base);
+ /* 8132_2 */
+ dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(sbdn3+1,1));
+ res = find_resource(dev,PCI_BASE_ADDRESS_0);
+ smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res->base);
-}
-
+ }
-/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID * PIN# */
-smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x0);
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x1, m->apicid_mcp55, 0x1);
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x2);
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x3, m->apicid_mcp55, 0x3);
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x4, m->apicid_mcp55, 0x4);
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x6, m->apicid_mcp55, 0x6);
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x7, m->apicid_mcp55, 0x7);
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x8, m->apicid_mcp55, 0x8);
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xc, m->apicid_mcp55, 0xc);
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xd, m->apicid_mcp55, 0xd);
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xe, m->apicid_mcp55, 0xe);
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xf, m->apicid_mcp55, 0xf);
-
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0x5); /* 5 SMBus! Not correctly assign!!*/
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0xb); /* 11 USB, OK */
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0xa); /* 10 USB, OK */
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x5); /* 5 IDE, OK*/
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0xa); /* 10 IDE, OK*/
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0xa); /* 10 IDE, OK*/
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+6)<<2)|1, m->apicid_mcp55, 0xa); /* 10 VGA, OK*/
-
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, ((3)<<2)|0, m->apicid_mcp55, 0x5); /* 5 eth0, OK*/
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, ((3)<<2)|1, m->apicid_mcp55, 0xb); /* 11 eth1, OK*/
-
-
-for(j=7;j>=2; j--) {
+ /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x0);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x1, m->apicid_mcp55, 0x1);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x2);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x3, m->apicid_mcp55, 0x3);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x4, m->apicid_mcp55, 0x4);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x6, m->apicid_mcp55, 0x6);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x7, m->apicid_mcp55, 0x7);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x8, m->apicid_mcp55, 0x8);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xc, m->apicid_mcp55, 0xc);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xd, m->apicid_mcp55, 0xd);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xe, m->apicid_mcp55, 0xe);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xf, m->apicid_mcp55, 0xf);
+
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0x5); /* 5 SMBus! Not correctly assign!!*/
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0xb); /* 11 USB, OK */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0xa); /* 10 USB, OK */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x5); /* 5 IDE, OK*/
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0xa); /* 10 IDE, OK*/
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0xa); /* 10 IDE, OK*/
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+6)<<2)|1, m->apicid_mcp55, 0xa); /* 10 VGA, OK*/
+
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, ((3)<<2)|0, m->apicid_mcp55, 0x5); /* 5 eth0, OK*/
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, ((3)<<2)|1, m->apicid_mcp55, 0xb); /* 11 eth1, OK*/
+
+ for(j=7;j>=2; j--) {
if(!m->bus_mcp55[j]) continue;
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
@@ -172,7 +157,7 @@ for(j=7;j>=2; j--) {
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
printk_debug("Wrote the mp table end at: %p - %p\n",
- mc, smp_next_mpe_entry(mc));
+ mc, smp_next_mpe_entry(mc));
return smp_next_mpe_entry(mc);
}
diff --git a/src/mainboard/supermicro/h8qme_fam10/spd_addr.h b/src/mainboard/supermicro/h8qme_fam10/spd_addr.h
index c954ca5bd7..b5994bf017 100644
--- a/src/mainboard/supermicro/h8qme_fam10/spd_addr.h
+++ b/src/mainboard/supermicro/h8qme_fam10/spd_addr.h
@@ -107,9 +107,9 @@ static const u8 spd_addr[] = {
RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 2
- // third node
- RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
- // forth node
+ //third node
+ RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ //forth node
RC03, DIMM4, DIMM6,0 , 0, DIMM5, DIMM7, 0, 0,
#endif
};
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 19:36:04 +0000