diff options
Diffstat (limited to 'src/mainboard')
68 files changed, 226 insertions, 221 deletions
diff --git a/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c b/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c index 612ab5b176..a273741eca 100644 --- a/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c +++ b/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c @@ -142,7 +142,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.ImcEnable = TRUE; FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ - FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */ + FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader); diff --git a/src/mainboard/amd/lamar/BiosCallOuts.c b/src/mainboard/amd/lamar/BiosCallOuts.c index 98b59e79ec..da6d9ac1af 100644 --- a/src/mainboard/amd/lamar/BiosCallOuts.c +++ b/src/mainboard/amd/lamar/BiosCallOuts.c @@ -159,7 +159,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.ImcEnable = TRUE; FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ - FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */ + FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader); diff --git a/src/mainboard/amd/olivehill/BiosCallOuts.c b/src/mainboard/amd/olivehill/BiosCallOuts.c index 0ff1e9a700..6f8baa945f 100644 --- a/src/mainboard/amd/olivehill/BiosCallOuts.c +++ b/src/mainboard/amd/olivehill/BiosCallOuts.c @@ -111,7 +111,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.ImcEnable = TRUE; FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ - FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */ + FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader); diff --git a/src/mainboard/amd/olivehillplus/BiosCallOuts.c b/src/mainboard/amd/olivehillplus/BiosCallOuts.c index 92ba28795f..c5e51cddfd 100644 --- a/src/mainboard/amd/olivehillplus/BiosCallOuts.c +++ b/src/mainboard/amd/olivehillplus/BiosCallOuts.c @@ -125,7 +125,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.ImcEnable = TRUE; FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ - FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */ + FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader); diff --git a/src/mainboard/amd/parmer/BiosCallOuts.c b/src/mainboard/amd/parmer/BiosCallOuts.c index b912d28870..a90085953e 100644 --- a/src/mainboard/amd/parmer/BiosCallOuts.c +++ b/src/mainboard/amd/parmer/BiosCallOuts.c @@ -111,7 +111,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.ImcEnable = TRUE; FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ - FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */ + FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader); diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c index e355aaef28..9f273a4d8b 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c @@ -49,7 +49,7 @@ unsigned long acpi_fill_madt(unsigned long current) res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_1, - res->base, gsi_base ); + res->base, gsi_base); gsi_base+=7; } } @@ -58,7 +58,7 @@ unsigned long acpi_fill_madt(unsigned long current) res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_2, - res->base, gsi_base ); + res->base, gsi_base); gsi_base+=7; } } @@ -66,9 +66,10 @@ unsigned long acpi_fill_madt(unsigned long current) int i; int j = 0; - for(i = 1; i < sysconf.hc_possible_num; i++) { + for (i = 1; i < sysconf.hc_possible_num; i++) { u32 d = 0; - if(!(sysconf.pci1234[i] & 0x1) ) continue; + if (!(sysconf.pci1234[i] & 0x1)) + continue; /* 8131 need to use +4 */ switch (sysconf.hcid[i]) { case 1: @@ -86,7 +87,7 @@ unsigned long acpi_fill_madt(unsigned long current) res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][0], - res->base, gsi_base ); + res->base, gsi_base); gsi_base+=d; } } @@ -95,7 +96,7 @@ unsigned long acpi_fill_madt(unsigned long current) res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][1], - res->base, gsi_base ); + res->base, gsi_base); gsi_base+=d; } } @@ -105,7 +106,7 @@ unsigned long acpi_fill_madt(unsigned long current) } } - current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *) current, 0, 0, 2, 5 ); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 5); /* 0: mean bus 0--->ISA */ /* 0: PIC 0 */ /* 2: APIC 2 */ @@ -135,11 +136,12 @@ unsigned long mainboard_write_acpi_tables(struct device *device, * change HCIN, and recalculate the checknum and add_table */ - for(i = 1; i < sysconf.hc_possible_num; i++) { /* 0: is hc sblink */ + for (i = 1; i < sysconf.hc_possible_num; i++) { /* 0: is hc sblink */ const char *file_name; - if((sysconf.pci1234[i] & 1) != 1 ) continue; + if ((sysconf.pci1234[i] & 1) != 1) + continue; u8 c; - if(i < 7) { + if (i < 7) { c = (u8) ('4' + i - 1); } else { diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c index 97a06ab361..adf43c0157 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c @@ -95,7 +95,7 @@ void get_bus_conf(void) int i, j; struct mb_sysconf_t *m; - if(get_bus_conf_done == 1) + if (get_bus_conf_done == 1) return; /* do it only once */ get_bus_conf_done = 1; @@ -105,7 +105,7 @@ void get_bus_conf(void) m = sysconf.mb; sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); - for(i = 0; i < sysconf.hc_possible_num; i++) { + for (i = 0; i < sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; } @@ -144,8 +144,9 @@ void get_bus_conf(void) /* HT chain 1 */ j = 0; - for(i = 1; i< sysconf.hc_possible_num; i++) { - if(!(sysconf.pci1234[i] & 0x1) ) continue; + for (i = 1; i < sysconf.hc_possible_num; i++) { + if (!(sysconf.pci1234[i] & 0x1)) + continue; /* check hcid type here */ sysconf.hcid[i] = get_hcid(i); @@ -201,7 +202,7 @@ void get_bus_conf(void) m->apicid_8111 = apicid_base + 0; m->apicid_8132_1 = apicid_base + 1; m->apicid_8132_2 = apicid_base + 2; - for(i = 0; i < j; i++) { + for (i = 0; i < j; i++) { m->apicid_8132a[i][0] = apicid_base + 3 + i * 2; m->apicid_8132a[i][1] = apicid_base + 3 + i * 2 + 1; } diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c index 0927199521..3bc81e9b02 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c @@ -67,8 +67,9 @@ static void *smp_write_config_table(void *v) j = 0; - for(i = 1; i< sysconf.hc_possible_num; i++) { - if(!(sysconf.pci1234[i] & 0x1) ) continue; + for (i = 1; i < sysconf.hc_possible_num; i++) { + if (!(sysconf.pci1234[i] & 0x1)) + continue; switch(sysconf.hcid[i]) { case 1: @@ -106,32 +107,33 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0 << 2)|3, m->apicid_8111, 0x13); /* Slot 3 PCI 32 */ - for(i = 0; i < 4; i++) { + for (i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5 << 2)|i, m->apicid_8111, 0x10 + (1+i)%4); /* 16 */ } /* Slot 4 PCI 32 */ - for(i = 0; i < 4; i++) { + for (i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4 << 2)|i, m->apicid_8111, 0x10 + (0+i)%4); /* 16 */ } /* Slot 1 PCI-X 133/100/66 */ - for(i = 0; i < 4; i++) { + for (i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1 << 2)|i, m->apicid_8132_2, (0+i)%4); } /* Slot 2 PCI-X 133/100/66 */ - for(i = 0; i < 4; i++) { + for (i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1 << 2)|i, m->apicid_8132_1, (1+i)%4); /* 25 */ } j = 0; - for(i = 1; i< sysconf.hc_possible_num; i++) { - if(!(sysconf.pci1234[i] & 0x1) ) continue; + for (i = 1; i < sysconf.hc_possible_num; i++) { + if (!(sysconf.pci1234[i] & 0x1)) + continue; int ii; int jj; struct device *dev; @@ -143,9 +145,9 @@ static void *smp_write_config_table(void *v) if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { - for(jj = 0; jj < 4; jj++) { + for (jj = 0; jj < 4; jj++) { /* Slot 1 PCI-X 133/100/66 */ - for(ii = 0; ii < 4; ii++) { + for (ii = 0; ii < 4; ii++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (jj << 2)|ii, m->apicid_8132a[j][0], (jj+ii)%4); } } @@ -156,9 +158,9 @@ static void *smp_write_config_table(void *v) if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { - for(jj = 0; jj < 4; jj++) { + for (jj = 0; jj < 4; jj++) { /* Slot 2 PCI-X 133/100/66 */ - for(ii = 0; ii < 4; ii++) { + for (ii = 0; ii < 4; ii++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (jj << 2)|ii, m->apicid_8132a[j][1], (jj+ii)%4); /* 25 */ } } diff --git a/src/mainboard/amd/thatcher/BiosCallOuts.c b/src/mainboard/amd/thatcher/BiosCallOuts.c index 9ebcdb2b62..2cbfbdfefc 100644 --- a/src/mainboard/amd/thatcher/BiosCallOuts.c +++ b/src/mainboard/amd/thatcher/BiosCallOuts.c @@ -111,7 +111,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.ImcEnable = TRUE; FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ - FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */ + FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader); diff --git a/src/mainboard/amd/tilapia_fam10/mainboard.c b/src/mainboard/amd/tilapia_fam10/mainboard.c index d4baf8534c..543b77508b 100644 --- a/src/mainboard/amd/tilapia_fam10/mainboard.c +++ b/src/mainboard/amd/tilapia_fam10/mainboard.c @@ -149,7 +149,7 @@ static void set_gpio40_gfx(void) dword &= ~(1 << 10); /* When the gpio40 is configured as GPIO, this will represent the output value*/ - /* 1 :enable two x8 , 0 : master slot enable only */ + /* 1: enable two x8, 0: master slot enable only */ dword |= (1 << 26); pci_write_config32(sm_dev, 0xfc, dword); @@ -161,7 +161,7 @@ static void set_gpio40_gfx(void) dword &= ~(1 << 10); /* When the gpio40 is configured as GPIO, this will represent the output value*/ - /* 1 :enable two x8 , 0 : master slot enable only */ + /* 1: enable two x8, 0: master slot enable only */ dword &= ~(1 << 26); pci_write_config32(sm_dev, 0xfc, dword); } @@ -187,7 +187,7 @@ static void set_thermal_config(void) byte = ADT7461_read_byte(0x02); /* read status register to clear it */ ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */ - printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte); + printk(BIOS_INFO, "Init adt7461 end, status 0x02 %02x\n", byte); /* sb700 settings for thermal config */ /* set SB700 GPIO 64 to GPIO with pull-up */ diff --git a/src/mainboard/amd/torpedo/gpio.c b/src/mainboard/amd/torpedo/gpio.c index 7633cf36f3..4a8861cd33 100644 --- a/src/mainboard/amd/torpedo/gpio.c +++ b/src/mainboard/amd/torpedo/gpio.c @@ -91,7 +91,7 @@ void gpioEarlyInit(void) { Mmio8_And_Or (GpioMmioAddr, Index, 0xA3, gpio_table[Index].value); } if (Index == GPIO_65) { - if ( BoardType == 0 ) { + if (BoardType == 0) { Mmio8_And_Or (IoMuxMmioAddr, GPIO_65, 0x00, 3); // function 3 } } diff --git a/src/mainboard/asus/am1i-a/BiosCallOuts.c b/src/mainboard/asus/am1i-a/BiosCallOuts.c index 6b25d38b01..f70b88db44 100644 --- a/src/mainboard/asus/am1i-a/BiosCallOuts.c +++ b/src/mainboard/asus/am1i-a/BiosCallOuts.c @@ -125,7 +125,7 @@ void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env) /* Read SATA controller mode from CMOS */ enum cb_err ret; ret = get_option(&FchParams_env->Sata.SataClass, "sata_mode"); - if ( ret != CB_SUCCESS) { + if (ret != CB_SUCCESS) { FchParams_env->Sata.SataClass = 0; printk(BIOS_DEBUG, "ERROR: cannot read CMOS setting, falling back to default. Error code: %x\n", (int)ret); } diff --git a/src/mainboard/asus/m4a785-m/mainboard.c b/src/mainboard/asus/m4a785-m/mainboard.c index 00a12cca4b..0a0eedd859 100644 --- a/src/mainboard/asus/m4a785-m/mainboard.c +++ b/src/mainboard/asus/m4a785-m/mainboard.c @@ -133,7 +133,7 @@ static void set_thermal_config(void) byte = ADT7461_read_byte(0x02); /* read status register to clear it */ ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */ - printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte); + printk(BIOS_INFO, "Init adt7461 end, status 0x02 %02x\n", byte); /* sb700 settings for thermal config */ /* set SB700 GPIO 64 to GPIO with pull-up */ @@ -172,7 +172,7 @@ static void set_thermal_config(void) * pm_iowrite(0x55, byte); * * byte = pm_ioread(0x67); - * byte &= ~( 1 << 6); + * byte &= ~(1 << 6); * pm_iowrite(0x67, byte); */ } diff --git a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c index 7723341fb3..ef7cea8f15 100644 --- a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c +++ b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c @@ -114,7 +114,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.ImcEnable = TRUE; FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ - FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */ + FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader); diff --git a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c index 7dc7ac69b4..63eb975cf1 100644 --- a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c +++ b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c @@ -127,7 +127,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.ImcEnable = TRUE; FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ - FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */ + FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader); diff --git a/src/mainboard/biostar/a68n_5200/BiosCallOuts.c b/src/mainboard/biostar/a68n_5200/BiosCallOuts.c index 7698b4bc59..be6b5f5c20 100644 --- a/src/mainboard/biostar/a68n_5200/BiosCallOuts.c +++ b/src/mainboard/biostar/a68n_5200/BiosCallOuts.c @@ -111,7 +111,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.ImcEnable = TRUE; FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ - FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */ + FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader); diff --git a/src/mainboard/biostar/am1ml/romstage.c b/src/mainboard/biostar/am1ml/romstage.c index 7caa4dccb0..20518847ce 100644 --- a/src/mainboard/biostar/am1ml/romstage.c +++ b/src/mainboard/biostar/am1ml/romstage.c @@ -59,37 +59,37 @@ static void ite_exit_conf(pnp_devfn_t dev) static void ite_evc_conf(pnp_devfn_t dev) { ite_enter_conf(dev); - it_sio_write(dev, 0xf1 , 0x40 ); - it_sio_write(dev, 0xf4 , 0x80 ); - it_sio_write(dev, 0xf5 , 0x00 ); - it_sio_write(dev, 0xf6 , 0xf0 ); - it_sio_write(dev, 0xf9 , 0x48 ); - it_sio_write(dev, 0xfa , 0x00 ); - it_sio_write(dev, 0xfb , 0x00 ); + it_sio_write(dev, 0xf1, 0x40); + it_sio_write(dev, 0xf4, 0x80); + it_sio_write(dev, 0xf5, 0x00); + it_sio_write(dev, 0xf6, 0xf0); + it_sio_write(dev, 0xf9, 0x48); + it_sio_write(dev, 0xfa, 0x00); + it_sio_write(dev, 0xfb, 0x00); ite_exit_conf(dev); } static void ite_gpio_conf(pnp_devfn_t dev) { ite_enter_conf (dev); - it_sio_write (dev, 0x25 , 0x80 ); - it_sio_write (dev, 0x26 , 0x07 ); - it_sio_write (dev, 0x28 , 0x81 ); - it_sio_write (dev, 0x2c , 0x06 ); - it_sio_write (dev, 0x72 , 0x00 ); - it_sio_write (dev, 0x73 , 0x00 ); - it_sio_write (dev, 0xb3 , 0x01 ); - it_sio_write (dev, 0xb8 , 0x00 ); - it_sio_write (dev, 0xc0 , 0x00 ); - it_sio_write (dev, 0xc3 , 0x00 ); - it_sio_write (dev, 0xc8 , 0x00 ); - it_sio_write (dev, 0xc9 , 0x07 ); - it_sio_write (dev, 0xcb , 0x01 ); - it_sio_write (dev, 0xf0 , 0x10 ); - it_sio_write (dev, 0xf4 , 0x27 ); - it_sio_write (dev, 0xf8 , 0x20 ); - it_sio_write (dev, 0xf9 , 0x01 ); - ite_exit_conf (dev); + it_sio_write(dev, 0x25, 0x80); + it_sio_write(dev, 0x26, 0x07); + it_sio_write(dev, 0x28, 0x81); + it_sio_write(dev, 0x2c, 0x06); + it_sio_write(dev, 0x72, 0x00); + it_sio_write(dev, 0x73, 0x00); + it_sio_write(dev, 0xb3, 0x01); + it_sio_write(dev, 0xb8, 0x00); + it_sio_write(dev, 0xc0, 0x00); + it_sio_write(dev, 0xc3, 0x00); + it_sio_write(dev, 0xc8, 0x00); + it_sio_write(dev, 0xc9, 0x07); + it_sio_write(dev, 0xcb, 0x01); + it_sio_write(dev, 0xf0, 0x10); + it_sio_write(dev, 0xf4, 0x27); + it_sio_write(dev, 0xf8, 0x20); + it_sio_write(dev, 0xf9, 0x01); + ite_exit_conf(dev); } void board_BeforeAgesa(struct sysinfo *cb) diff --git a/src/mainboard/esd/atom15/romstage.c b/src/mainboard/esd/atom15/romstage.c index 3aa02d8deb..c89a1e2efa 100644 --- a/src/mainboard/esd/atom15/romstage.c +++ b/src/mainboard/esd/atom15/romstage.c @@ -57,7 +57,7 @@ void late_mainboard_romstage_entry() read_ssus_gpio(27), read_ssus_gpio(28), read_ssus_gpio(29), - read_ssus_gpio(30) ); + read_ssus_gpio(30)); } diff --git a/src/mainboard/gigabyte/ma785gmt/mainboard.c b/src/mainboard/gigabyte/ma785gmt/mainboard.c index de90fda029..a0e963190d 100644 --- a/src/mainboard/gigabyte/ma785gmt/mainboard.c +++ b/src/mainboard/gigabyte/ma785gmt/mainboard.c @@ -226,7 +226,7 @@ static void set_thermal_config(void) * pm_iowrite(0x55, byte); * * byte = pm_ioread(0x67); - * byte &= ~( 1 << 6); + * byte &= ~(1 << 6); * pm_iowrite(0x67, byte); */ } diff --git a/src/mainboard/gizmosphere/gizmo/OemCustomize.c b/src/mainboard/gizmosphere/gizmo/OemCustomize.c index c07465c181..e1850d241a 100644 --- a/src/mainboard/gizmosphere/gizmo/OemCustomize.c +++ b/src/mainboard/gizmosphere/gizmo/OemCustomize.c @@ -123,7 +123,7 @@ static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { #define WLSEED 0x08 #define RXSEED 0x40 WRITE_LEVELING_SEED(ANY_SOCKET, ANY_CHANNEL, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED), - HW_RXEN_SEED( ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED), + HW_RXEN_SEED(ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED), PSO_END }; diff --git a/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c b/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c index fd3a821c09..512aea5c91 100644 --- a/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c +++ b/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c @@ -111,7 +111,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.ImcEnable = TRUE; FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ - FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */ + FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader); diff --git a/src/mainboard/google/cyan/variants/banon/gpio.c b/src/mainboard/google/cyan/variants/banon/gpio.c index 92ef836c0d..f9e4e3e362 100644 --- a/src/mainboard/google/cyan/variants/banon/gpio.c +++ b/src/mainboard/google/cyan/variants/banon/gpio.c @@ -66,7 +66,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_NC, /* 69 MMC1_RCLK */ Native_M1, /* 75 GPO USB_OC1_B */ Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA), + GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), /* GPIO_ALERT 77 */ GPIO_NC, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ @@ -127,9 +127,9 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { /* 76 GPI SATA_GP1 */ GPIO_INPUT_PU_20K, /* 77 SATA_LEDN */ GPIO_NC, /* 80 SATA_GP3 */ - Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ + Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */ GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */ - Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ + Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */ Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */ /* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */ Native_M1, /* 90 PCIE_CLKREQ0B */ @@ -156,7 +156,7 @@ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_NC, /* 06 GPIO_DFX8 */ GPIO_NC, /* 07 GPIO_DFX2 */ GPIO_NC, /* 08 GPIO_DFX6 */ - GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data , + GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data, UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */ GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), diff --git a/src/mainboard/google/cyan/variants/celes/gpio.c b/src/mainboard/google/cyan/variants/celes/gpio.c index d011428c3a..b4d8b1e280 100644 --- a/src/mainboard/google/cyan/variants/celes/gpio.c +++ b/src/mainboard/google/cyan/variants/celes/gpio.c @@ -66,13 +66,13 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_NC, /* 69 MMC1_RCLK */ Native_M1, /* 75 GPO USB_OC1_B */ Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA), + GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), /* GPIO_ALERT 77 */ Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ Native_M1, /* 80 USB_OC0_B */ GPI(trig_edge_both, L1, P_20K_H, non_maskable, - en_edge_detect, NA , NA), + en_edge_detect, NA, NA), /* 81 SDMMC3_CD_B */ GPIO_NC, /* 82 spkr assumed gpio number */ Native_M1, /* 83 SUSPWRDNACK */ @@ -132,7 +132,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_NC, /* 78 SATA_GP2 */ GPIO_NC, /* 79 MF_SMB_ALERTB */ GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */ - GPIO_NC, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ + GPIO_NC, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */ GPIO_NC, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */ /* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */ Native_M1, /* 90 PCIE_CLKREQ0B */ @@ -159,7 +159,7 @@ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_NC, /* 06 GPIO_DFX8 */ GPIO_NC, /* 07 GPIO_DFX2 */ GPIO_NC, /* 08 GPIO_DFX6 */ - GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data , + GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data, UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */ GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), diff --git a/src/mainboard/google/cyan/variants/cyan/gpio.c b/src/mainboard/google/cyan/variants/cyan/gpio.c index bf869fec23..4cdfcdf18c 100644 --- a/src/mainboard/google/cyan/variants/cyan/gpio.c +++ b/src/mainboard/google/cyan/variants/cyan/gpio.c @@ -66,7 +66,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_NC, /* 69 MMC1_RCLK */ Native_M1, /* 75 GPO USB_OC1_B */ Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA), + GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), /* GPIO_ALERT 77 */ Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ @@ -130,7 +130,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_NC, /* 78 HSIC AUX1 / SV Mode/ SATA_GP2 */ Native_M1, /* 79 MF_SMB_ALERTB */ GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */ - Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ + Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */ Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */ /* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */ Native_M1, /* 90 PCIE_CLKREQ0B */ @@ -159,7 +159,7 @@ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_NC, /* 06 GPIO_DFX8 */ GPIO_NC, /* 07 GPIO_DFX2 */ GPIO_NC, /* 08 GPIO_DFX6 */ - GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data , + GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data, UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */ GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), diff --git a/src/mainboard/google/cyan/variants/edgar/gpio.c b/src/mainboard/google/cyan/variants/edgar/gpio.c index d9d2648e37..2010ac5172 100644 --- a/src/mainboard/google/cyan/variants/edgar/gpio.c +++ b/src/mainboard/google/cyan/variants/edgar/gpio.c @@ -66,7 +66,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_NC, /* 69 MMC1_RCLK */ Native_M1, /* 75 GPO USB_OC1_B */ Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA), + GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), /* GPIO_ALERT 77 */ Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ @@ -129,7 +129,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_NC, /* 78 SATA_GP2 */ Native_M1, /* 79 MF_SMB_ALERTB */ GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */ - Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ + Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */ Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */ /* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */ GPIO_INPUT_PU_20K, /* 90 PCIE_CLKREQ0B */ @@ -156,7 +156,7 @@ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_NC, /* 06 GPIO_DFX8 */ GPIO_NC, /* 07 GPIO_DFX2 */ GPIO_NC, /* 08 GPIO_DFX6 */ - GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data , + GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data, UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */ GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), diff --git a/src/mainboard/google/cyan/variants/kefka/gpio.c b/src/mainboard/google/cyan/variants/kefka/gpio.c index 76549ba458..d628658228 100644 --- a/src/mainboard/google/cyan/variants/kefka/gpio.c +++ b/src/mainboard/google/cyan/variants/kefka/gpio.c @@ -67,7 +67,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_NC, /* 69 MMC1_RCLK */ Native_M1, /* 75 GPO USB_OC1_B */ Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA), + GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), /* GPIO_ALERT 77 */ Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ @@ -129,7 +129,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_NC, /* 78 SATA_GP2 */ Native_M1, /* 79 MF_SMB_ALERTB */ GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */ - Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ + Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */ Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */ /* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */ GPIO_NC, /* 90 PCIE_CLKREQ0B */ @@ -156,7 +156,7 @@ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_NC, /* 06 GPIO_DFX8 */ GPIO_NC, /* 07 GPIO_DFX2 */ GPIO_NC, /* 08 GPIO_DFX6 */ - GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data , + GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data, UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */ GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), diff --git a/src/mainboard/google/cyan/variants/reks/gpio.c b/src/mainboard/google/cyan/variants/reks/gpio.c index 1a9e5404ef..7b9b5af83d 100644 --- a/src/mainboard/google/cyan/variants/reks/gpio.c +++ b/src/mainboard/google/cyan/variants/reks/gpio.c @@ -66,7 +66,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_NC, /* 69 MMC1_RCLK */ Native_M1, /* 75 GPO USB_OC1_B */ Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA), + GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), /* GPIO_ALERT 77 */ Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ @@ -129,9 +129,9 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { /* 76 GPI SATA_GP1 */ GPIO_INPUT_PU_20K, /* 77 SATA_LEDN-> EC_IN_RW */ GPIO_NC, /* 80 SATA_GP3 */ - Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ + Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */ GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */ - Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ + Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */ Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */ /* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */ Native_M1, /* 90 PCIE_CLKREQ0B */ @@ -158,7 +158,7 @@ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_NC, /* 06 GPIO_DFX8 */ GPIO_NC, /* 07 GPIO_DFX2 */ GPIO_NC, /* 08 GPIO_DFX6 */ - GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data , + GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data, UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */ GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), diff --git a/src/mainboard/google/cyan/variants/relm/gpio.c b/src/mainboard/google/cyan/variants/relm/gpio.c index 6c1dbdced8..95c130073a 100644 --- a/src/mainboard/google/cyan/variants/relm/gpio.c +++ b/src/mainboard/google/cyan/variants/relm/gpio.c @@ -67,7 +67,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_NC, /* 69 MMC1_RCLK */ Native_M1, /* 75 GPO USB_OC1_B */ Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA), + GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), /* GPIO_ALERT 77 */ Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ @@ -130,9 +130,9 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { /* 76 GPI SATA_GP1 */ GPIO_INPUT_PU_20K, /* 77 SATA_LEDN */ GPIO_NC, /* 80 SATA_GP3 */ - Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ + Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */ GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */ - Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ + Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */ Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */ /* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */ Native_M1, /* 90 PCIE_CLKREQ0B */ @@ -159,7 +159,7 @@ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_NC, /* 06 GPIO_DFX8 */ GPIO_NC, /* 07 GPIO_DFX2 */ GPIO_NC, /* 08 GPIO_DFX6 */ - GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data , + GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data, UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */ GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), diff --git a/src/mainboard/google/cyan/variants/setzer/gpio.c b/src/mainboard/google/cyan/variants/setzer/gpio.c index df1bff1cef..1307f7ded6 100644 --- a/src/mainboard/google/cyan/variants/setzer/gpio.c +++ b/src/mainboard/google/cyan/variants/setzer/gpio.c @@ -67,7 +67,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_NC, /* 69 MMC1_RCLK */ Native_M1, /* 75 GPO USB_OC1_B */ Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA), + GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), /* GPIO_ALERT 77 */ Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ @@ -128,9 +128,9 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { /* 76 GPI SATA_GP1 */ GPIO_INPUT_PU_20K, /* 77 SATA_LEDN */ GPIO_NC, /* 78 SATA_GP2 */ - Native_M1, /* 79 NFC_DEV_WAKE , MF_SMB_CLK */ + Native_M1, /* 79 NFC_DEV_WAKE, MF_SMB_CLK */ GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID3 */ - Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ + Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */ Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */ /* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */ GPIO_NC, /* 90 PCIE_CLKREQ0B */ @@ -157,7 +157,7 @@ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_NC, /* 06 GPIO_DFX8 */ GPIO_NC, /* 07 GPIO_DFX2 */ GPIO_NC, /* 08 GPIO_DFX6 */ - GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data , + GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data, UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */ GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), diff --git a/src/mainboard/google/cyan/variants/terra/gpio.c b/src/mainboard/google/cyan/variants/terra/gpio.c index 8328eddfec..b4feebff16 100644 --- a/src/mainboard/google/cyan/variants/terra/gpio.c +++ b/src/mainboard/google/cyan/variants/terra/gpio.c @@ -66,7 +66,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_NC, /* 69 MMC1_RCLK */ Native_M1, /* 75 GPO USB_OC1_B */ Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA), + GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), /* GPIO_ALERT 77 */ Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ @@ -128,7 +128,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_NC, /* 78 SATA_GP2 */ GPIO_NC, /* 79 MF_SMB_ALERTB */ GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */ - Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ + Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */ Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */ /* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */ Native_M1, /* 90 PCIE_CLKREQ0B */ @@ -155,7 +155,7 @@ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_NC, /* 06 GPIO_DFX8 */ GPIO_NC, /* 07 GPIO_DFX2 */ GPIO_NC, /* 08 GPIO_DFX6 */ - GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data , + GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data, UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */ GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), diff --git a/src/mainboard/google/cyan/variants/ultima/gpio.c b/src/mainboard/google/cyan/variants/ultima/gpio.c index c6875b4ef2..43f1099a54 100644 --- a/src/mainboard/google/cyan/variants/ultima/gpio.c +++ b/src/mainboard/google/cyan/variants/ultima/gpio.c @@ -66,7 +66,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_NC, /* 69 MMC1_RCLK */ Native_M1, /* 75 GPO USB_OC1_B */ Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA), + GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), /* GPIO_ALERT 77 */ Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ @@ -129,9 +129,9 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { /* 76 GPI SATA_GP1 */ GPIO_INPUT_PU_20K, /* 77 SATA_LEDN-> EC_IN_RW */ GPIO_NC, /* 80 SATA_GP3 */ - Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ + Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */ GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */ - Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ + Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */ Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */ /* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */ Native_M1, /* 90 PCIE_CLKREQ0B */ @@ -158,7 +158,7 @@ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_NC, /* 06 GPIO_DFX8 */ GPIO_NC, /* 07 GPIO_DFX2 */ GPIO_NC, /* 08 GPIO_DFX6 */ - GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data , + GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data, UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */ GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), diff --git a/src/mainboard/google/cyan/variants/wizpig/gpio.c b/src/mainboard/google/cyan/variants/wizpig/gpio.c index 361143932c..3d3b27359e 100644 --- a/src/mainboard/google/cyan/variants/wizpig/gpio.c +++ b/src/mainboard/google/cyan/variants/wizpig/gpio.c @@ -66,7 +66,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_NC, /* 69 MMC1_RCLK */ Native_M1, /* 75 GPO USB_OC1_B */ Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA), + GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), /* GPIO_ALERT 77 */ Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ @@ -128,9 +128,9 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_NC, /* 76 GPI SATA_GP1 */ GPIO_INPUT_PU_20K, /* 77 SATA_LEDN */ GPIO_NC, /* 78 SATA_GP2 */ - Native_M1, /* 79 NFC_DEV_WAKE , MF_SMB_CLK */ + Native_M1, /* 79 NFC_DEV_WAKE, MF_SMB_CLK */ GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */ - Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ + Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */ Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */ /* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */ GPIO_NC, /* 90 PCIE_CLKREQ0B */ @@ -157,7 +157,7 @@ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_NC, /* 06 GPIO_DFX8 */ GPIO_NC, /* 07 GPIO_DFX2 */ GPIO_NC, /* 08 GPIO_DFX6 */ - GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data , + GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data, UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */ GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), diff --git a/src/mainboard/google/eve/romstage.c b/src/mainboard/google/eve/romstage.c index 6f8ff0f19c..975eea5819 100644 --- a/src/mainboard/google/eve/romstage.c +++ b/src/mainboard/google/eve/romstage.c @@ -27,7 +27,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; /* DQ byte map */ const u8 dq_map[2][12] = { - { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0 , + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; diff --git a/src/mainboard/google/glados/variants/lars/variant.c b/src/mainboard/google/glados/variants/lars/variant.c index 297b149b4b..4fe88ef7c8 100644 --- a/src/mainboard/google/glados/variants/lars/variant.c +++ b/src/mainboard/google/glados/variants/lars/variant.c @@ -33,9 +33,9 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { /* DQ byte map */ const u8 dq_map[2][12] = { - { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0 , + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, - { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0 , + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; /* DQS CPU<>DRAM map */ const u8 dqs_map[2][8] = { diff --git a/src/mainboard/google/gru/boardid.c b/src/mainboard/google/gru/boardid.c index aaa8ae7d0b..5b2985a7c2 100644 --- a/src/mainboard/google/gru/boardid.c +++ b/src/mainboard/google/gru/boardid.c @@ -65,7 +65,7 @@ static uint32_t get_index(uint32_t channel, int *cached_id) } } - die("Read impossible value ( > 1023) from 10-bit ADC!"); + die("Read impossible value (> 1023) from 10-bit ADC!"); } uint32_t board_id(void) diff --git a/src/mainboard/google/link/i915.c b/src/mainboard/google/link/i915.c index 8b8000cb98..8bd758b958 100644 --- a/src/mainboard/google/link/i915.c +++ b/src/mainboard/google/link/i915.c @@ -295,7 +295,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, index = run(index); auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_LINK_BW_SET << 8|0x8; auxout[1] = 0x0a840000; - /*( DP_LINK_BW_2_7 &0xa)|0x0000840a*/ + /*(DP_LINK_BW_2_7 &0xa)|0x0000840a*/ auxout[2] = 0x00000000; auxout[3] = 0x01000000; intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 13, auxin, 0); diff --git a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c index a82ddf9f0b..201198d629 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c @@ -112,7 +112,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.ImcEnable = TRUE; FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ - FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */ + FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader); diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c index ed79dad524..7ab5eb1221 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c @@ -365,9 +365,9 @@ GPIO_CONTROL pavilion_m6_1035dx_gpio[] = { #define SCI_MAP_PWRBTN 0x73 SCI_MAP_CONTROL m6_1035dx_sci_map[] = { - {GEVENT_PIN( EC_SCI_GEVENT ), EC_SCI_GPE}, - {GEVENT_PIN( EC_LID_GEVENT ), EC_LID_GPE}, - {GEVENT_PIN( PCIE_GEVENT ), PCIE_GPE}, + {GEVENT_PIN(EC_SCI_GEVENT), EC_SCI_GPE}, + {GEVENT_PIN(EC_LID_GEVENT), EC_LID_GPE}, + {GEVENT_PIN(PCIE_GEVENT), PCIE_GPE}, {SCI_MAP_OHCI_12_0, PME_GPE}, {SCI_MAP_OHCI_13_0, PME_GPE}, {SCI_MAP_XHCI_10_0, PME_GPE}, diff --git a/src/mainboard/intel/bayleybay_fsp/romstage.c b/src/mainboard/intel/bayleybay_fsp/romstage.c index d98802344c..199a15e3e6 100644 --- a/src/mainboard/intel/bayleybay_fsp/romstage.c +++ b/src/mainboard/intel/bayleybay_fsp/romstage.c @@ -65,67 +65,67 @@ const uint32_t mAzaliaVerbTableData13[] = { /* *ALC262 Verb Table - 10EC0262 */ - /* Pin Complex (NID 0x11 ) */ + /* Pin Complex (NID 0x11) */ 0x01171CF0, 0x01171D11, 0x01171E11, 0x01171F41, - /* Pin Complex (NID 0x12 ) */ + /* Pin Complex (NID 0x12) */ 0x01271CF0, 0x01271D11, 0x01271E11, 0x01271F41, - /* Pin Complex (NID 0x14 ) */ + /* Pin Complex (NID 0x14) */ 0x01471C10, 0x01471D40, 0x01471E01, 0x01471F01, - /* Pin Complex (NID 0x15 ) */ + /* Pin Complex (NID 0x15) */ 0x01571CF0, 0x01571D11, 0x01571E11, 0x01571F41, - /* Pin Complex (NID 0x16 ) */ + /* Pin Complex (NID 0x16) */ 0x01671CF0, 0x01671D11, 0x01671E11, 0x01671F41, - /* Pin Complex (NID 0x18 ) */ + /* Pin Complex (NID 0x18) */ 0x01871C20, 0x01871D98, 0x01871EA1, 0x01871F01, - /* Pin Complex (NID 0x19 ) */ + /* Pin Complex (NID 0x19) */ 0x01971C21, 0x01971D98, 0x01971EA1, 0x01971F02, - /* Pin Complex (NID 0x1A ) */ + /* Pin Complex (NID 0x1A) */ 0x01A71C2F, 0x01A71D30, 0x01A71E81, 0x01A71F01, - /* Pin Complex (NID 0x1B ) */ + /* Pin Complex (NID 0x1B) */ 0x01B71C1F, 0x01B71D40, 0x01B71E21, 0x01B71F02, - /* Pin Complex (NID 0x1C ) */ + /* Pin Complex (NID 0x1C) */ 0x01C71CF0, 0x01C71D11, 0x01C71E11, 0x01C71F41, - /* Pin Complex (NID 0x1D ) */ + /* Pin Complex (NID 0x1D) */ 0x01D71C01, 0x01D71DC6, 0x01D71E14, 0x01D71F40, - /* Pin Complex (NID 0x1E ) */ + /* Pin Complex (NID 0x1E) */ 0x01E71CF0, 0x01E71D11, 0x01E71E11, 0x01E71F41, - /* Pin Complex (NID 0x1F ) */ + /* Pin Complex (NID 0x1F) */ 0x01F71CF0, 0x01F71D11, 0x01F71E11, diff --git a/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c b/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c index 4e2f31fc4b..31f5452603 100644 --- a/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c +++ b/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c @@ -23,7 +23,7 @@ void mainboard_fill_dq_map_ch0(void *dq_map_ptr) { /* DQ byte map Ch0 */ const u8 dq_map[12] = { - 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00 , + 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c index 38af2b881b..f6c867a001 100644 --- a/src/mainboard/intel/cougar_canyon2/romstage.c +++ b/src/mainboard/intel/cougar_canyon2/romstage.c @@ -261,7 +261,7 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) { /* For reference print FSP version */ u32 version = MCHBAR32(0x5034); printk(BIOS_DEBUG, "FSP Version %d.%d.%d Build %d\n", - version >> 24 , (version >> 16) & 0xff, + version >> 24, (version >> 16) & 0xff, (version >> 8) & 0xff, version & 0xff); printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status); diff --git a/src/mainboard/intel/kunimitsu/spd/spd_util.c b/src/mainboard/intel/kunimitsu/spd/spd_util.c index 676f84d01c..fc0581cb24 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd_util.c +++ b/src/mainboard/intel/kunimitsu/spd/spd_util.c @@ -26,9 +26,9 @@ void mainboard_fill_dq_map_data(void *dq_map_ptr) { /* DQ byte map */ const u8 dq_map[2][12] = { - { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0 , + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, - { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0 , + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); } diff --git a/src/mainboard/intel/strago/gpio.c b/src/mainboard/intel/strago/gpio.c index fa24594ee0..ed9ae4b4d1 100644 --- a/src/mainboard/intel/strago/gpio.c +++ b/src/mainboard/intel/strago/gpio.c @@ -69,7 +69,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_NC, /* 69 MMC1_RCLK */ Native_M1, /* 75 GPO USB_OC1_B */ Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA), + GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), /* GPIO_ALERT 77 */ Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ @@ -131,11 +131,11 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_OUT_HIGH, /* 75 SATA_GP0 */ GPIO_NC, /* 76 GPI SATA_GP1 */ - GPIO_INPUT_PU_20K, /* 77 SATA_LEDN , EC_IN_RW */ + GPIO_INPUT_PU_20K, /* 77 SATA_LEDN, EC_IN_RW */ GPIO_NC, /* 80 SATA_GP3 */ - Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ + Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */ GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */ - Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ + Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */ Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */ /* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */ Native_M1, /* 90 PCIE_CLKREQ0B */ @@ -162,7 +162,7 @@ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_NC, /* 06 GPIO_DFX8 */ GPIO_NC, /* 07 GPIO_DFX2 */ GPIO_NC, /* 08 GPIO_DFX6 */ - GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data , + GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data, UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */ GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), diff --git a/src/mainboard/lenovo/g505s/BiosCallOuts.c b/src/mainboard/lenovo/g505s/BiosCallOuts.c index a82ddf9f0b..201198d629 100644 --- a/src/mainboard/lenovo/g505s/BiosCallOuts.c +++ b/src/mainboard/lenovo/g505s/BiosCallOuts.c @@ -112,7 +112,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.ImcEnable = TRUE; FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ - FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */ + FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader); diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c index 9ef46d5708..3eaa8b07fb 100644 --- a/src/mainboard/lenovo/g505s/buildOpts.c +++ b/src/mainboard/lenovo/g505s/buildOpts.c @@ -365,9 +365,9 @@ GPIO_CONTROL lenovo_g505s_gpio[] = { #define SCI_MAP_PWRBTN 0x73 SCI_MAP_CONTROL lenovo_g505s_sci_map[] = { - {GEVENT_PIN( EC_SCI_GEVENT ), EC_SCI_GPE}, - {GEVENT_PIN( EC_LID_GEVENT ), EC_LID_GPE}, - {GEVENT_PIN( PCIE_GEVENT ), PCIE_GPE}, + {GEVENT_PIN(EC_SCI_GEVENT), EC_SCI_GPE}, + {GEVENT_PIN(EC_LID_GEVENT), EC_LID_GPE}, + {GEVENT_PIN(PCIE_GEVENT), PCIE_GPE}, {SCI_MAP_OHCI_12_0, PME_GPE}, {SCI_MAP_OHCI_13_0, PME_GPE}, {SCI_MAP_XHCI_10_0, PME_GPE}, diff --git a/src/mainboard/lenovo/t430s/romstage.c b/src/mainboard/lenovo/t430s/romstage.c index b409b5e59b..203044e312 100644 --- a/src/mainboard/lenovo/t430s/romstage.c +++ b/src/mainboard/lenovo/t430s/romstage.c @@ -43,7 +43,7 @@ void mainboard_rcba_config(void) } const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, /* P0: , OC 0 */ + { 1, 0, 0 }, /* P0:, OC 0 */ { 1, 1, 1 }, /* P1: (EHCI debug), OC 1 */ { 1, 1, 3 }, /* P2: OC 3 */ { 1, 0, -1 }, /* P3: no OC */ diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index e4a8efb608..3d4baa5355 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -183,7 +183,7 @@ void mainboard_romstage_entry(unsigned long bist) /* We want early GPIO setup, to be able to detect legacy I/O module */ pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); /* Enable GPIOs */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */ , 0x10); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */, 0x10); setup_pch_gpios(&mainboard_gpio_map); dock_err = dlpc_init(); diff --git a/src/mainboard/lenovo/t60/smihandler.c b/src/mainboard/lenovo/t60/smihandler.c index 7707d624c8..bccb7f128a 100644 --- a/src/mainboard/lenovo/t60/smihandler.c +++ b/src/mainboard/lenovo/t60/smihandler.c @@ -49,7 +49,7 @@ static void mainboard_smi_brightness_up(void) { u8 *bar; if ((bar = (u8 *)pci_read_config32(PCI_DEV(1, 0, 0), 0x18))) { - printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int )bar, *(bar+LVTMA_BL_MOD_LEVEL)); + printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, *(bar+LVTMA_BL_MOD_LEVEL)); *(bar+LVTMA_BL_MOD_LEVEL) |= 0x0f; if (*(bar+LVTMA_BL_MOD_LEVEL) < 0xf0) *(bar+LVTMA_BL_MOD_LEVEL) += 0x10; diff --git a/src/mainboard/lenovo/x60/dock.c b/src/mainboard/lenovo/x60/dock.c index 5b49498a84..f55428e66d 100644 --- a/src/mainboard/lenovo/x60/dock.c +++ b/src/mainboard/lenovo/x60/dock.c @@ -190,7 +190,7 @@ int dock_connect(void) dock_gpio_set_mode(0x14, PC87392_GPIO_PIN_PULLUP, 0x00); dock_gpio_set_mode(0x15, PC87392_GPIO_PIN_PULLUP, 0x00); dock_gpio_set_mode(0x16, PC87392_GPIO_PIN_PULLUP | - PC87392_GPIO_PIN_OE , 0x00); + PC87392_GPIO_PIN_OE, 0x00); dock_gpio_set_mode(0x17, PC87392_GPIO_PIN_PULLUP, 0x00); diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c index 94c8a8fe03..d5dc9f57f5 100644 --- a/src/mainboard/lenovo/z61t/romstage.c +++ b/src/mainboard/lenovo/z61t/romstage.c @@ -183,7 +183,7 @@ void mainboard_romstage_entry(unsigned long bist) /* We want early GPIO setup, to be able to detect legacy I/O module */ pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); /* Enable GPIOs */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */ , 0x10); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */, 0x10); setup_pch_gpios(&mainboard_gpio_map); dock_err = dlpc_init(); diff --git a/src/mainboard/lenovo/z61t/smihandler.c b/src/mainboard/lenovo/z61t/smihandler.c index d98a80957b..b93f48ee92 100644 --- a/src/mainboard/lenovo/z61t/smihandler.c +++ b/src/mainboard/lenovo/z61t/smihandler.c @@ -50,7 +50,7 @@ static void mainboard_smi_brightness_up(void) { u8 *bar; if ((bar = (u8 *)pci_read_config32(PCI_DEV(1, 0, 0), 0x18))) { - printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int )bar, + printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, *(bar+LVTMA_BL_MOD_LEVEL)); *(bar+LVTMA_BL_MOD_LEVEL) |= 0x0f; if (*(bar+LVTMA_BL_MOD_LEVEL) < 0xf0) diff --git a/src/mainboard/lippert/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/mainboard.c index 3866035f30..cc25957dd1 100644 --- a/src/mainboard/lippert/frontrunner-af/mainboard.c +++ b/src/mainboard/lippert/frontrunner-af/mainboard.c @@ -65,19 +65,19 @@ static void init(struct device *dev) /* Init Hudson GPIOs. */ printk(BIOS_DEBUG, "Init FCH GPIOs @ 0x%08x\n", ACPI_MMIO_BASE+GPIO_BASE); - FCH_IOMUX( 50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices - FCH_GPIO ( 50) = 0xC0; // = output set to 1 as it's never needed + FCH_IOMUX(50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices + FCH_GPIO (50) = 0xC0; // = output set to 1 as it's never needed FCH_IOMUX(197) = 2; // GPIO197: BIOS_DEFAULTS# = input (int. PU) - FCH_IOMUX( 56) = 1; // GPIO58-56: REV_ID2-0 - FCH_GPIO ( 56) = 0x28; // = inputs, disable int. pull-ups - FCH_IOMUX( 57) = 1; - FCH_GPIO ( 57) = 0x28; - FCH_IOMUX( 58) = 1; - FCH_GPIO ( 58) = 0x28; - FCH_IOMUX( 96) = 1; // "Gpio96": GEVENT0# signal on X2 connector (int. PU) - FCH_IOMUX( 52) = 1; // GPIO52,61,62,187-192 free to use on X2 connector - FCH_IOMUX( 61) = 2; // default to inputs with int. PU - FCH_IOMUX( 62) = 2; + FCH_IOMUX(56) = 1; // GPIO58-56: REV_ID2-0 + FCH_GPIO (56) = 0x28; // = inputs, disable int. pull-ups + FCH_IOMUX(57) = 1; + FCH_GPIO (57) = 0x28; + FCH_IOMUX(58) = 1; + FCH_GPIO (58) = 0x28; + FCH_IOMUX(96) = 1; // "Gpio96": GEVENT0# signal on X2 connector (int. PU) + FCH_IOMUX(52) = 1; // GPIO52,61,62,187-192 free to use on X2 connector + FCH_IOMUX(61) = 2; // default to inputs with int. PU + FCH_IOMUX(62) = 2; FCH_IOMUX(187) = 2; FCH_IOMUX(188) = 2; FCH_IOMUX(189) = 1; diff --git a/src/mainboard/lippert/toucan-af/mainboard.c b/src/mainboard/lippert/toucan-af/mainboard.c index 3de388ba41..cea5350542 100644 --- a/src/mainboard/lippert/toucan-af/mainboard.c +++ b/src/mainboard/lippert/toucan-af/mainboard.c @@ -33,16 +33,16 @@ static void init(struct device *dev) /* Init Hudson GPIOs. */ printk(BIOS_DEBUG, "Init FCH GPIOs @ 0x%08x\n", ACPI_MMIO_BASE+GPIO_BASE); - FCH_IOMUX( 50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices - FCH_GPIO ( 50) = 0xC0; // = output set to 1 as it's never needed + FCH_IOMUX(50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices + FCH_GPIO (50) = 0xC0; // = output set to 1 as it's never needed FCH_IOMUX(197) = 2; // GPIO197: BIOS_DEFAULTS# FCH_GPIO (197) = 0x28; // = input, disable int. pull-up - FCH_IOMUX( 56) = 1; // GPIO58-56: REV_ID2-0 - FCH_GPIO ( 56) = 0x28; // = inputs, disable int. pull-ups - FCH_IOMUX( 57) = 1; - FCH_GPIO ( 57) = 0x28; - FCH_IOMUX( 58) = 1; - FCH_GPIO ( 58) = 0x28; + FCH_IOMUX(56) = 1; // GPIO58-56: REV_ID2-0 + FCH_GPIO (56) = 0x28; // = inputs, disable int. pull-ups + FCH_IOMUX(57) = 1; + FCH_GPIO (57) = 0x28; + FCH_IOMUX(58) = 1; + FCH_GPIO (58) = 0x28; FCH_IOMUX(187) = 2; // GPIO187,188,166,GPO160: GPO0-3 on COM Express connector FCH_GPIO (187) = 0x08; // = outputs, disable PUs, default to 0 FCH_IOMUX(188) = 2; diff --git a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c index c5ceb75749..9c744ced1a 100644 --- a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c +++ b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c @@ -101,12 +101,12 @@ void get_bus_conf(void) } for (i = 2; i < 8; i++) { - dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0)); + dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); if (dev) { m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 ); + printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); } } diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 8538d33a50..4555bf94c1 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -87,13 +87,13 @@ static void sio_setup(void) u32 dword; u8 byte; - byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); + byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0x7b); byte |= 0x20; - pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); + pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0x7b, byte); - dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa0); dword |= (1 << 0); - pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); + pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa0, dword); } static const u8 spd_addr[] = { diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c index 8fe2dc09d5..e482840431 100644 --- a/src/mainboard/pcengines/alix1c/romstage.c +++ b/src/mainboard/pcengines/alix1c/romstage.c @@ -44,7 +44,7 @@ * 4banks (2) * SSTL_2 (2) * 4th GEN die (C) - * Normal Power Consumption (<blank> ) + * Normal Power Consumption (<blank>) * TSOP (T) * Single Die (<blank>) * Lead Free (P) diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c index da3913d2a4..9bb9c00d2d 100644 --- a/src/mainboard/pcengines/alix2d/romstage.c +++ b/src/mainboard/pcengines/alix2d/romstage.c @@ -42,7 +42,7 @@ * 4banks (2) * SSTL_2 (2) * 4th GEN die (C) - * Normal Power Consumption (<blank> ) + * Normal Power Consumption (<blank>) * TSOP (T) * Single Die (<blank>) * Lead Free (P) diff --git a/src/mainboard/pcengines/apu1/OemCustomize.c b/src/mainboard/pcengines/apu1/OemCustomize.c index 330531f7e4..9febec73d0 100644 --- a/src/mainboard/pcengines/apu1/OemCustomize.c +++ b/src/mainboard/pcengines/apu1/OemCustomize.c @@ -108,7 +108,7 @@ static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { #define WLSEED 0x08 #define RXSEED 0x40 WRITE_LEVELING_SEED(ANY_SOCKET, ANY_CHANNEL, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED), - HW_RXEN_SEED( ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED), + HW_RXEN_SEED(ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED), PSO_END }; diff --git a/src/mainboard/pcengines/apu1/gpio_ftns.c b/src/mainboard/pcengines/apu1/gpio_ftns.c index 74c3b7b5ac..7a988e7ec6 100644 --- a/src/mainboard/pcengines/apu1/gpio_ftns.c +++ b/src/mainboard/pcengines/apu1/gpio_ftns.c @@ -25,9 +25,9 @@ uintptr_t find_gpio_base(void) uintptr_t base_addr = 0; /* Find the ACPImmioAddr base address */ - for ( pm_index = 0x27; pm_index > 0x23; pm_index-- ) { - outb( pm_index, PM_INDEX ); - pm_data = inb( PM_DATA ); + for (pm_index = 0x27; pm_index > 0x23; pm_index--) { + outb(pm_index, PM_INDEX); + pm_data = inb(PM_DATA); base_addr <<= 8; base_addr |= (u32)pm_data; } diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c index 8e2636bdfc..1c7b4fd7a9 100644 --- a/src/mainboard/pcengines/apu2/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c @@ -99,7 +99,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) FchParams->Usb.Ehci1Enable = TRUE; } - // Enable EHCI 1 ( port 4 to 7) + // Enable EHCI 1 (port 4 to 7) // port 4 and 5 to EHCI header port 6 and 7 to PCIe slot. FchParams->Usb.Ehci2Enable = TRUE; diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c index 9434b938f4..99ddf80373 100644 --- a/src/mainboard/pcengines/apu2/mainboard.c +++ b/src/mainboard/pcengines/apu2/mainboard.c @@ -167,12 +167,12 @@ static void mainboard_enable(struct device *dev) // // Enable the RTC output // - pm_write16 ( PM_RTC_CONTROL, pm_read16( PM_RTC_CONTROL ) | (1 << 11)); + pm_write16(PM_RTC_CONTROL, pm_read16(PM_RTC_CONTROL) | (1 << 11)); // // Enable power on from WAKE# // - pm_write16 ( PM_S_STATE_CONTROL, pm_read16( PM_S_STATE_CONTROL ) | (1 << 14)); + pm_write16(PM_S_STATE_CONTROL, pm_read16(PM_S_STATE_CONTROL) | (1 << 14)); /* Initialize the PIRQ data structures for consumption */ pirq_setup(); diff --git a/src/mainboard/siemens/mc_tcu3/ptn3460.c b/src/mainboard/siemens/mc_tcu3/ptn3460.c index 89bc29399e..8143a16957 100644 --- a/src/mainboard/siemens/mc_tcu3/ptn3460.c +++ b/src/mainboard/siemens/mc_tcu3/ptn3460.c @@ -53,7 +53,7 @@ int ptn3460_init(char *hwi_block) hwi_block); return 1; } - if (hwilib_get_field(PF_Color_Depth ,&color_depth, 1) != 1) { + if (hwilib_get_field(PF_Color_Depth, &color_depth, 1) != 1) { printk(BIOS_ERR, "LCD: Missing panel features from %s\n", hwi_block); return 1; diff --git a/src/mainboard/siemens/mc_tcu3/romstage.c b/src/mainboard/siemens/mc_tcu3/romstage.c index 628e88b9f1..ef07f7e4fc 100644 --- a/src/mainboard/siemens/mc_tcu3/romstage.c +++ b/src/mainboard/siemens/mc_tcu3/romstage.c @@ -66,67 +66,67 @@ const uint32_t mAzaliaVerbTableData13[] = { /* *ALC262 Verb Table - 10EC0262 */ - /* Pin Complex (NID 0x11 ) */ + /* Pin Complex (NID 0x11) */ 0x01171CF0, 0x01171D11, 0x01171E11, 0x01171F41, - /* Pin Complex (NID 0x12 ) */ + /* Pin Complex (NID 0x12) */ 0x01271CF0, 0x01271D11, 0x01271E11, 0x01271F41, - /* Pin Complex (NID 0x14 ) */ + /* Pin Complex (NID 0x14) */ 0x01471C10, 0x01471D40, 0x01471E01, 0x01471F01, - /* Pin Complex (NID 0x15 ) */ + /* Pin Complex (NID 0x15) */ 0x01571CF0, 0x01571D11, 0x01571E11, 0x01571F41, - /* Pin Complex (NID 0x16 ) */ + /* Pin Complex (NID 0x16) */ 0x01671CF0, 0x01671D11, 0x01671E11, 0x01671F41, - /* Pin Complex (NID 0x18 ) */ + /* Pin Complex (NID 0x18) */ 0x01871C20, 0x01871D98, 0x01871EA1, 0x01871F01, - /* Pin Complex (NID 0x19 ) */ + /* Pin Complex (NID 0x19) */ 0x01971C21, 0x01971D98, 0x01971EA1, 0x01971F02, - /* Pin Complex (NID 0x1A ) */ + /* Pin Complex (NID 0x1A) */ 0x01A71C2F, 0x01A71D30, 0x01A71E81, 0x01A71F01, - /* Pin Complex (NID 0x1B ) */ + /* Pin Complex (NID 0x1B) */ 0x01B71C1F, 0x01B71D40, 0x01B71E21, 0x01B71F02, - /* Pin Complex (NID 0x1C ) */ + /* Pin Complex (NID 0x1C) */ 0x01C71CF0, 0x01C71D11, 0x01C71E11, 0x01C71F41, - /* Pin Complex (NID 0x1D ) */ + /* Pin Complex (NID 0x1D) */ 0x01D71C01, 0x01D71DC6, 0x01D71E14, 0x01D71F40, - /* Pin Complex (NID 0x1E ) */ + /* Pin Complex (NID 0x1E) */ 0x01E71CF0, 0x01E71D11, 0x01E71E11, 0x01E71F41, - /* Pin Complex (NID 0x1F ) */ + /* Pin Complex (NID 0x1F) */ 0x01F71CF0, 0x01F71D11, 0x01F71E11, diff --git a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c index b2bc0ddd31..58b5ba4ff9 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c +++ b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c @@ -99,12 +99,12 @@ void get_bus_conf(void) } for(i = 2; i < 8; i++) { - dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0)); + dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); if (dev) { m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 ); + printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); } } diff --git a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c index 75b1347aba..b3195584fd 100644 --- a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c +++ b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c @@ -105,12 +105,12 @@ void get_bus_conf(void) } for(i = 2; i < 8; i++) { - dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0)); + dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); if (dev) { m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 ); + printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); } } diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 6aa20bbc2a..e51cf19ce2 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -89,17 +89,17 @@ static void sio_setup(void) // smbusx_write_byte(1, (0x58 >> 1), 0, 0x80); /* select bank0 */ smbusx_write_byte(1, (0x58 >> 1), 0xb1, 0xff); /* set FAN ctrl to DC mode */ - byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); + byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0x7b); byte |= 0x20; - pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); + pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0x7b, byte); - dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa0); dword |= (1 << 0); - pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); + pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa0, dword); - dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa4); dword |= (1 << 16); - pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); + pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa4, dword); } static const u8 spd_addr[] = { @@ -113,7 +113,7 @@ static const u8 spd_addr[] = { /* third node */ RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, /* fourth node */ - RC03, DIMM4, DIMM6,0 , 0, DIMM5, DIMM7, 0, 0, + RC03, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, #endif }; diff --git a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c index 09704f876b..7164940b91 100644 --- a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c +++ b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c @@ -98,12 +98,12 @@ void get_bus_conf(void) } for(i = 2; i < 8; i++) { - dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0)); + dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); if (dev) { m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 ); + printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); } } diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 7c4fd5b4bc..2d302f12d8 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -87,18 +87,18 @@ static void sio_setup(void) uint32_t dword; uint8_t byte; - byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); + byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0x7b); byte |= 0x20; - pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); + pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0x7b, byte); - dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa0); /*serial 0 */ dword |= (1 << 0); - pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); + pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa0, dword); - dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa4); dword |= (1 << 16); - pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); + pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa4, dword); } static const u8 spd_addr[] = { |