10 files changed, 0 insertions, 20 deletions
diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c
index d8d5aa99f7..f8c3aec66b 100644
--- a/src/mainboard/amd/serengeti_cheetah/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah/romstage.c
@@ -135,9 +135,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 
-#if CONFIG_MEM_TRAIN_SEQ == 1
         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
-#endif
 	setup_coherent_ht_domain(); // routing table and start other core0
 
 	wait_all_core0_started();
diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c
index 8250743d86..fea1984843 100644
--- a/src/mainboard/asus/m2n-e/romstage.c
+++ b/src/mainboard/asus/m2n-e/romstage.c
@@ -121,10 +121,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo, sysinfo + 1);
 	printk(BIOS_DEBUG, "bsp_apicid=0x%02x\n", bsp_apicid);
 
-#if CONFIG_MEM_TRAIN_SEQ == 1
 	/* In BSP so could hold all AP until sysinfo is in RAM. */
 	set_sysinfo_in_ram(0);
-#endif
 
 	setup_coherent_ht_domain(); /* Routing table and start other core0. */
 	wait_all_core0_started();
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
index f770577ddf..633daad09a 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
@@ -145,9 +145,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 
-#if CONFIG_MEM_TRAIN_SEQ == 1
         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
-#endif
         setup_coherent_ht_domain(); // routing table and start other core0
 
         wait_all_core0_started();
diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c
index 88f3d2558a..3fbaacb8b7 100644
--- a/src/mainboard/gigabyte/m57sli/romstage.c
+++ b/src/mainboard/gigabyte/m57sli/romstage.c
@@ -148,9 +148,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 
-#if CONFIG_MEM_TRAIN_SEQ == 1
         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
-#endif
         setup_coherent_ht_domain(); // routing table and start other core0
 
         wait_all_core0_started();
diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c
index 48a4f9d658..e53b52712d 100644
--- a/src/mainboard/hp/dl145_g3/romstage.c
+++ b/src/mainboard/hp/dl145_g3/romstage.c
@@ -158,9 +158,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 	printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
 
-#if CONFIG_MEM_TRAIN_SEQ == 1
 	set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
-#endif
 	setup_coherent_ht_domain();
 
 	wait_all_core0_started();
diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c
index c3bdc581c7..efe2102909 100644
--- a/src/mainboard/msi/ms7260/romstage.c
+++ b/src/mainboard/msi/ms7260/romstage.c
@@ -139,10 +139,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	print_debug_hex8(bsp_apicid);
 	print_debug("\n");
 
-#if CONFIG_MEM_TRAIN_SEQ == 1
 	/* In BSP so could hold all AP until sysinfo is in RAM. */
 	set_sysinfo_in_ram(0);
-#endif
 
 	setup_coherent_ht_domain(); /* Routing table and start other core0. */
 	wait_all_core0_started();
diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c
index 305ab661d9..06b4c983b5 100644
--- a/src/mainboard/nvidia/l1_2pvv/romstage.c
+++ b/src/mainboard/nvidia/l1_2pvv/romstage.c
@@ -137,9 +137,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 
-#if CONFIG_MEM_TRAIN_SEQ == 1
 	set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
-#endif
 	setup_coherent_ht_domain(); // routing table and start other core0
 
 	wait_all_core0_started();
diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c
index 1505794781..48c6156572 100644
--- a/src/mainboard/supermicro/h8dme/romstage.c
+++ b/src/mainboard/supermicro/h8dme/romstage.c
@@ -205,9 +205,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	print_debug_hex8(bsp_apicid);
 	print_debug("\n");
 
-#if CONFIG_MEM_TRAIN_SEQ == 1
 	set_sysinfo_in_ram(0);	// in BSP so could hold all ap until sysinfo is in ram
-#endif
 /*	dump_smbus_registers(); */
 	setup_coherent_ht_domain();	// routing table and start other core0
 
diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c
index 2709e1d201..c97eef30bd 100644
--- a/src/mainboard/supermicro/h8dmr/romstage.c
+++ b/src/mainboard/supermicro/h8dmr/romstage.c
@@ -132,9 +132,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 
-#if CONFIG_MEM_TRAIN_SEQ == 1
         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
-#endif
         setup_coherent_ht_domain(); // routing table and start other core0
 
         wait_all_core0_started();
diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c
index 7957f95ab5..2ff8fd752c 100644
--- a/src/mainboard/tyan/s2912/romstage.c
+++ b/src/mainboard/tyan/s2912/romstage.c
@@ -135,9 +135,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 
-#if CONFIG_MEM_TRAIN_SEQ == 1
 	set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
-#endif
 	setup_coherent_ht_domain(); // routing table and start other core0
 
 	wait_all_core0_started();