diff options
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/Kconfig | 8 | ||||
| -rw-r--r-- | src/mainboard/traverse/Kconfig | 7 | ||||
| -rw-r--r-- | src/mainboard/traverse/geos/Kconfig | 37 | ||||
| -rw-r--r-- | src/mainboard/traverse/geos/chip.h | 25 | ||||
| -rw-r--r-- | src/mainboard/traverse/geos/cmos.layout | 75 | ||||
| -rw-r--r-- | src/mainboard/traverse/geos/devicetree.cb | 40 | ||||
| -rw-r--r-- | src/mainboard/traverse/geos/irq_tables.c | 71 | ||||
| -rw-r--r-- | src/mainboard/traverse/geos/mainboard.c | 38 | ||||
| -rw-r--r-- | src/mainboard/traverse/geos/romstage.c | 100 |
9 files changed, 401 insertions, 0 deletions
diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index facfde9252..e73e8bc6b9 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -96,6 +96,8 @@ config VENDOR_TELEVIDEO bool "TeleVideo" config VENDOR_THOMSON bool "Thomson" +config VENDOR_TRAVERSE + bool "Traverse Technologies" config VENDOR_TYAN bool "Tyan" config VENDOR_VIA @@ -359,6 +361,11 @@ config MAINBOARD_VENDOR config MAINBOARD_VENDOR string + default "Traverse Technologies" + depends on VENDOR_TRAVERSE + +config MAINBOARD_VENDOR + string default "Tyan" depends on VENDOR_TYAN @@ -438,6 +445,7 @@ source "src/mainboard/technexion/Kconfig" source "src/mainboard/technologic/Kconfig" source "src/mainboard/televideo/Kconfig" source "src/mainboard/thomson/Kconfig" +source "src/mainboard/traverse/Kconfig" source "src/mainboard/tyan/Kconfig" source "src/mainboard/via/Kconfig" source "src/mainboard/winent/Kconfig" diff --git a/src/mainboard/traverse/Kconfig b/src/mainboard/traverse/Kconfig new file mode 100644 index 0000000000..692af42baf --- /dev/null +++ b/src/mainboard/traverse/Kconfig @@ -0,0 +1,7 @@ +choice + prompt "Mainboard model" + depends on VENDOR_TRAVERSE + +source "src/mainboard/traverse/geos/Kconfig" + +endchoice diff --git a/src/mainboard/traverse/geos/Kconfig b/src/mainboard/traverse/geos/Kconfig new file mode 100644 index 0000000000..4f3b2c6a74 --- /dev/null +++ b/src/mainboard/traverse/geos/Kconfig @@ -0,0 +1,37 @@ +config BOARD_TRAVERSE_GEOS + bool "Geos" + select ARCH_X86 + select CPU_AMD_LX + select NORTHBRIDGE_AMD_LX + select SOUTHBRIDGE_AMD_CS5536 + select HAVE_PIRQ_TABLE + select PIRQ_ROUTE + select UDELAY_TSC + select USE_DCACHE_RAM + select USE_PRINTK_IN_CAR + select BOARD_ROMSIZE_KB_1024 + +config MAINBOARD_DIR + string + default traverse/geos + depends on BOARD_TRAVERSE_GEOS + +config MAINBOARD_PART_NUMBER + string + default "Geos" + depends on BOARD_TRAVERSE_GEOS + +config HAVE_OPTION_TABLE + bool + default n + depends on BOARD_TRAVERSE_GEOS + +config IRQ_SLOT_COUNT + int + default 6 + depends on BOARD_TRAVERSE_GEOS + +config RAMBASE + hex + default 0x4000 + depends on BOARD_TRAVERSE_GEOS diff --git a/src/mainboard/traverse/geos/chip.h b/src/mainboard/traverse/geos/chip.h new file mode 100644 index 0000000000..fb8c6abe4b --- /dev/null +++ b/src/mainboard/traverse/geos/chip.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config { + int nothing; +}; diff --git a/src/mainboard/traverse/geos/cmos.layout b/src/mainboard/traverse/geos/cmos.layout new file mode 100644 index 0000000000..864d89ad2a --- /dev/null +++ b/src/mainboard/traverse/geos/cmos.layout @@ -0,0 +1,75 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 1 e 0 dcon_present +1008 16 h 0 check_sum + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM + +checksums + +checksum 392 1007 1008 + + diff --git a/src/mainboard/traverse/geos/devicetree.cb b/src/mainboard/traverse/geos/devicetree.cb new file mode 100644 index 0000000000..eab70c7c78 --- /dev/null +++ b/src/mainboard/traverse/geos/devicetree.cb @@ -0,0 +1,40 @@ +chip northbridge/amd/lx + device pci_domain 0 on + device pci 1.0 on end # Northbridge + device pci 1.1 on end # Graphics + chip southbridge/amd/cs5536 + # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK + # SIRQ Mode = Active(Quiet) mode. Save power.... + # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK + register "lpc_serirq_enable" = "0x00001002" + register "lpc_serirq_polarity" = "0x0000EFFD" + register "lpc_serirq_mode" = "1" + register "enable_gpio_int_route" = "0x0D0C0700" + register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash + register "enable_USBP4_device" = "0" #0: host, 1:device + register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) + register "com1_enable" = "1" + register "com1_address" = "0x3F8" + register "com1_irq" = "4" + register "com2_enable" = "0" + register "com2_address" = "0x2F8" + register "com2_irq" = "3" + register "unwanted_vpci[0]" = "0" # End of list has a zero + device pci a.0 on end # Ethernet 0 + device pci b.0 on end # Ethernet 1 + device pci c.0 on end # Xilinx + device pci d.0 on end # Mini PCI + device pci f.0 on end # ISA Bridge + device pci f.2 on end # IDE Controller + device pci f.3 on end # Audio + device pci f.4 on end # OHCI + device pci f.5 on end # EHCI + end + end + # APIC cluster is late CPU init. + device lapic_cluster 0 on + chip cpu/amd/model_lx + device lapic 0 on end + end + end +end diff --git a/src/mainboard/traverse/geos/irq_tables.c b/src/mainboard/traverse/geos/irq_tables.c new file mode 100644 index 0000000000..21c2b5db0f --- /dev/null +++ b/src/mainboard/traverse/geos/irq_tables.c @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> +#include <console/console.h> +#include <arch/io.h> +#include <arch/pirq_routing.h> +#include "../../../southbridge/amd/cs5536/cs5536.h" + +/* Platform IRQs */ +#define PIRQA 11 +#define PIRQB 10 +#define PIRQC 11 +#define PIRQD 9 + +/* Map */ +#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */ +#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */ +#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */ +#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */ + +/* Link */ +#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */ +#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */ +#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */ +#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */ + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ + 0x00, /* Where the interrupt router lies (bus) */ + (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ + 0x00, /* IRQs devoted exclusively to PCI usage */ + 0x100B, /* Vendor */ + 0x002B, /* Device */ + 0, /* Crap (miniport) */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ + 0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + { + /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */ + {0x00, (0x0A << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* eth0 */ + {0x00, (0x0B << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* eth1 */ + {0x00, (0x0C << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x2, 0x0}, /* xilinx */ + {0x00, (0x0D << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}}, 0x1, 0x0}, /* mini PCI */ + {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} diff --git a/src/mainboard/traverse/geos/mainboard.c b/src/mainboard/traverse/geos/mainboard.c new file mode 100644 index 0000000000..b578959171 --- /dev/null +++ b/src/mainboard/traverse/geos/mainboard.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include "chip.h" + +static void init(struct device *dev) +{ + printk(BIOS_DEBUG, "Geos ENTER %s\n", __func__); + printk(BIOS_DEBUG, "Geos EXIT %s\n", __func__); +} + +static void enable_dev(struct device *dev) +{ + dev->ops->init = init; +} + +struct chip_operations mainboard_ops = { + CHIP_NAME("Traverse Technologies Geos Mainboard") + .enable_dev = enable_dev, +}; diff --git a/src/mainboard/traverse/geos/romstage.c b/src/mainboard/traverse/geos/romstage.c new file mode 100644 index 0000000000..40501a95e0 --- /dev/null +++ b/src/mainboard/traverse/geos/romstage.c @@ -0,0 +1,100 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/hlt.h> +#include <console/console.h> +#include "lib/ramtest.c" +#include "cpu/x86/bist.h" +#include "cpu/x86/msr.h" +#include <cpu/amd/lxdef.h> +#include <cpu/amd/geode_post_code.h> +#include "southbridge/amd/cs5536/cs5536.h" + +#include "southbridge/amd/cs5536/cs5536_early_smbus.c" +#include "southbridge/amd/cs5536/cs5536_early_setup.c" + +static inline int spd_read_byte(unsigned int device, unsigned int address) +{ + return smbus_read_byte(device, address); +} + +#define ManualConf 1 /* Do automatic strapped PLL config */ +#define PLLMSRhi 0x0000059C /* manual settings for the PLL */ +#define PLLMSRlo 0x00DE602E +#define DIMM0 0xA0 +#define DIMM1 0xA2 + +#include "northbridge/amd/lx/raminit.h" +#include "northbridge/amd/lx/pll_reset.c" +#include "northbridge/amd/lx/raminit.c" +#include "lib/generic_sdram.c" +#include "cpu/amd/model_lx/cpureginit.c" +#include "cpu/amd/model_lx/syspreinit.c" +#include "cpu/amd/model_lx/msrinit.c" + +static void mb_gpio_init(void) +{ + /* Early mainboard specific GPIO setup. */ +} + +void main(unsigned long bist) +{ + post_code(0x01); + + static const struct mem_controller memctrl[] = { + {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}} + }; + + SystemPreInit(); + msr_init(); + + cs5536_early_setup(); + + /* Note: must do this AFTER the early_setup! It is counting on some + * early MSR setup for CS5536. + */ + /* cs5536_disable_internal_uart: disable them for now, set them + * up later... + */ + /* If debug. real setup done in chipset init via Config.lb. */ + cs5536_setup_onchipuart(1); + mb_gpio_init(); + uart_init(); + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + pll_reset(ManualConf); + + cpuRegInit(); + + sdram_initialize(1, memctrl); + + /* Check memory. */ + /* ram_check(0x00000000, 640 * 1024); */ + + /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */ + return; +} |