summaryrefslogtreecommitdiff
path: root/src/mainboard
diff options
context:
space:
mode:
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c2
-rw-r--r--src/mainboard/broadcom/blast/cache_as_ram_auto.c3
-rw-r--r--src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c2
-rw-r--r--src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c2
-rw-r--r--src/mainboard/hp/dl145_g3/cache_as_ram_auto.c1
-rw-r--r--src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c2
-rw-r--r--src/mainboard/iwill/dk8s2/cache_as_ram_auto.c2
-rw-r--r--src/mainboard/iwill/dk8x/cache_as_ram_auto.c2
-rw-r--r--src/mainboard/msi/ms7260/cache_as_ram_auto.c1
-rw-r--r--src/mainboard/msi/ms9185/cache_as_ram_auto.c2
-rw-r--r--src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c2
-rw-r--r--src/mainboard/sunw/ultra40/cache_as_ram_auto.c2
-rw-r--r--src/mainboard/supermicro/h8dme/cache_as_ram_auto.c1
-rw-r--r--src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c2
-rw-r--r--src/mainboard/tyan/s2895/cache_as_ram_auto.c1
-rw-r--r--src/mainboard/tyan/s2912/cache_as_ram_auto.c2
16 files changed, 0 insertions, 29 deletions
diff --git a/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c b/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c
index b39ae1ed34..a3e2b164a5 100644
--- a/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c
+++ b/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c
@@ -10,10 +10,8 @@
#define QRANK_DIMM_SUPPORT 1
//used by incoherent_ht
-//#define K8_SCAN_PCI_BUS 1
//#define K8_ALLOCATE_IO_RANGE 1
-
//used by init_cpus and fidvid
#define K8_SET_FIDVID 0
//if we want to wait for core1 done before DQS training, set it to 0
diff --git a/src/mainboard/broadcom/blast/cache_as_ram_auto.c b/src/mainboard/broadcom/blast/cache_as_ram_auto.c
index 5ac6f4be9f..3b94d3fd32 100644
--- a/src/mainboard/broadcom/blast/cache_as_ram_auto.c
+++ b/src/mainboard/broadcom/blast/cache_as_ram_auto.c
@@ -1,9 +1,6 @@
#define ASSEMBLY 1
#define __ROMCC__
-
-//#define K8_SCAN_PCI_BUS 1
-
#define QRANK_DIMM_SUPPORT 1
#if CONFIG_LOGICAL_CPUS==1
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c b/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c
index e81dc4c210..056cd08331 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c
@@ -27,8 +27,6 @@
#define RAMINIT_SYSINFO 1
#define K8_ALLOCATE_IO_RANGE 1
-//#define K8_SCAN_PCI_BUS 1
-
#define QRANK_DIMM_SUPPORT 1
diff --git a/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c b/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c
index 812878892a..26e5ee985e 100644
--- a/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c
+++ b/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c
@@ -25,8 +25,6 @@
#define RAMINIT_SYSINFO 1
#define K8_ALLOCATE_IO_RANGE 1
-//#define K8_SCAN_PCI_BUS 1
-
#define QRANK_DIMM_SUPPORT 1
diff --git a/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c b/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c
index f786d9fdec..0f54f46af2 100644
--- a/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c
+++ b/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c
@@ -31,7 +31,6 @@
#define RAMINIT_SYSINFO 1
#define K8_ALLOCATE_IO_RANGE 1
-//#define K8_SCAN_PCI_BUS 1
#define QRANK_DIMM_SUPPORT 1
diff --git a/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c b/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c
index f4213c1ec3..76e56f80a4 100644
--- a/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c
+++ b/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c
@@ -10,10 +10,8 @@
#define QRANK_DIMM_SUPPORT 1
//used by incoherent_ht
-//#define K8_SCAN_PCI_BUS 1
//#define K8_ALLOCATE_IO_RANGE 1
-
//used by init_cpus and fidvid
#define K8_SET_FIDVID 0
//if we want to wait for core1 done before DQS training, set it to 0
diff --git a/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c b/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c
index e702d0e5fa..78b1de980d 100644
--- a/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c
+++ b/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c
@@ -10,10 +10,8 @@
#define QRANK_DIMM_SUPPORT 1
//used by incoherent_ht
-//#define K8_SCAN_PCI_BUS 1
//#define K8_ALLOCATE_IO_RANGE 1
-
//used by init_cpus and fidvid
#define K8_SET_FIDVID 0
//if we want to wait for core1 done before DQS training, set it to 0
diff --git a/src/mainboard/iwill/dk8x/cache_as_ram_auto.c b/src/mainboard/iwill/dk8x/cache_as_ram_auto.c
index e702d0e5fa..78b1de980d 100644
--- a/src/mainboard/iwill/dk8x/cache_as_ram_auto.c
+++ b/src/mainboard/iwill/dk8x/cache_as_ram_auto.c
@@ -10,10 +10,8 @@
#define QRANK_DIMM_SUPPORT 1
//used by incoherent_ht
-//#define K8_SCAN_PCI_BUS 1
//#define K8_ALLOCATE_IO_RANGE 1
-
//used by init_cpus and fidvid
#define K8_SET_FIDVID 0
//if we want to wait for core1 done before DQS training, set it to 0
diff --git a/src/mainboard/msi/ms7260/cache_as_ram_auto.c b/src/mainboard/msi/ms7260/cache_as_ram_auto.c
index 6458a65bde..ed84a426b2 100644
--- a/src/mainboard/msi/ms7260/cache_as_ram_auto.c
+++ b/src/mainboard/msi/ms7260/cache_as_ram_auto.c
@@ -31,7 +31,6 @@
#define RAMINIT_SYSINFO 1
#define K8_ALLOCATE_IO_RANGE 1
-// #define K8_SCAN_PCI_BUS 1 /* ? */
#define QRANK_DIMM_SUPPORT 1
#if CONFIG_LOGICAL_CPUS == 1
#define SET_NB_CFG_54 1
diff --git a/src/mainboard/msi/ms9185/cache_as_ram_auto.c b/src/mainboard/msi/ms9185/cache_as_ram_auto.c
index b95d55a91a..95704b9791 100644
--- a/src/mainboard/msi/ms9185/cache_as_ram_auto.c
+++ b/src/mainboard/msi/ms9185/cache_as_ram_auto.c
@@ -35,10 +35,8 @@
#define QRANK_DIMM_SUPPORT 1
//used by incoherent_ht
-//#define K8_SCAN_PCI_BUS 1
//#define K8_ALLOCATE_IO_RANGE 1
-
//used by init_cpus and fidvid
#define K8_SET_FIDVID 1
//if we want to wait for core1 done before DQS training, set it to 0
diff --git a/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c b/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c
index 9962aefec6..04fa546f6a 100644
--- a/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c
+++ b/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c
@@ -25,8 +25,6 @@
#define RAMINIT_SYSINFO 1
#define K8_ALLOCATE_IO_RANGE 1
-//#define K8_SCAN_PCI_BUS 1
-
#define QRANK_DIMM_SUPPORT 1
diff --git a/src/mainboard/sunw/ultra40/cache_as_ram_auto.c b/src/mainboard/sunw/ultra40/cache_as_ram_auto.c
index 18af542809..468e049750 100644
--- a/src/mainboard/sunw/ultra40/cache_as_ram_auto.c
+++ b/src/mainboard/sunw/ultra40/cache_as_ram_auto.c
@@ -3,8 +3,6 @@
#define K8_ALLOCATE_IO_RANGE 1
-//#define K8_SCAN_PCI_BUS 1
-
#define QRANK_DIMM_SUPPORT 1
diff --git a/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c b/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c
index 18435a61f2..151b2d0a4a 100644
--- a/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c
+++ b/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c
@@ -22,7 +22,6 @@
#define RAMINIT_SYSINFO 1
#define K8_ALLOCATE_IO_RANGE 1
-// #define K8_SCAN_PCI_BUS 1
#define QRANK_DIMM_SUPPORT 1
diff --git a/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c b/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c
index 3a9b0ca375..672f551fa1 100644
--- a/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c
+++ b/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c
@@ -25,8 +25,6 @@
#define RAMINIT_SYSINFO 1
#define K8_ALLOCATE_IO_RANGE 1
-//#define K8_SCAN_PCI_BUS 1
-
#define QRANK_DIMM_SUPPORT 1
diff --git a/src/mainboard/tyan/s2895/cache_as_ram_auto.c b/src/mainboard/tyan/s2895/cache_as_ram_auto.c
index 0e144eb29c..77bd04d330 100644
--- a/src/mainboard/tyan/s2895/cache_as_ram_auto.c
+++ b/src/mainboard/tyan/s2895/cache_as_ram_auto.c
@@ -2,7 +2,6 @@
#define __ROMCC__
#define K8_ALLOCATE_IO_RANGE 1
-//#define K8_SCAN_PCI_BUS 1
#define QRANK_DIMM_SUPPORT 1
diff --git a/src/mainboard/tyan/s2912/cache_as_ram_auto.c b/src/mainboard/tyan/s2912/cache_as_ram_auto.c
index c27e74b2c1..8fb6473499 100644
--- a/src/mainboard/tyan/s2912/cache_as_ram_auto.c
+++ b/src/mainboard/tyan/s2912/cache_as_ram_auto.c
@@ -25,8 +25,6 @@
#define RAMINIT_SYSINFO 1
#define K8_ALLOCATE_IO_RANGE 1
-//#define K8_SCAN_PCI_BUS 1
-
#define QRANK_DIMM_SUPPORT 1
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 18:46:25 +0000