diff options
Diffstat (limited to 'src/mainboard')
24 files changed, 30 insertions, 263 deletions
diff --git a/src/mainboard/amd/dinar/Makefile.inc b/src/mainboard/amd/dinar/Makefile.inc index 8dfe21d499..4e7323ad00 100644 --- a/src/mainboard/amd/dinar/Makefile.inc +++ b/src/mainboard/amd/dinar/Makefile.inc @@ -18,13 +18,11 @@ # romstage-y += buildOpts.c -romstage-y += agesawrapper.c romstage-y += BiosCallOuts.c romstage-y += sb700_cfg.c romstage-y += rd890_cfg.c ramstage-y += buildOpts.c -ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c ramstage-y += sb700_cfg.c ramstage-y += rd890_cfg.c diff --git a/src/mainboard/amd/dinar/agesawrapper.c b/src/mainboard/amd/dinar/agesawrapper.c deleted file mode 100644 index 9454e17bef..0000000000 --- a/src/mainboard/amd/dinar/agesawrapper.c +++ /dev/null @@ -1,231 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdint.h> -#include <string.h> -#include <cpu/x86/mtrr.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/BiosCallOuts.h> -#include "cpuRegisters.h" -#include "cpuCacheInit.h" -#include "cpuApicUtilities.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "Dispatcher.h" -#include "cpuCacheInit.h" -#include "amdlib.h" -#include "heapManager.h" -#include "Filecode.h" -#include <arch/io.h> - -#include <southbridge/amd/cimx/sb700/gpio_oem.h> - -#define FILECODE UNASSIGNED_FILE_FILECODE - -/*Get the Bus Number from CONFIG_MMCONF_BUS_NUMBER, Please reference AMD BIOS BKDG docuemt about it*/ -/* -BusRange: bus range identifier. Read-write. Reset: X. This specifies the number of buses in the -MMIO configuration space range. The size of the MMIO configuration space range varies with this -field as follows: the size is 1 Mbyte times the number of buses. This field is encoded as follows: -Bits Buses Bits Buses -0h 1 5h 32 -1h 2 6h 64 -2h 4 7h 128 -3h 8 8h 256 -4h 16 Fh-9h Reserved -*/ -STATIC UINT8 GetEndBusNum(VOID) -{ - UINT64 BusNum; - UINT8 Index; - for (Index = 1; Index <= 8; Index++) { - BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index; - if (BusNum == 1) { - break; - } - } - return Index; -} - -AGESA_STATUS agesawrapper_amdinitcpuio(void) -{ - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; - UINT32 TopMem; - UINT32 nodes; - UINT32 node; - UINT32 SbLink; - UINT32 i; - - /* get the number of coherent nodes in the system */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 0, 0x60); - LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader); - nodes = ((PciData >> 4) & 7) + 1; //nodes[6:4] - /* Find out the Link ID of Node0 that connects to the - * Southbridge (system IO hub). e.g. family10 MCM Processor, - * SbLink is Processor0 Link2, internal Node0 Link3 - */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 0, 0x64); - LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader); - SbLink = (PciData >> 8) & 3; //assume ganged - /* Enable MMIO on AMD CPU Address Map Controller for all nodes */ - for (node = 0; node < nodes; node++) { - /* clear all MMIO Mapped Base/Limit Registers */ - for (i = 0; i < 8; i++) { - PciData = 0x00000000; - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x80 + i * 8); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x84 + i * 8); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - } - /* clear all IO Space Base/Limit Registers */ - for (i = 0; i < 4; i++) { - PciData = 0x00000000; - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0 + i * 8); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4 + i * 8); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - } - - /* Enable MMIO on AMD CPU Address Map Controller */ - - /* Set VGA Ram MMIO 0000A0000-0000BFFFF to Node0 sbLink */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x80); - PciData = (0xA0000 >> 8) | 3; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x84); - PciData = 0xB0000 >> 8; - PciData &= (~0xFF); - PciData |= SbLink << 4; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Set UMA MMIO. */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x88); - LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader); - TopMem = (UINT32) MsrReg; - MsrReg = (MsrReg >> 8) | 3; - PciData = (UINT32) MsrReg; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x8c); - if (TopMem <= CONFIG_MMCONF_BASE_ADDRESS) { - PciData = (CONFIG_MMCONF_BASE_ADDRESS - 1) >> 8; - } else { - PciData = (0x100000000ull - 1) >> 8; - } - PciData &= (~0xFF); - PciData |= SbLink << 4; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Set PCIE MMIO. */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x90); - PciData = (CONFIG_MMCONF_BASE_ADDRESS >> 8) | 3; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x94); - PciData = ((CONFIG_MMCONF_BASE_ADDRESS + CONFIG_MMCONF_BUS_NUMBER * 4096 * 256 - 1) >> 8) & (~0xFF); - PciData &= (~0xFF); - PciData |= MMIO_NP_BIT; - PciData |= SbLink << 4; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Set XAPIC MMIO. 24K */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x98); - PciData = (0xFEC00000 >> 8) | 3; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x9c); - PciData = ((0xFEC00000 + 6 * 4096 - 1) >> 8); - PciData &= (~0xFF); - PciData |= MMIO_NP_BIT; - PciData |= SbLink << 4; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Set Local APIC MMIO. 4K*4= 16K, Llano CPU are 4 cores */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xA0); - PciData = (0xFEE00000 >> 8) | 3; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xA8); - PciData = (0xFEE00000 + 4 * 4096 - 1) >> 8; - PciData &= (~0xFF); - PciData |= MMIO_NP_BIT; - PciData |= SbLink << 4; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Set PCIO: 0x0 - 0xFFF000 and enabled VGA IO */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0); - PciData = 0x13; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4); - PciData = 0x00FFF000; - PciData &= (~0x7F); - PciData |= SbLink << 4; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - } - Status = AGESA_SUCCESS; - return Status; -} - -AGESA_STATUS agesawrapper_amdinitmmio(void) -{ - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; - - /* - Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base - Address MSR register. - */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (GetEndBusNum() << 2) | 1; - LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader); - - /* - Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. - */ - LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader); - MsrReg = MsrReg | BIT46; - LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader); - - /* Set PCIE MMIO. */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x90); - PciData = (CONFIG_MMCONF_BASE_ADDRESS >> 8) | 3; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x94); - PciData = ((CONFIG_MMCONF_BASE_ADDRESS + CONFIG_MMCONF_BUS_NUMBER * 4096 * 256 - 1) >> 8) | MMIO_NP_BIT; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Enable memory access */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0x04); - LibAmdPciRead(AccessWidth8, PciAddress, &PciData, &StdHeader); - PciData |= BIT1; - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0x04); - LibAmdPciWrite(AccessWidth8, PciAddress, &PciData, &StdHeader); - - /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000 - CACHE_ROM_SIZE) | 5; - LibAmdMsrWrite(0x20E, &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; - LibAmdMsrWrite(0x20F, &MsrReg, &StdHeader); - - Status = AGESA_SUCCESS; - return Status; -} diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index c011038c7e..ad6bce358d 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -43,7 +43,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - agesawrapper_amdinitmmio(); + amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c index 68822e0d33..6a13d03402 100644 --- a/src/mainboard/amd/inagua/romstage.c +++ b/src/mainboard/amd/inagua/romstage.c @@ -54,7 +54,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ __writemsr (0xc0010062, 0); - agesawrapper_amdinitmmio(); + amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c index abab68844a..82dcd602de 100644 --- a/src/mainboard/amd/olivehill/romstage.c +++ b/src/mainboard/amd/olivehill/romstage.c @@ -50,7 +50,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) outb(0xD2, 0xcd6); outb(0x00, 0xcd7); - agesawrapper_amdinitmmio(); + amd_initmmio(); /* Set LPC decode enables. */ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); @@ -101,7 +101,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x60); agesawrapper_amdinitresume(); - agesawrapper_amdinitcpuio(); + amd_initcpuio(); agesawrapper_amds3laterestore(); post_code(0x61); diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index 9a55e8060b..e38d715c8b 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -42,7 +42,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - agesawrapper_amdinitmmio(); + amd_initmmio(); /* Set LPC decode enables. */ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); @@ -84,7 +84,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x60); agesawrapper_amdinitresume(); - agesawrapper_amdinitcpuio(); + amd_initcpuio(); agesawrapper_amds3laterestore(); post_code(0x61); diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index b0c1624780..17da39c9d2 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -60,7 +60,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); - agesawrapper_amdinitmmio(); + amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c index 727b92d7aa..53a1dce371 100644 --- a/src/mainboard/amd/south_station/romstage.c +++ b/src/mainboard/amd/south_station/romstage.c @@ -55,7 +55,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); - agesawrapper_amdinitmmio(); + amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 193454542c..319cd3a8bd 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -47,7 +47,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u8 byte; pci_devfn_t dev; - agesawrapper_amdinitmmio(); + amd_initmmio(); /* Set LPC decode enables. */ dev = PCI_DEV(0, 0x14, 3); @@ -98,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x60); agesawrapper_amdinitresume(); - agesawrapper_amdinitcpuio(); + amd_initcpuio(); agesawrapper_amds3laterestore(); post_code(0x61); diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c index f2bcccc519..e3f41a070b 100644 --- a/src/mainboard/amd/torpedo/romstage.c +++ b/src/mainboard/amd/torpedo/romstage.c @@ -44,7 +44,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 val; post_code(0x35); - agesawrapper_amdinitmmio(); + amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c index 4d31d2baf1..022b43237a 100644 --- a/src/mainboard/amd/union_station/romstage.c +++ b/src/mainboard/amd/union_station/romstage.c @@ -50,7 +50,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) __writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5); __writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800); - agesawrapper_amdinitmmio(); + amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index ea59a8d805..911e821664 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -55,7 +55,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr(0xc0010062, 0); - agesawrapper_amdinitmmio(); + amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c index 3d1458bed1..1ba1104eb0 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/romstage.c @@ -55,7 +55,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) //outb(0xD2, 0xcd6); //outb(0x00, 0xcd7); - agesawrapper_amdinitmmio(); + amd_initmmio(); /* Set LPC decode enables. */ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); @@ -125,7 +125,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x60); agesawrapper_amdinitresume(); - agesawrapper_amdinitcpuio(); + amd_initcpuio(); agesawrapper_amds3laterestore(); post_code(0x61); diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index fbc89a7fa2..95298d1a14 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -75,7 +75,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) hudson_lpc_port80(); #endif - agesawrapper_amdinitmmio(); + amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { @@ -143,7 +143,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x60); agesawrapper_amdinitresume(); - agesawrapper_amdinitcpuio(); + amd_initcpuio(); agesawrapper_amds3laterestore(); post_code(0x61); diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c index 5132eef39c..50cc12c502 100644 --- a/src/mainboard/gizmosphere/gizmo/romstage.c +++ b/src/mainboard/gizmosphere/gizmo/romstage.c @@ -68,7 +68,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) msr.hi = 0; wrmsr (MSR_PSTATE_CONTROL, msr); - agesawrapper_amdinitmmio(); + amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); diff --git a/src/mainboard/gizmosphere/gizmo2/romstage.c b/src/mainboard/gizmosphere/gizmo2/romstage.c index abab68844a..82dcd602de 100644 --- a/src/mainboard/gizmosphere/gizmo2/romstage.c +++ b/src/mainboard/gizmosphere/gizmo2/romstage.c @@ -50,7 +50,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) outb(0xD2, 0xcd6); outb(0x00, 0xcd7); - agesawrapper_amdinitmmio(); + amd_initmmio(); /* Set LPC decode enables. */ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); @@ -101,7 +101,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x60); agesawrapper_amdinitresume(); - agesawrapper_amdinitcpuio(); + amd_initcpuio(); agesawrapper_amds3laterestore(); post_code(0x61); diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c index d142a9d754..bc92e6d7d3 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c @@ -38,7 +38,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - agesawrapper_amdinitmmio(); + amd_initmmio(); hudson_lpc_port80(); @@ -76,7 +76,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x60); agesawrapper_amdinitresume(); - agesawrapper_amdinitcpuio(); + amd_initcpuio(); agesawrapper_amds3laterestore(); post_code(0x61); diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index d7fa6bcfcb..e2f43d903d 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -76,7 +76,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); - agesawrapper_amdinitmmio(); + amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); diff --git a/src/mainboard/lenovo/g505s/romstage.c b/src/mainboard/lenovo/g505s/romstage.c index d142a9d754..bc92e6d7d3 100644 --- a/src/mainboard/lenovo/g505s/romstage.c +++ b/src/mainboard/lenovo/g505s/romstage.c @@ -38,7 +38,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - agesawrapper_amdinitmmio(); + amd_initmmio(); hudson_lpc_port80(); @@ -76,7 +76,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x60); agesawrapper_amdinitresume(); - agesawrapper_amdinitcpuio(); + amd_initcpuio(); agesawrapper_amds3laterestore(); post_code(0x61); diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c index 52da850276..c25e1ee2c1 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/romstage.c @@ -59,7 +59,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); - agesawrapper_amdinitmmio(); + amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index 13d6f66c40..c5212d7cee 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -60,7 +60,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); - agesawrapper_amdinitmmio(); + amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c index 9c48601f6a..477f1c43c2 100644 --- a/src/mainboard/supermicro/h8qgi/romstage.c +++ b/src/mainboard/supermicro/h8qgi/romstage.c @@ -45,7 +45,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 val; post_code(0x30); - agesawrapper_amdinitmmio(); + amd_initmmio(); post_code(0x31); /* Halt if there was a built in self test failure */ diff --git a/src/mainboard/supermicro/h8scm/romstage.c b/src/mainboard/supermicro/h8scm/romstage.c index 2f4c828db5..6e7ad70a86 100644 --- a/src/mainboard/supermicro/h8scm/romstage.c +++ b/src/mainboard/supermicro/h8scm/romstage.c @@ -44,7 +44,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 val; post_code(0x30); - agesawrapper_amdinitmmio(); + amd_initmmio(); post_code(0x31); /* Halt if there was a built in self test failure */ diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c index 8587ed1797..ac28874a30 100644 --- a/src/mainboard/tyan/s8226/romstage.c +++ b/src/mainboard/tyan/s8226/romstage.c @@ -43,7 +43,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 val; post_code(0x30); - agesawrapper_amdinitmmio(); + amd_initmmio(); post_code(0x31); /* For serial port. */ |