4 files changed, 59 insertions, 0 deletions
diff --git a/src/mainboard/google/reef/acpi/ec.asl b/src/mainboard/google/reef/acpi/ec.asl
new file mode 100644
index 0000000000..fe53cb5559
--- /dev/null
+++ b/src/mainboard/google/reef/acpi/ec.asl
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* mainboard configuration */
+#include "../ec.h"
+
+/* Enable EC backed ALS device in ACPI */
+#define EC_ENABLE_ALS_DEVICE
+
+/* Enable EC backed PD MCU device in ACPI */
+#define EC_ENABLE_PD_MCU_DEVICE
+
+/* ACPI code for EC functions */
+#include <ec/google/chromeec/acpi/ec.asl>
diff --git a/src/mainboard/google/reef/acpi/mainboard.asl b/src/mainboard/google/reef/acpi/mainboard.asl
index 05ea06add3..06b2efc9ac 100644
--- a/src/mainboard/google/reef/acpi/mainboard.asl
+++ b/src/mainboard/google/reef/acpi/mainboard.asl
@@ -14,3 +14,29 @@
  */
 
 #include "acpi/superio.asl"
+
+Scope (\_SB)
+{
+	Device (LID0)
+	{
+		Name (_HID, EisaId ("PNP0C0D"))
+		Method (_LID, 0)
+		{
+			Return (\_SB.PCI0.LPCB.EC0.LIDS)
+		}
+	}
+
+	Device (PWRB)
+	{
+		Name (_HID, EisaId ("PNP0C0C"))
+	}
+}
+
+/*
+ * LPC Trusted Platform Module
+ */
+Scope (\_SB.PCI0.LPCB)
+{
+	#include <drivers/pc80/tpm/acpi/tpm.asl>
+	#include "ec.asl"
+}
diff --git a/src/mainboard/google/reef/dsdt.asl b/src/mainboard/google/reef/dsdt.asl
index 41bb523f85..8aa42598ba 100644
--- a/src/mainboard/google/reef/dsdt.asl
+++ b/src/mainboard/google/reef/dsdt.asl
@@ -25,6 +25,9 @@ DefinitionBlock(
 	/* global NVS and variables */
 	#include <soc/intel/skylake/acpi/globalnvs.asl>
 
+	/* CPU */
+	#include <soc/intel/apollolake/acpi/cpu.asl>
+
 	Scope (\_SB) {
 		Device (PCI0)
 		{
diff --git a/src/mainboard/google/reef/ec.h b/src/mainboard/google/reef/ec.h
index 51d4028aa5..5a32697d2e 100644
--- a/src/mainboard/google/reef/ec.h
+++ b/src/mainboard/google/reef/ec.h
@@ -18,6 +18,10 @@
 
 #include <ec/google/chromeec/ec_commands.h>
 
+/* This is the GPE status bit.
+   TODO: Fix this to proper bit matching GPE routing table */
+#define EC_SCI_GPI   15
+
 #define MAINBOARD_EC_SCI_EVENTS \
 	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)        |\
 	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)          |\