diff options
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/gru/mainboard.c | 4 | ||||
| -rw-r--r-- | src/mainboard/google/kahlee/OemCustomize.c | 2 | ||||
| -rw-r--r-- | src/mainboard/google/kahlee/variants/baseboard/memory.c | 4 | ||||
| -rw-r--r-- | src/mainboard/google/octopus/romstage.c | 2 | ||||
| -rw-r--r-- | src/mainboard/intel/harcuvar/romstage.c | 2 | ||||
| -rw-r--r-- | src/mainboard/scaleway/tagada/romstage.c | 2 |
6 files changed, 8 insertions, 8 deletions
diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c index c177c15f33..53277715a2 100644 --- a/src/mainboard/google/gru/mainboard.c +++ b/src/mainboard/google/gru/mainboard.c @@ -247,12 +247,12 @@ static void configure_display(void) static void usb_power_cycle(int port) { if (google_chromeec_set_usb_pd_role(port, USB_PD_CTRL_ROLE_FORCE_SINK)) - printk(BIOS_ERR, "ERROR: Cannot force USB%d PD sink\n", port); + printk(BIOS_ERR, "Cannot force USB%d PD sink\n", port); mdelay(10); /* Make sure USB stick is fully depowered. */ if (google_chromeec_set_usb_pd_role(port, USB_PD_CTRL_ROLE_TOGGLE_ON)) - printk(BIOS_ERR, "ERROR: Cannot restore USB%d PD mode\n", port); + printk(BIOS_ERR, "Cannot restore USB%d PD mode\n", port); } static void setup_usb(int port) diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c index 9f37a460d8..5ccd1816a6 100644 --- a/src/mainboard/google/kahlee/OemCustomize.c +++ b/src/mainboard/google/kahlee/OemCustomize.c @@ -67,7 +67,7 @@ void set_board_env_params(GNB_ENV_CONFIGURATION *params) const struct soc_amd_stoneyridge_config *cfg; const struct device *dev = pcidev_path_on_root(GNB_DEVFN); if (!dev || !dev->chip_info) { - printk(BIOS_WARNING, "Warning: Cannot find SoC devicetree config\n"); + printk(BIOS_WARNING, "Cannot find SoC devicetree config\n"); return; } cfg = dev->chip_info; diff --git a/src/mainboard/google/kahlee/variants/baseboard/memory.c b/src/mainboard/google/kahlee/variants/baseboard/memory.c index 4b60a9cfc3..91101872f4 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/memory.c +++ b/src/mainboard/google/kahlee/variants/baseboard/memory.c @@ -29,12 +29,12 @@ int __weak variant_mainboard_read_spd(uint8_t spdAddress, void *spd = (void *)spd_cbfs_map(spd_index); if (!spd) { - printk(BIOS_ERR, "Error: spd.bin not found\n"); + printk(BIOS_ERR, "spd.bin not found\n"); return -1; } if (len != CONFIG_DIMM_SPD_SIZE) { - printk(BIOS_ERR, "Error: spd.bin is not the correct size\n"); + printk(BIOS_ERR, "spd.bin is not the correct size\n"); return -1; } diff --git a/src/mainboard/google/octopus/romstage.c b/src/mainboard/google/octopus/romstage.c index 8d83609fbf..47daba23dd 100644 --- a/src/mainboard/google/octopus/romstage.c +++ b/src/mainboard/google/octopus/romstage.c @@ -34,7 +34,7 @@ void mainboard_save_dimm_info(void) if (google_chromeec_cbi_get_dram_part_num(&part_num_store[0], ARRAY_SIZE(part_num_store)) < 0) - printk(BIOS_ERR, "ERROR: Couldn't obtain DRAM part number from CBI\n"); + printk(BIOS_ERR, "Couldn't obtain DRAM part number from CBI\n"); else part_num = &part_num_store[0]; diff --git a/src/mainboard/intel/harcuvar/romstage.c b/src/mainboard/intel/harcuvar/romstage.c index 027c56ef52..44551a2edf 100644 --- a/src/mainboard/intel/harcuvar/romstage.c +++ b/src/mainboard/intel/harcuvar/romstage.c @@ -88,7 +88,7 @@ void mainboard_config_gpios(void) } if ((!table) || (!num)) { - printk(BIOS_ERR, "ERROR: No valid GPIO table found!\n"); + printk(BIOS_ERR, "No valid GPIO table found!\n"); return; } diff --git a/src/mainboard/scaleway/tagada/romstage.c b/src/mainboard/scaleway/tagada/romstage.c index f041b6f7e2..e64356ef31 100644 --- a/src/mainboard/scaleway/tagada/romstage.c +++ b/src/mainboard/scaleway/tagada/romstage.c @@ -25,7 +25,7 @@ void mainboard_config_gpios(void) num = ARRAY_SIZE(tagada_gpio_config); if ((!table) || (!num)) { - printk(BIOS_ERR, "ERROR: No valid GPIO table found!\n"); + printk(BIOS_ERR, "No valid GPIO table found!\n"); return; } |