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-rw-r--r--src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb5
1 files changed, 1 insertions, 4 deletions
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
index 5d688fd421..ee2fe9a5f4 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
@@ -47,10 +47,7 @@ chip northbridge/intel/sandybridge
drq 0x22 = 0xd7 # Power down UART B and LPT
end
device pnp 2e.6 off end # CIR
- device pnp 2e.8 on # WDT1
- drq 0xe0 = 0x7f # GP07 output
- drq 0xe1 = 0x80 # GP07 high
- end
+ device pnp 2e.8 off end # WDT1
device pnp 2e.a on # ACPI
drq 0xe4 = 0x10 # Enable 3VSBSW#, needed for S3 suspend
drq 0xe7 = 0x11 # HWM reset by LRESET#, 0.5s S3 delay for compatibility