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-rw-r--r--src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb1
-rw-r--r--src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb1
-rw-r--r--src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb1
3 files changed, 0 insertions, 3 deletions
diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb
index 0fdc88a7a8..baf0ba12ee 100644
--- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb
+++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb
@@ -14,7 +14,6 @@ chip soc/intel/elkhartlake
# FSP configuration
register "SaGv" = "SaGv_Enabled"
- register "SmbusEnable" = "1"
register "Heci2Enable" = "1"
# Display related UPDs
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
index d7c3e22f3b..9bb8d8f328 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
@@ -14,7 +14,6 @@ chip soc/intel/elkhartlake
# FSP configuration
register "SaGv" = "SaGv_Disabled"
- register "SmbusEnable" = "1"
# Enable IBECC for the complete memory
register "ibecc" = "{
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
index f74b504e0d..72e4f60cd3 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
@@ -14,7 +14,6 @@ chip soc/intel/elkhartlake
# FSP configuration
register "SaGv" = "SaGv_Disabled"
- register "SmbusEnable" = "1"
# Enable IBECC for the complete memory
register "ibecc" = "{