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-rw-r--r--src/mainboard/hp/280_g2/Kconfig42
-rw-r--r--src/mainboard/hp/280_g2/Kconfig.name2
-rw-r--r--src/mainboard/hp/280_g2/Makefile.inc7
-rw-r--r--src/mainboard/hp/280_g2/acpi/ec.asl0
-rw-r--r--src/mainboard/hp/280_g2/acpi/superio.asl0
-rw-r--r--src/mainboard/hp/280_g2/board_info.txt8
-rw-r--r--src/mainboard/hp/280_g2/bootblock.c103
-rw-r--r--src/mainboard/hp/280_g2/data.vbtbin0 -> 6144 bytes
-rw-r--r--src/mainboard/hp/280_g2/devicetree.cb144
-rw-r--r--src/mainboard/hp/280_g2/dsdt.asl26
-rw-r--r--src/mainboard/hp/280_g2/gma-mainboard.ads16
-rw-r--r--src/mainboard/hp/280_g2/hda_verb.c25
-rw-r--r--src/mainboard/hp/280_g2/romstage.c52
13 files changed, 425 insertions, 0 deletions
diff --git a/src/mainboard/hp/280_g2/Kconfig b/src/mainboard/hp/280_g2/Kconfig
new file mode 100644
index 0000000000..10f6828ca7
--- /dev/null
+++ b/src/mainboard/hp/280_g2/Kconfig
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+if BOARD_HP_280_G2
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_8192
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select INTEL_GMA_HAVE_VBT
+ select INTEL_LPSS_UART_FOR_CONSOLE
+ select MAINBOARD_HAS_LIBGFXINIT
+ select SKYLAKE_SOC_PCH_H
+ select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+ select SOC_INTEL_KABYLAKE
+ select SPD_READ_BY_WORD
+ select SUPERIO_ITE_COMMON_PRE_RAM
+
+config MAINBOARD_DIR
+ string
+ default "hp/280_g2"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "280 G2"
+
+config DIMM_MAX
+ int
+ default 2
+
+config DIMM_SPD_SIZE
+ int
+ default 512
+
+config UART_FOR_CONSOLE
+ int
+ default 2
+
+config USE_LEGACY_8254_TIMER
+ default y
+
+endif
diff --git a/src/mainboard/hp/280_g2/Kconfig.name b/src/mainboard/hp/280_g2/Kconfig.name
new file mode 100644
index 0000000000..74ddaf4fd3
--- /dev/null
+++ b/src/mainboard/hp/280_g2/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_HP_280_G2
+ bool "280 G2"
diff --git a/src/mainboard/hp/280_g2/Makefile.inc b/src/mainboard/hp/280_g2/Makefile.inc
new file mode 100644
index 0000000000..3c2a7c49e3
--- /dev/null
+++ b/src/mainboard/hp/280_g2/Makefile.inc
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += bootblock.c
+
+ramstage-y += hda_verb.c
+
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/hp/280_g2/acpi/ec.asl b/src/mainboard/hp/280_g2/acpi/ec.asl
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/src/mainboard/hp/280_g2/acpi/ec.asl
diff --git a/src/mainboard/hp/280_g2/acpi/superio.asl b/src/mainboard/hp/280_g2/acpi/superio.asl
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/src/mainboard/hp/280_g2/acpi/superio.asl
diff --git a/src/mainboard/hp/280_g2/board_info.txt b/src/mainboard/hp/280_g2/board_info.txt
new file mode 100644
index 0000000000..b0e71e53a0
--- /dev/null
+++ b/src/mainboard/hp/280_g2/board_info.txt
@@ -0,0 +1,8 @@
+Vendor name: HP
+Board name: 280 G2
+Category: desktop
+Board URL: https://support.hp.com/us-en/document/c04955444
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/hp/280_g2/bootblock.c b/src/mainboard/hp/280_g2/bootblock.c
new file mode 100644
index 0000000000..f42c3f26f7
--- /dev/null
+++ b/src/mainboard/hp/280_g2/bootblock.c
@@ -0,0 +1,103 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <console/console.h>
+#include <device/pnp_ops.h>
+#include <gpio.h>
+#include <soc/gpio.h>
+#include <superio/ite/common/ite.h>
+#include <types.h>
+
+static const struct pad_config gpio_table[] = {
+ PAD_CFG_NF(GPP_B14, DN_20K, PLTRST, NF1), /* SPKR */
+ PAD_CFG_NF(GPP_C20, UP_20K, PLTRST, NF1), /* PCH_UART2_RXD */
+ PAD_CFG_NF(GPP_C21, UP_20K, PLTRST, NF1), /* PCH_UART2_TXD */
+ PAD_NC(GPP_C22, NONE),
+ PAD_CFG_GPI(GPP_C23, NONE, PLTRST), /* TODO: SIO PME# */
+ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), /* SATA_LED# */
+ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_OC_LAN# */
+ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB3.0_OC_BACK# */
+ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USB_OC_REAR2# */
+ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* USB_OC_FRONT1# */
+ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), /* USB_OC_FRONT2# */
+ PAD_CFG_GPI(GPP_G1, NONE, PLTRST), /* LPT_DET# */
+ PAD_CFG_GPO(GPP_G2, 0, PLTRST), /* AUD_AMP_ON# */
+ PAD_CFG_GPO(GPP_G3, 0, PLTRST), /* W_DISABLE2# */
+ PAD_CFG_GPI(GPP_G4, NONE, PLTRST), /* CLR_CMOS# */
+ PAD_CFG_GPI(GPP_G5, NONE, PLTRST), /* CLR_PSWD# */
+ PAD_CFG_GPI(GPP_G6, NONE, PLTRST), /* BOOT_BLOCK_EN# */
+ PAD_CFG_GPI(GPP_G9, NONE, PLTRST), /* HOOD_SW_DET# */
+ PAD_CFG_GPI(GPP_G12, NONE, PLTRST), /* FRONT_USB_DET1# */
+ PAD_CFG_GPI(GPP_G13, NONE, PLTRST), /* FRONT_USB_DET2# */
+ PAD_CFG_GPI(GPP_G14, NONE, PLTRST), /* FRONT_USB_DET3# */
+ PAD_CFG_GPI(GPP_G16, NONE, PLTRST), /* F_AUDIO_DET# */
+ PAD_CFG_GPI(GPP_G17, NONE, PLTRST), /* COMM_B_DET# */
+ PAD_CFG_GPI_SCI(GPP_G21, NONE, DEEP, EDGE_SINGLE, INVERT), /* SPI_TPM_PIRQ# */
+ PAD_CFG_GPI(GPP_H10, NONE, PLTRST), /* S_GPI_SKU0 */
+ PAD_CFG_GPI(GPP_H15, NONE, PLTRST), /* BRD_REV0 */
+ PAD_CFG_GPI(GPP_H16, NONE, PLTRST), /* BRD_REV1 */
+ PAD_CFG_GPI(GPP_H17, NONE, PLTRST), /* BRD_REV2 */
+ PAD_CFG_GPI(GPP_H18, NONE, PLTRST), /* S_GPI_SKU1 */
+ PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1), /* DPD_HPD_R */
+ PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), /* DPE_HPD_R */
+ PAD_CFG_NF(GPP_I9, NONE, PLTRST, NF1), /* DDPD_CTRLCLK */
+ PAD_CFG_NF(GPP_I10, DN_20K, PLTRST, NF1), /* DDPD_CTRLDATA */
+};
+
+static void mainboard_configure_super_io(void)
+{
+ const pnp_devfn_t dev = PNP_DEV(0x2e, 7);
+
+ pnp_enter_conf_state(dev);
+ pnp_set_logical_device(dev);
+
+ pnp_write_config(dev, 0x23, 0x59);
+ pnp_write_config(dev, 0x25, 0x10);
+ pnp_write_config(dev, 0x26, 0x04);
+ pnp_write_config(dev, 0x28, 0x08);
+ pnp_write_config(dev, 0x2a, 0x81);
+ pnp_write_config(dev, 0x71, 0x08);
+ pnp_write_config(dev, 0xc0, 0x00);
+ pnp_write_config(dev, 0xc1, 0x04);
+ pnp_write_config(dev, 0xc8, 0x00);
+ pnp_write_config(dev, 0xc9, 0x04);
+ pnp_write_config(dev, 0xcb, 0x08);
+ pnp_write_config(dev, 0xd5, 0x07);
+ pnp_write_config(dev, 0xf8, 0x12);
+ pnp_write_config(dev, 0xf9, 0x01);
+
+ pnp_exit_conf_state(dev);
+}
+
+void bootblock_mainboard_early_init(void)
+{
+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+
+ mainboard_configure_super_io();
+}
+
+void bootblock_mainboard_init(void)
+{
+ const gpio_t rev_gpios[] = {
+ GPP_H15,
+ GPP_H16,
+ GPP_H17,
+ };
+
+ const char *const rev_table[8] = {
+ [0] = "DB",
+ [1] = "Pre-SI",
+ [2] = "SI",
+ [3] = "PV",
+ [4] = "1.00 (SMVB)",
+ [5] = "1.10 (ECN1)",
+ [6] = "1.20 (ECN1)",
+ [7] = "1.30 (ECN1)",
+ };
+
+ const char *const brd_str = gpio_get(GPP_H10) ? "Sid" : "Manny";
+
+ const uint32_t brd_rev = gpio_base2_value(rev_gpios, ARRAY_SIZE(rev_gpios));
+
+ printk(BIOS_DEBUG, "Mainboard: %s rev %s\n", brd_str, rev_table[brd_rev]);
+}
diff --git a/src/mainboard/hp/280_g2/data.vbt b/src/mainboard/hp/280_g2/data.vbt
new file mode 100644
index 0000000000..d444f0932e
--- /dev/null
+++ b/src/mainboard/hp/280_g2/data.vbt
Binary files differ
diff --git a/src/mainboard/hp/280_g2/devicetree.cb b/src/mainboard/hp/280_g2/devicetree.cb
new file mode 100644
index 0000000000..8784080f95
--- /dev/null
+++ b/src/mainboard/hp/280_g2/devicetree.cb
@@ -0,0 +1,144 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/intel/skylake
+ register "common_soc_config" = "{
+ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+ }"
+
+ register "SerialIoDevMode" = "{
+ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, /* Routed to debug header */
+ }"
+
+ register "eist_enable" = "1"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+ device domain 0 on
+ subsystemid 0x103c 0x2b5e inherit
+ device pci 00.0 on end # Host bridge
+ device pci 01.0 on end # PCIe graphics
+ device pci 02.0 on end # iGPU
+ device pci 04.0 on end # CPU Thermal
+ device pci 08.0 on end # GMM
+ device pci 14.0 on # xHCI
+ register "usb2_ports[0]" = "USB2_PORT_MID(OC0)"
+ register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"
+ register "usb2_ports[2]" = "USB2_PORT_MID(OC4)"
+ register "usb2_ports[3]" = "USB2_PORT_MID(OC4)"
+ register "usb2_ports[4]" = "USB2_PORT_MID(OC2)"
+ register "usb2_ports[5]" = "USB2_PORT_MID(OC2)"
+ register "usb2_ports[6]" = "USB2_PORT_MID(OC0)"
+ register "usb2_ports[7]" = "USB2_PORT_MID(OC0)"
+ register "usb2_ports[8]" = "USB2_PORT_MID(OC0)"
+ register "usb2_ports[9]" = "USB2_PORT_MID(OC0)"
+ register "usb2_ports[10]" = "USB2_PORT_MID(OC1)"
+ register "usb2_ports[11]" = "USB2_PORT_MID(OC1)"
+ register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)"
+ register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)"
+
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)"
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)"
+ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)"
+ register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)"
+ register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)"
+ register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)"
+ register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)"
+ register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)"
+ end
+ device pci 14.1 off end # USB OTG
+ device pci 14.2 on end # PCH Thermal
+ device pci 15.0 off end # I2C #0
+ device pci 15.1 off end # I2C #1
+ device pci 15.2 off end # I2C #2
+ device pci 15.3 off end # I2C #3
+ device pci 16.0 on end # MEI #1
+ device pci 16.1 off end # MEI #2
+ device pci 16.2 off end # ME IDE-R
+ device pci 16.3 off end # ME KT
+ device pci 16.4 off end # MEI #3
+ device pci 17.0 on # SATA
+ register "SataMode" = "SATA_AHCI"
+ register "SataSalpSupport" = "1"
+ register "SataPortsEnable" = "{
+ [0] = 1,
+ [1] = 1,
+ [2] = 1,
+ [3] = 1,
+ }"
+ register "SataPortsHotPlug" = "{
+ [0] = 1,
+ [1] = 1,
+ [2] = 1,
+ [3] = 1,
+ }"
+ # DevSlp not supported
+
+ # Enable test mode for SATA margining
+ register "SataTestMode" = "1"
+ end
+ device pci 19.0 on end # UART #2
+ device pci 1c.0 off end # RP #1
+ device pci 1c.1 off end # RP #2
+ device pci 1c.2 off end # RP #3
+ device pci 1c.3 off end # RP #4
+ device pci 1c.4 on # RP #5: IT8893E PCI Bridge
+ register "PcieRpEnable[4]" = "1"
+ register "PcieRpLtrEnable[4]" = "1"
+ register "PcieRpAdvancedErrorReporting[4]" = "1"
+ register "PcieRpClkSrcNumber[4]" = "11"
+ end
+ device pci 1c.5 on # RP #6: PCIe x1 slot
+ register "PcieRpEnable[5]" = "1"
+ register "PcieRpHotPlug[5]" = "1"
+ register "PcieRpLtrEnable[5]" = "1"
+ register "PcieRpAdvancedErrorReporting[5]" = "1"
+ register "PcieRpClkSrcNumber[5]" = "6"
+ end
+ device pci 1c.6 on # RP #7: RTL8111 GbE NIC
+ register "PcieRpEnable[6]" = "1"
+ register "PcieRpLtrEnable[6]" = "1"
+ register "PcieRpAdvancedErrorReporting[6]" = "1"
+ register "PcieRpClkSrcNumber[6]" = "10"
+ end
+ device pci 1c.7 on # RP #8: M.2 2230 slot
+ register "PcieRpEnable[7]" = "1"
+ register "PcieRpHotPlug[7]" = "1"
+ register "PcieRpLtrEnable[7]" = "1"
+ register "PcieRpAdvancedErrorReporting[7]" = "1"
+ register "PcieRpClkSrcNumber[7]" = "12"
+ end
+ device pci 1d.0 off end # RP #9
+ device pci 1d.1 off end # RP #10
+ device pci 1d.2 off end # RP #11
+ device pci 1d.3 off end # RP #12
+ device pci 1e.0 off end # UART #0
+ device pci 1e.1 off end # UART #1
+ device pci 1e.2 off end # GSPI #0
+ device pci 1e.3 off end # GSPI #1
+ device pci 1f.0 on # LPC bridge
+ register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
+ # FIXME: Missing Super I/O HWM config
+ register "gen1_dec" = "0x000c0291"
+ end
+ device pci 1f.1 on end # P2SB
+ device pci 1f.2 on # PMC
+ register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS"
+ register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S"
+ register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S"
+ register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S"
+ register "PmConfigPwrCycDur" = "RESET_POWER_CYCLE_4S"
+ end
+ device pci 1f.3 on end # Intel HDA
+ device pci 1f.4 on end # SMBus
+ device pci 1f.5 on end # SPI
+ device pci 1f.6 off end # Intel GbE
+ device pci 1f.7 on # Trace Hub
+ register "TraceHubMemReg0Size" = "2"
+ register "TraceHubMemReg1Size" = "2"
+ end
+ end
+end
diff --git a/src/mainboard/hp/280_g2/dsdt.asl b/src/mainboard/hp/280_g2/dsdt.asl
new file mode 100644
index 0000000000..26ebbe071f
--- /dev/null
+++ b/src/mainboard/hp/280_g2/dsdt.asl
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ ACPI_DSDT_REV_2,
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20110725
+)
+{
+ #include <acpi/dsdt_top.asl>
+
+ #include <cpu/intel/common/acpi/cpu.asl>
+ #include <soc/intel/common/block/acpi/acpi/platform.asl>
+ #include <soc/intel/skylake/acpi/globalnvs.asl>
+
+ Device (\_SB.PCI0) {
+ #include <soc/intel/skylake/acpi/systemagent.asl>
+ #include <soc/intel/skylake/acpi/pch.asl>
+ }
+
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/hp/280_g2/gma-mainboard.ads b/src/mainboard/hp/280_g2/gma-mainboard.ads
new file mode 100644
index 0000000000..735fe2684c
--- /dev/null
+++ b/src/mainboard/hp/280_g2/gma-mainboard.ads
@@ -0,0 +1,16 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (HDMI3, -- DVI-I
+ eDP, -- VGA
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/hp/280_g2/hda_verb.c b/src/mainboard/hp/280_g2/hda_verb.c
new file mode 100644
index 0000000000..3ed214fc04
--- /dev/null
+++ b/src/mainboard/hp/280_g2/hda_verb.c
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ /* coreboot specific header */
+ 0x10ec0221, /* Codec Vendor / Device ID: Realtek ALC221 */
+ 0x103c2b5e, /* Subsystem ID */
+ 11, /* Number of jacks */
+ AZALIA_SUBVENDOR(0, 0x103c2b5e),
+ AZALIA_PIN_CFG(0, 0x12, 0x40000000),
+ AZALIA_PIN_CFG(0, 0x14, 0x01014010),
+ AZALIA_PIN_CFG(0, 0x17, 0x90170120),
+ AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1a, 0x01813030),
+ AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1d, 0x4044c301),
+ AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x21, 0x0221101f),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/hp/280_g2/romstage.c b/src/mainboard/hp/280_g2/romstage.c
new file mode 100644
index 0000000000..8f32d2495a
--- /dev/null
+++ b/src/mainboard/hp/280_g2/romstage.c
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <assert.h>
+#include <fsp/soc_binding.h>
+#include <soc/romstage.h>
+#include <spd_bin.h>
+#include <string.h>
+#include <types.h>
+
+/* Rcomp resistors are located on the CPU package */
+static const u16 rcomp_resistors[3] = { 121, 75, 100 };
+
+/* Rcomp targets for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk */
+static const u16 rcomp_targets[5] = { 50, 26, 20, 20, 26 };
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+ FSP_M_CONFIG *const mem_cfg = &mupd->FspmConfig;
+
+ struct spd_block blk = {
+ .addr_map = { 0x51, 0x50 },
+ };
+
+ get_spd_smbus(&blk);
+
+ mem_cfg->DqPinsInterleaved = true;
+
+ mem_cfg->UserBd = BOARD_TYPE_DESKTOP;
+
+ mem_cfg->MemorySpdDataLen = blk.len;
+ mem_cfg->MemorySpdPtr00 = (u32)blk.spd_array[0];
+ mem_cfg->MemorySpdPtr10 = (u32)blk.spd_array[1];
+
+ assert(sizeof(mem_cfg->RcompResistor) == sizeof(rcomp_resistors));
+ assert(sizeof(mem_cfg->RcompTarget) == sizeof(rcomp_targets));
+
+ memcpy(mem_cfg->RcompResistor, rcomp_resistors, sizeof(mem_cfg->RcompResistor));
+ memcpy(mem_cfg->RcompTarget, rcomp_targets, sizeof(mem_cfg->RcompTarget));
+
+ /* These settings are most likely useless if using a release build of FSP */
+ mem_cfg->PcdDebugInterfaceFlags = 2; /* Enable UART */
+ mem_cfg->PcdSerialIoUartNumber = 2; /* Use UART #2 */
+ mem_cfg->PcdSerialDebugBaudRate = 7; /* 115200 baud */
+ mem_cfg->PcdSerialDebugLevel = 3; /* Log <= Info */
+
+ /* Trace Hub */
+ mem_cfg->PcdDebugInterfaceFlags |= 1 << 5;
+
+ /* Allow changing memory timings after MRC is done */
+ mem_cfg->RealtimeMemoryTiming = 1;
+ mem_cfg->SaOcSupport = 1;
+}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 12:46:35 +0000