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-rw-r--r--src/mainboard/foxconn/d41s/romstage.c101
-rw-r--r--src/mainboard/intel/d510mo/romstage.c103
2 files changed, 13 insertions, 191 deletions
diff --git a/src/mainboard/foxconn/d41s/romstage.c b/src/mainboard/foxconn/d41s/romstage.c
index cde813c159..ade85e66a5 100644
--- a/src/mainboard/foxconn/d41s/romstage.c
+++ b/src/mainboard/foxconn/d41s/romstage.c
@@ -15,44 +15,16 @@
* GNU General Public License for more details.
*/
-#include <stdint.h>
-#include <stdlib.h>
-#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
-#include <console/console.h>
#include <southbridge/intel/i82801gx/i82801gx.h>
-#include <southbridge/intel/common/gpio.h>
-#include <northbridge/intel/pineview/raminit.h>
#include <northbridge/intel/pineview/pineview.h>
-#include <cpu/x86/bist.h>
-#include <cpu/intel/romstage.h>
-#include <cpu/x86/lapic.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8721f/it8721f.h>
-#include <lib.h>
-#include <cbmem.h>
-#include <romstage_handoff.h>
-#include <timestamp.h>
#define SERIAL_DEV PNP_DEV(0x2e, IT8721F_SP1)
-/* Early mainboard specific GPIO setup */
-static void mb_gpio_init(void)
-{
- pci_devfn_t dev;
-
- /* Southbridge GPIOs. */
- dev = PCI_DEV(0x0, 0x1f, 0x0);
-
- /* Set the value for GPIO base address register and enable GPIO. */
- pci_write_config32(dev, GPIO_BASE, (DEFAULT_GPIOBASE | 1));
- pci_write_config8(dev, GPIO_CNTL, 0x10);
-
- setup_pch_gpios(&mainboard_gpio_map);
-}
-
-static void nm10_enable_lpc(void)
+void mb_enable_lpc(void)
{
/* Disable Serial IRQ */
pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
@@ -65,75 +37,12 @@ static void nm10_enable_lpc(void)
/* Environment Controller */
pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x00fc0a01);
-}
-static void rcba_config(void)
-{
- /* Set up virtual channel 0 */
- RCBA32(0x0014) = 0x80000001;
- RCBA32(0x001c) = 0x03128010;
-
- /* Enable IOAPIC */
- RCBA8(OIC) = 0x03;
+ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
}
-void mainboard_romstage_entry(unsigned long bist)
+void get_mb_spd_addrmap(u8 *spd_addrmap)
{
- const u8 spd_addrmap[4] = { 0x50, 0x51, 0, 0 };
- int cbmem_was_initted;
- int s3resume = 0;
- int boot_path;
-
- if (bist == 0)
- enable_lapic();
-
- /* Disable watchdog timer */
- RCBA32(GCS) = RCBA32(GCS) | 0x20;
-
- /* Set southbridge and Super I/O GPIOs. */
- mb_gpio_init();
-
- nm10_enable_lpc();
- ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
-
- report_bist_failure(bist);
- enable_smbus();
-
- pineview_early_initialization();
-
- post_code(0x30);
-
- s3resume = southbridge_detect_s3_resume();
-
- if (s3resume) {
- boot_path = BOOT_PATH_RESUME;
- } else {
- if (MCHBAR32(0xf14) & (1 << 8)) /* HOT RESET */
- boot_path = BOOT_PATH_RESET;
- else
- boot_path = BOOT_PATH_NORMAL;
- }
-
- printk(BIOS_DEBUG, "Initializing memory\n");
- timestamp_add_now(TS_BEFORE_INITRAM);
- sdram_initialize(boot_path, spd_addrmap);
- timestamp_add_now(TS_AFTER_INITRAM);
- printk(BIOS_DEBUG, "Memory initialized\n");
-
- post_code(0x31);
-
- quick_ram_check();
-
- rcba_config();
-
- cbmem_was_initted = !cbmem_recovery(s3resume);
-
- if (!cbmem_was_initted && s3resume) {
- /* Failed S3 resume, reset to come up cleanly */
- outb(0x6, 0xcf9);
- halt();
- }
-
- romstage_handoff_init(s3resume);
+ spd_addrmap[0] = 0x50;
+ spd_addrmap[1] = 0x51;
}
diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c
index 8648e20de0..28e2e25999 100644
--- a/src/mainboard/intel/d510mo/romstage.c
+++ b/src/mainboard/intel/d510mo/romstage.c
@@ -14,45 +14,17 @@
* GNU General Public License for more details.
*/
-#include <stdint.h>
-#include <stdlib.h>
-#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
-#include <console/console.h>
#include <southbridge/intel/i82801gx/i82801gx.h>
-#include <southbridge/intel/common/gpio.h>
-#include <northbridge/intel/pineview/raminit.h>
#include <northbridge/intel/pineview/pineview.h>
-#include <cpu/x86/bist.h>
-#include <cpu/intel/romstage.h>
-#include <cpu/x86/lapic.h>
#include <superio/winbond/w83627thg/w83627thg.h>
#include <superio/winbond/common/winbond.h>
-#include <lib.h>
-#include <cbmem.h>
-#include <romstage_handoff.h>
-#include <timestamp.h>
#define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1)
#define SUPERIO_DEV PNP_DEV(0x4e, 0)
-/* Early mainboard specific GPIO setup */
-static void mb_gpio_init(void)
-{
- pci_devfn_t dev;
-
- /* Southbridge GPIOs. */
- dev = PCI_DEV(0x0, 0x1f, 0x0);
-
- /* Set the value for GPIO base address register and enable GPIO. */
- pci_write_config32(dev, GPIO_BASE, (DEFAULT_GPIOBASE | 1));
- pci_write_config8(dev, GPIO_CNTL, 0x10);
-
- setup_pch_gpios(&mainboard_gpio_map);
-}
-
-static void nm10_enable_lpc(void)
+void mb_enable_lpc(void)
{
/* Disable Serial IRQ */
pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0x00);
@@ -64,14 +36,12 @@ static void nm10_enable_lpc(void)
| COMB_LPC_EN);
pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x7c0291);
+
+ winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
}
-static void rcba_config(void)
+void mb_pirq_setup(void)
{
- /* Set up virtual channel 0 */
- RCBA32(0x0014) = 0x80000001;
- RCBA32(0x001c) = 0x03128010;
-
/* dev irq route register */
RCBA16(D31IR) = 0x0132;
RCBA16(D30IR) = 0x0146;
@@ -79,69 +49,12 @@ static void rcba_config(void)
RCBA16(D28IR) = 0x3201;
RCBA16(D27IR) = 0x0146;
- /* Enable IOAPIC */
- RCBA8(OIC) = 0x03;
-
+ /* Does not belong here, but is it needed? */
RCBA32(FD) |= FD_INTLAN;
}
-void mainboard_romstage_entry(unsigned long bist)
+void get_mb_spd_addrmap(u8 *spd_addrmap)
{
- const u8 spd_addrmap[4] = { 0x50, 0x51, 0, 0 };
- int cbmem_was_initted;
- int s3resume = 0;
- int boot_path;
-
- if (bist == 0)
- enable_lapic();
-
- /* Disable watchdog timer */
- RCBA32(GCS) = RCBA32(GCS) | 0x20;
-
- /* Set southbridge and Super I/O GPIOs. */
- mb_gpio_init();
-
- nm10_enable_lpc();
- winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
-
- report_bist_failure(bist);
- enable_smbus();
-
- pineview_early_initialization();
-
- post_code(0x30);
-
- s3resume = southbridge_detect_s3_resume();
-
- if (s3resume) {
- boot_path = BOOT_PATH_RESUME;
- } else {
- if (MCHBAR32(0xf14) & (1 << 8)) /* HOT RESET */
- boot_path = BOOT_PATH_RESET;
- else
- boot_path = BOOT_PATH_NORMAL;
- }
-
- printk(BIOS_DEBUG, "Initializing memory\n");
- timestamp_add_now(TS_BEFORE_INITRAM);
- sdram_initialize(boot_path, spd_addrmap);
- timestamp_add_now(TS_AFTER_INITRAM);
- printk(BIOS_DEBUG, "Memory initialized\n");
-
- post_code(0x31);
-
- quick_ram_check();
-
- rcba_config();
-
- cbmem_was_initted = !cbmem_recovery(s3resume);
-
- if (!cbmem_was_initted && s3resume) {
- /* Failed S3 resume, reset to come up cleanly */
- outb(0x6, 0xcf9);
- halt();
- }
-
- romstage_handoff_init(s3resume);
+ spd_addrmap[0] = 0x50;
+ spd_addrmap[1] = 0x51;
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 22:55:09 +0000