diff options
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/brya/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/google/brya/mainboard.c | 31 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb | 10 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb | 10 |
4 files changed, 30 insertions, 22 deletions
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 00e8bc9c18..6690a905ff 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -2,6 +2,7 @@ config BOARD_GOOGLE_BRYA_COMMON def_bool n select ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR select BOARD_ROMSIZE_KB_32768 + select CR50_USE_LONG_INTERRUPT_PULSES select DRIVERS_GENERIC_ALC1015 select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_GENERIC_MAX98357A diff --git a/src/mainboard/google/brya/mainboard.c b/src/mainboard/google/brya/mainboard.c index 488eb889cc..42536bb793 100644 --- a/src/mainboard/google/brya/mainboard.c +++ b/src/mainboard/google/brya/mainboard.c @@ -1,12 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <acpi/acpigen.h> #include <baseboard/variants.h> #include <device/device.h> +#include <drivers/tpm/cr50.h> +#include <drivers/wwan/fm/chip.h> #include <ec/ec.h> #include <soc/ramstage.h> #include <fw_config.h> -#include <acpi/acpigen.h> -#include <drivers/wwan/fm/chip.h> +#include <security/tpm/tss.h> +#include <soc/gpio.h> +#include <soc/ramstage.h> WEAK_DEV_PTR(rp6_wwan); @@ -28,6 +32,29 @@ static void mainboard_smbios_strings(struct device *dev, struct smbios_type11 *t void mainboard_update_soc_chip_config(struct soc_intel_alderlake_config *config) { + int ret; + + ret = tlcl_lib_init(); + if (ret != VB2_SUCCESS) { + printk(BIOS_ERR, "tlcl_lib_init() failed: 0x%x\n", ret); + return; + } + + if (cr50_is_long_interrupt_pulse_enabled()) { + printk(BIOS_INFO, "Enabling GPIO PM b/c CR50 has long IRQ pulse support\n"); + config->gpio_override_pm = 0; + } else { + printk(BIOS_INFO, "Disabling GPIO PM b/c CR50 does not have long IRQ pulse " + "support\n"); + config->gpio_override_pm = 1; + config->gpio_pm[COMM_0] = 0; + config->gpio_pm[COMM_1] = 0; + config->gpio_pm[COMM_2] = 0; + config->gpio_pm[COMM_3] = 0; + config->gpio_pm[COMM_4] = 0; + config->gpio_pm[COMM_5] = 0; + } + variant_update_soc_chip_config(config); } diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb index 98dd3a5fec..9eb8bb2adb 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb @@ -76,16 +76,6 @@ chip soc/intel/alderlake # FIVR RFI Spread Spectrum 1.5% register "FivrSpreadSpectrum" = "FIVR_SS_1_5" - # This disables autonomous GPIO power management, otherwise - # old cr50 FW only supports short pulses. - register "gpio_override_pm" = "1" - register "gpio_pm[COMM_0]" = "0" - register "gpio_pm[COMM_1]" = "0" - register "gpio_pm[COMM_2]" = "0" - register "gpio_pm[COMM_3]" = "0" - register "gpio_pm[COMM_4]" = "0" - register "gpio_pm[COMM_5]" = "0" - # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index 6ac796af1f..0558307f1c 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -72,16 +72,6 @@ chip soc/intel/alderlake # FIVR RFI Spread Spectrum 1.5% register "FivrSpreadSpectrum" = "FIVR_SS_1_5" - # This disables autonomous GPIO power management, otherwise old cr50 FW - # only supports short pulses and they can be missed by the PCH. - register "gpio_override_pm" = "1" - register "gpio_pm[COMM_0]" = "0" - register "gpio_pm[COMM_1]" = "0" - register "gpio_pm[COMM_2]" = "0" - register "gpio_pm[COMM_3]" = "0" - register "gpio_pm[COMM_4]" = "0" - register "gpio_pm[COMM_5]" = "0" - # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | |