2 files changed, 40 insertions, 0 deletions
diff --git a/src/mainboard/intel/cannonlake_rvp/Makefile.inc b/src/mainboard/intel/cannonlake_rvp/Makefile.inc
index 247f1719b8..7e8219640d 100644
--- a/src/mainboard/intel/cannonlake_rvp/Makefile.inc
+++ b/src/mainboard/intel/cannonlake_rvp/Makefile.inc
@@ -24,6 +24,7 @@ verstage-$(CONFIG_CHROMEOS) += chromeos.c
 romstage-$(CONFIG_CHROMEOS) += chromeos.c
 
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-y += mainboard.c
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
 subdirs-y += variants/baseboard
diff --git a/src/mainboard/intel/cannonlake_rvp/mainboard.c b/src/mainboard/intel/cannonlake_rvp/mainboard.c
new file mode 100644
index 0000000000..855d368d56
--- /dev/null
+++ b/src/mainboard/intel/cannonlake_rvp/mainboard.c
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <device/device.h>
+#include <soc/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <variant/gpio.h>
+
+static void mainboard_init(void *chip_info)
+{
+	const struct pad_config *pads;
+	size_t num;
+
+	pads = variant_gpio_table(&num);
+	gpio_configure_pads(pads, num);
+}
+
+static void mainboard_enable(device_t dev)
+{
+	dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
+}
+
+struct chip_operations mainboard_ops = {
+	.init = mainboard_init,
+	.enable_dev = mainboard_enable,
+};