diff options
Diffstat (limited to 'src/mainboard')
117 files changed, 237 insertions, 244 deletions
diff --git a/src/mainboard/advantech/pcm-5820/romstage.c b/src/mainboard/advantech/pcm-5820/romstage.c index 3c77b11e2a..86281e3ba4 100644 --- a/src/mainboard/advantech/pcm-5820/romstage.c +++ b/src/mainboard/advantech/pcm-5820/romstage.c @@ -27,7 +27,7 @@ #include "northbridge/amd/gx1/raminit.c" #include "cpu/x86/bist.h" #include "superio/winbond/w83977f/w83977f_early_serial.c" -#include "southbridge/amd/cs5530/cs5530_enable_rom.c" +#include "southbridge/amd/cs5530/enable_rom.c" #define SERIAL_DEV PNP_DEV(0x3f0, W83977F_SP1) diff --git a/src/mainboard/amd/db800/romstage.c b/src/mainboard/amd/db800/romstage.c index 8b7027189b..188ec1f8f5 100644 --- a/src/mainboard/amd/db800/romstage.c +++ b/src/mainboard/amd/db800/romstage.c @@ -31,8 +31,8 @@ #include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> -#include "southbridge/amd/cs5536/cs5536_early_smbus.c" -#include "southbridge/amd/cs5536/cs5536_early_setup.c" +#include "southbridge/amd/cs5536/early_smbus.c" +#include "southbridge/amd/cs5536/early_setup.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c index 88ecd941ef..6e3d3fcad1 100644 --- a/src/mainboard/amd/dbm690t/romstage.c +++ b/src/mainboard/amd/dbm690t/romstage.c @@ -43,8 +43,8 @@ #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/amd/rs690/rs690_early_setup.c" -#include "southbridge/amd/sb600/sb600_early_setup.c" +#include "southbridge/amd/rs690/early_setup.c" +#include "southbridge/amd/sb600/early_setup.c" #include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */ static void memreset(int controllers, const struct mem_controller *ctrl) { } diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c index c20c0a6f7b..4ad0aa0d3b 100644 --- a/src/mainboard/amd/mahogany/romstage.c +++ b/src/mainboard/amd/mahogany/romstage.c @@ -43,9 +43,9 @@ #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/amd/rs780/rs780_early_setup.c" -#include "southbridge/amd/sb700/sb700_early_setup.c" -#include "northbridge/amd/amdk8/debug.c" /* After sb700_early_setup.c! */ +#include "southbridge/amd/rs780/early_setup.c" +#include "southbridge/amd/sb700/early_setup.c" +#include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */ static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index 1157b00832..92502e32a4 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -47,8 +47,8 @@ #include "cpu/x86/mtrr/earlymtrr.c" #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" -#include "southbridge/amd/rs780/rs780_early_setup.c" -#include "southbridge/amd/sb700/sb700_early_setup.c" +#include "southbridge/amd/rs780/early_setup.c" +#include "southbridge/amd/sb700/early_setup.c" #include "northbridge/amd/amdfam10/debug.c" #include <spd.h> @@ -69,7 +69,7 @@ static int spd_read_byte(u32 device, u32 address) #include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" -#include "southbridge/amd/sb700/sb700_early_setup.c" +#include "southbridge/amd/sb700/early_setup.c" void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/amd/norwich/romstage.c b/src/mainboard/amd/norwich/romstage.c index f60313842a..7350c440c9 100644 --- a/src/mainboard/amd/norwich/romstage.c +++ b/src/mainboard/amd/norwich/romstage.c @@ -31,8 +31,8 @@ #include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> -#include "southbridge/amd/cs5536/cs5536_early_smbus.c" -#include "southbridge/amd/cs5536/cs5536_early_setup.c" +#include "southbridge/amd/cs5536/early_smbus.c" +#include "southbridge/amd/cs5536/early_setup.c" static inline int spd_read_byte(unsigned int device, unsigned int address) { diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c index 187eb207c2..291d1f4607 100644 --- a/src/mainboard/amd/pistachio/romstage.c +++ b/src/mainboard/amd/pistachio/romstage.c @@ -38,9 +38,9 @@ #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/amd/rs690/rs690_early_setup.c" -#include "southbridge/amd/sb600/sb600_early_setup.c" -#include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */ +#include "southbridge/amd/rs690/early_setup.c" +#include "southbridge/amd/sb600/early_setup.c" +#include "northbridge/amd/amdk8/debug.c" /* After sb600/early_setup.c! */ static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } diff --git a/src/mainboard/amd/rumba/romstage.c b/src/mainboard/amd/rumba/romstage.c index ade6f62d0f..ecc22c08d3 100644 --- a/src/mainboard/amd/rumba/romstage.c +++ b/src/mainboard/amd/rumba/romstage.c @@ -10,8 +10,8 @@ #include <cpu/amd/gx2def.h> #include <cpu/amd/geode_post_code.h> #include <spd.h> -#include "southbridge/amd/cs5536/cs5536_early_smbus.c" -#include "southbridge/amd/cs5536/cs5536_early_setup.c" +#include "southbridge/amd/cs5536/early_smbus.c" +#include "southbridge/amd/cs5536/early_setup.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index ee78f31c5c..10b7eccdcc 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -13,7 +13,7 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> -#include "southbridge/amd/amd8111/amd8111_early_smbus.c" +#include "southbridge/amd/amd8111/early_smbus.c" #include <reset.h> #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" @@ -26,7 +26,7 @@ #include <cpu/amd/mtrr.h> #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" +#include "southbridge/amd/amd8111/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index 2124c284c9..ff0c1da06e 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -35,7 +35,7 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> -#include "southbridge/amd/amd8111/amd8111_early_smbus.c" +#include "southbridge/amd/amd8111/early_smbus.c" #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" #include <lib.h> @@ -48,7 +48,7 @@ #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "northbridge/amd/amdfam10/setup_resource_map.c" -#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" +#include "southbridge/amd/amd8111/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index ddb5076c12..8e22cdab49 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -47,8 +47,8 @@ #include "cpu/x86/mtrr/earlymtrr.c" #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" -#include "southbridge/amd/rs780/rs780_early_setup.c" -#include "southbridge/amd/sb700/sb700_early_setup.c" +#include "southbridge/amd/rs780/early_setup.c" +#include "southbridge/amd/sb700/early_setup.c" #include "northbridge/amd/amdfam10/debug.c" static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -68,7 +68,6 @@ static int spd_read_byte(u32 device, u32 address) #include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" -#include "southbridge/amd/sb700/sb700_early_setup.c" #include <spd.h> void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) diff --git a/src/mainboard/arima/hdama/romstage.c b/src/mainboard/arima/hdama/romstage.c index 61a0b0e5ba..56e66e1e6c 100644 --- a/src/mainboard/arima/hdama/romstage.c +++ b/src/mainboard/arima/hdama/romstage.c @@ -9,7 +9,7 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "southbridge/amd/amd8111/amd8111_early_smbus.c" +#include "southbridge/amd/amd8111/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" @@ -21,7 +21,7 @@ #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include <spd.h> -#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" +#include "southbridge/amd/amd8111/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1) diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c index 7b213bf1c7..4df61a2679 100644 --- a/src/mainboard/artecgroup/dbe61/romstage.c +++ b/src/mainboard/artecgroup/dbe61/romstage.c @@ -33,8 +33,8 @@ #include "southbridge/amd/cs5536/cs5536.h" #include "spd_table.h" #include <spd.h> -#include "southbridge/amd/cs5536/cs5536_early_smbus.c" -#include "southbridge/amd/cs5536/cs5536_early_setup.c" +#include "southbridge/amd/cs5536/early_smbus.c" +#include "southbridge/amd/cs5536/early_setup.c" static int spd_read_byte(unsigned device, unsigned address) { diff --git a/src/mainboard/asi/mb_5blgp/romstage.c b/src/mainboard/asi/mb_5blgp/romstage.c index 3d3367aa85..1adca8a7ea 100644 --- a/src/mainboard/asi/mb_5blgp/romstage.c +++ b/src/mainboard/asi/mb_5blgp/romstage.c @@ -27,7 +27,7 @@ #include "northbridge/amd/gx1/raminit.c" #include "cpu/x86/bist.h" #include "superio/nsc/pc87351/pc87351_early_serial.c" -#include "southbridge/amd/cs5530/cs5530_enable_rom.c" +#include "southbridge/amd/cs5530/enable_rom.c" #define SERIAL_DEV PNP_DEV(0x2e, PC87351_SP1) diff --git a/src/mainboard/asi/mb_5blmp/romstage.c b/src/mainboard/asi/mb_5blmp/romstage.c index f79c2437b9..01b5a78326 100644 --- a/src/mainboard/asi/mb_5blmp/romstage.c +++ b/src/mainboard/asi/mb_5blmp/romstage.c @@ -28,7 +28,7 @@ #include "northbridge/amd/gx1/raminit.c" #include "superio/nsc/pc87351/pc87351_early_serial.c" #include "cpu/x86/bist.h" -#include "southbridge/amd/cs5530/cs5530_enable_rom.c" +#include "southbridge/amd/cs5530/enable_rom.c" #define SERIAL_DEV PNP_DEV(0x2e, PC87351_SP1) diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c index fcbda3ff89..c35d22b05b 100644 --- a/src/mainboard/asrock/939a785gmh/romstage.c +++ b/src/mainboard/asrock/939a785gmh/romstage.c @@ -44,9 +44,9 @@ #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/amd/rs780/rs780_early_setup.c" -#include "southbridge/amd/sb700/sb700_early_setup.c" -#include "northbridge/amd/amdk8/debug.c" /* After sb700_early_setup.c! */ +#include "southbridge/amd/rs780/early_setup.c" +#include "southbridge/amd/sb700/early_setup.c" +#include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */ #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) #define GPIO2345_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V) diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c index 9558d055b1..f7ee69685f 100644 --- a/src/mainboard/asus/a8n_e/romstage.c +++ b/src/mainboard/asus/a8n_e/romstage.c @@ -38,7 +38,7 @@ #include <cpu/amd/model_fxx_rev.h> #include <console/console.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "southbridge/nvidia/ck804/ck804_early_smbus.h" +#include "southbridge/nvidia/ck804/early_smbus.h" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" @@ -60,8 +60,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/raminit.c" #include "lib/generic_sdram.c" -#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h" -#include "southbridge/nvidia/ck804/ck804_early_setup.c" +#include "southbridge/nvidia/ck804/early_setup_ss.h" +#include "southbridge/nvidia/ck804/early_setup.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "northbridge/amd/amdk8/early_ht.c" diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index 1f3c088858..cbba7cf5b7 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -41,8 +41,8 @@ unsigned int get_sbdn(unsigned bus); #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/early_ht.c" #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c" -#include "southbridge/via/vt8237r/vt8237r_early_smbus.c" -#include "northbridge/amd/amdk8/debug.c" /* After vt8237r_early_smbus.c! */ +#include "southbridge/via/vt8237r/early_smbus.c" +#include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -79,7 +79,7 @@ void soft_reset(void) } } -#include "southbridge/via/k8t890/k8t890_early_car.c" +#include "southbridge/via/k8t890/early_car.c" #include "northbridge/amd/amdk8/amdk8.h" #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index 1f3c088858..cbba7cf5b7 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -41,8 +41,8 @@ unsigned int get_sbdn(unsigned bus); #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/early_ht.c" #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c" -#include "southbridge/via/vt8237r/vt8237r_early_smbus.c" -#include "northbridge/amd/amdk8/debug.c" /* After vt8237r_early_smbus.c! */ +#include "southbridge/via/vt8237r/early_smbus.c" +#include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -79,7 +79,7 @@ void soft_reset(void) } } -#include "southbridge/via/k8t890/k8t890_early_car.c" +#include "southbridge/via/k8t890/early_car.c" #include "northbridge/amd/amdk8/amdk8.h" #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index 65fdd115aa..714b0544f7 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -45,7 +45,7 @@ unsigned int get_sbdn(unsigned bus); #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include "superio/ite/it8712f/it8712f_early_serial.c" -#include "southbridge/via/vt8237r/vt8237r_early_smbus.c" +#include "southbridge/via/vt8237r/early_smbus.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -62,7 +62,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "southbridge/via/k8t890/k8t890_early_car.c" +#include "southbridge/via/k8t890/early_car.c" #include "northbridge/amd/amdk8/amdk8.h" #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index 3176c39866..fab6d0ca34 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -45,7 +45,7 @@ unsigned int get_sbdn(unsigned bus); #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include "superio/ite/it8712f/it8712f_early_serial.c" -#include "southbridge/via/vt8237r/vt8237r_early_smbus.c" +#include "southbridge/via/vt8237r/early_smbus.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -64,7 +64,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "southbridge/via/k8t890/k8t890_early_car.c" +#include "southbridge/via/k8t890/early_car.c" #include "northbridge/amd/amdk8/amdk8.h" #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index c18b58b87b..e4514f6569 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -47,8 +47,8 @@ #include "cpu/x86/mtrr/earlymtrr.c" #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" -#include "southbridge/amd/rs780/rs780_early_setup.c" -#include "southbridge/amd/sb700/sb700_early_setup.c" +#include "southbridge/amd/rs780/early_setup.c" +#include "southbridge/amd/sb700/early_setup.c" #include "northbridge/amd/amdfam10/debug.c" static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -68,7 +68,6 @@ static int spd_read_byte(u32 device, u32 address) #include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" -#include "southbridge/amd/sb700/sb700_early_setup.c" #include <spd.h> void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index c18b58b87b..e4514f6569 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -47,8 +47,8 @@ #include "cpu/x86/mtrr/earlymtrr.c" #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" -#include "southbridge/amd/rs780/rs780_early_setup.c" -#include "southbridge/amd/sb700/sb700_early_setup.c" +#include "southbridge/amd/rs780/early_setup.c" +#include "southbridge/amd/sb700/early_setup.c" #include "northbridge/amd/amdfam10/debug.c" static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -68,7 +68,6 @@ static int spd_read_byte(u32 device, u32 address) #include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" -#include "southbridge/amd/sb700/sb700_early_setup.c" #include <spd.h> void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) diff --git a/src/mainboard/axus/tc320/romstage.c b/src/mainboard/axus/tc320/romstage.c index f5eeab3c29..c79f42d9f0 100644 --- a/src/mainboard/axus/tc320/romstage.c +++ b/src/mainboard/axus/tc320/romstage.c @@ -28,7 +28,7 @@ #include "northbridge/amd/gx1/raminit.c" #include "superio/nsc/pc97317/pc97317_early_serial.c" #include "cpu/x86/bist.h" -#include "southbridge/amd/cs5530/cs5530_enable_rom.c" +#include "southbridge/amd/cs5530/enable_rom.c" #define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1) diff --git a/src/mainboard/bcom/winnet100/romstage.c b/src/mainboard/bcom/winnet100/romstage.c index f5eeab3c29..c79f42d9f0 100644 --- a/src/mainboard/bcom/winnet100/romstage.c +++ b/src/mainboard/bcom/winnet100/romstage.c @@ -28,7 +28,7 @@ #include "northbridge/amd/gx1/raminit.c" #include "superio/nsc/pc97317/pc97317_early_serial.c" #include "cpu/x86/bist.h" -#include "southbridge/amd/cs5530/cs5530_enable_rom.c" +#include "southbridge/amd/cs5530/enable_rom.c" #define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1) diff --git a/src/mainboard/bcom/winnetp680/romstage.c b/src/mainboard/bcom/winnetp680/romstage.c index 7d9a5a7d57..96df58a148 100644 --- a/src/mainboard/bcom/winnetp680/romstage.c +++ b/src/mainboard/bcom/winnetp680/romstage.c @@ -33,7 +33,7 @@ #include "lib/delay.c" #include <lib.h> #include <spd.h> -#include "southbridge/via/vt8237r/vt8237r_early_smbus.c" +#include "southbridge/via/vt8237r/early_smbus.c" #include "superio/winbond/w83697hf/w83697hf_early_serial.c" #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c index e3791a79bf..d96e7ff38f 100644 --- a/src/mainboard/broadcom/blast/romstage.c +++ b/src/mainboard/broadcom/blast/romstage.c @@ -9,7 +9,7 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c" +#include "southbridge/broadcom/bcm5785/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" @@ -20,7 +20,7 @@ #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c" +#include "southbridge/broadcom/bcm5785/early_setup.c" #define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1) #define RTC_DEV PNP_DEV(0x2e, PC87417_RTC) diff --git a/src/mainboard/dell/s1850/romstage.c b/src/mainboard/dell/s1850/romstage.c index 3927cd2f33..49060ea2ea 100644 --- a/src/mainboard/dell/s1850/romstage.c +++ b/src/mainboard/dell/s1850/romstage.c @@ -6,7 +6,7 @@ #include <cpu/x86/lapic.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" +#include "southbridge/intel/i82801ex/early_smbus.c" #include "northbridge/intel/e7520/raminit.h" #include "superio/nsc/pc8374/pc8374_early_init.c" #include "cpu/x86/lapic/boot_cpu.c" diff --git a/src/mainboard/digitallogic/adl855pc/romstage.c b/src/mainboard/digitallogic/adl855pc/romstage.c index 823e5effa4..12d6bb430b 100644 --- a/src/mainboard/digitallogic/adl855pc/romstage.c +++ b/src/mainboard/digitallogic/adl855pc/romstage.c @@ -10,7 +10,7 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include "southbridge/intel/i82801dx/i82801dx.h" -#include "southbridge/intel/i82801dx/i82801dx_early_smbus.c" +#include "southbridge/intel/i82801dx/early_smbus.c" #include "northbridge/intel/i855/raminit.h" #include "northbridge/intel/i855/debug.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c index 4429914d74..93391b45f7 100644 --- a/src/mainboard/digitallogic/msm800sev/romstage.c +++ b/src/mainboard/digitallogic/msm800sev/romstage.c @@ -12,8 +12,8 @@ #include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> -#include "southbridge/amd/cs5536/cs5536_early_smbus.c" -#include "southbridge/amd/cs5536/cs5536_early_setup.c" +#include "southbridge/amd/cs5536/early_smbus.c" +#include "southbridge/amd/cs5536/early_setup.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/eaglelion/5bcm/romstage.c b/src/mainboard/eaglelion/5bcm/romstage.c index 16ea548ff5..fa6f29f576 100644 --- a/src/mainboard/eaglelion/5bcm/romstage.c +++ b/src/mainboard/eaglelion/5bcm/romstage.c @@ -8,7 +8,7 @@ #include <console/console.h> #include "superio/nsc/pc97317/pc97317_early_serial.c" #include "cpu/x86/bist.h" -#include "southbridge/amd/cs5530/cs5530_enable_rom.c" +#include "southbridge/amd/cs5530/enable_rom.c" #include "northbridge/amd/gx1/raminit.c" #define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1) diff --git a/src/mainboard/getac/p470/acpi_tables.c b/src/mainboard/getac/p470/acpi_tables.c index 490a182494..649dff6ebe 100644 --- a/src/mainboard/getac/p470/acpi_tables.c +++ b/src/mainboard/getac/p470/acpi_tables.c @@ -33,7 +33,7 @@ extern unsigned char AmlCode[]; -#include "southbridge/intel/i82801gx/i82801gx_nvs.h" +#include "southbridge/intel/i82801gx/nvs.h" static void acpi_create_gnvs(global_nvs_t *gnvs) { diff --git a/src/mainboard/getac/p470/mainboard_smi.c b/src/mainboard/getac/p470/mainboard_smi.c index c7fe3f74f1..6831d2e706 100644 --- a/src/mainboard/getac/p470/mainboard_smi.c +++ b/src/mainboard/getac/p470/mainboard_smi.c @@ -24,7 +24,7 @@ #include <console/console.h> #include <cpu/x86/smm.h> #include "southbridge/intel/i82801gx/i82801gx.h" -#include "southbridge/intel/i82801gx/i82801gx_nvs.h" +#include "southbridge/intel/i82801gx/nvs.h" #include "northbridge/intel/i945/udelay.c" #include "ec.c" diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c index 4b31b545af..86e3f6f24c 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c @@ -39,8 +39,8 @@ #include <spd.h> #include <cpu/amd/model_fxx_rev.h> #include "southbridge/sis/sis966/sis966.h" -#include "southbridge/sis/sis966/sis966_early_smbus.c" -#include "southbridge/sis/sis966/sis966_enable_rom.c" +#include "southbridge/sis/sis966/early_smbus.c" +#include "southbridge/sis/sis966/enable_rom.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" @@ -52,7 +52,7 @@ #include "northbridge/amd/amdk8/debug.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/sis/sis966/sis966_early_ctrl.c" +#include "southbridge/sis/sis966/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) @@ -86,7 +86,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ -#include "southbridge/sis/sis966/sis966_early_setup_ss.h" +#include "southbridge/sis/sis966/early_setup_ss.h" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index b76da5533f..55d95a571f 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -36,7 +36,7 @@ #include <usbdebug.h> #include <spd.h> #include <cpu/amd/model_fxx_rev.h> -#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" +#include "southbridge/nvidia/mcp55/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" @@ -48,7 +48,7 @@ #include "northbridge/amd/amdk8/debug.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" +#include "southbridge/nvidia/mcp55/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8716F_GPIO) @@ -69,8 +69,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ -#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" -#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" +#include "southbridge/nvidia/mcp55/early_setup_ss.h" +#include "southbridge/nvidia/mcp55/early_setup_car.c" #include "northbridge/amd/amdk8/amdk8_f.h" #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 8daa2b1dcd..10d369287d 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -43,8 +43,8 @@ #include "cpu/x86/mtrr/earlymtrr.c" #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" -#include "southbridge/amd/rs780/rs780_early_setup.c" -#include "southbridge/amd/sb700/sb700_early_setup.c" +#include "southbridge/amd/rs780/early_setup.c" +#include "southbridge/amd/sb700/early_setup.c" #include "northbridge/amd/amdfam10/debug.c" static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -64,7 +64,6 @@ static int spd_read_byte(u32 device, u32 address) #include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" -#include "southbridge/amd/sb700/sb700_early_setup.c" #include <spd.h> void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index bbf1f58a70..7245eb9d91 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -47,8 +47,8 @@ #include "cpu/x86/mtrr/earlymtrr.c" #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" -#include "southbridge/amd/rs780/rs780_early_setup.c" -#include "southbridge/amd/sb700/sb700_early_setup.c" +#include "southbridge/amd/rs780/early_setup.c" +#include "southbridge/amd/sb700/early_setup.c" #include "northbridge/amd/amdfam10/debug.c" static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -68,7 +68,6 @@ static int spd_read_byte(u32 device, u32 address) #include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" -#include "southbridge/amd/sb700/sb700_early_setup.c" #include <spd.h> void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c index a920cc840f..59dfc0351d 100644 --- a/src/mainboard/hp/dl145_g1/romstage.c +++ b/src/mainboard/hp/dl145_g1/romstage.c @@ -9,7 +9,7 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "southbridge/amd/amd8111/amd8111_early_smbus.c" +#include "southbridge/amd/amd8111/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" @@ -20,7 +20,7 @@ #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" +#include "southbridge/amd/amd8111/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index eeac3e5b6a..2687aea672 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -40,7 +40,7 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> -#include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c" +#include "southbridge/broadcom/bcm5785/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" @@ -53,7 +53,7 @@ #include "northbridge/amd/amdk8/debug.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c" +#include "southbridge/broadcom/bcm5785/early_setup.c" #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1) #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC) diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index ae9be8aeea..902be52dd3 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -39,7 +39,7 @@ #include "option_table.h" #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> -#include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c" +#include "southbridge/broadcom/bcm5785/early_smbus.c" #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" #include <lib.h> @@ -55,7 +55,7 @@ #include "northbridge/amd/amdfam10/debug.c" #include "cpu/x86/mtrr/earlymtrr.c" //#include "northbridge/amd/amdfam10/setup_resource_map.c" -#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c" +#include "southbridge/broadcom/bcm5785/early_setup.c" #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1) #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC) diff --git a/src/mainboard/ibase/mb899/acpi_tables.c b/src/mainboard/ibase/mb899/acpi_tables.c index f8009c3757..0089e2150a 100644 --- a/src/mainboard/ibase/mb899/acpi_tables.c +++ b/src/mainboard/ibase/mb899/acpi_tables.c @@ -35,7 +35,7 @@ extern const unsigned char AmlCode[]; unsigned long acpi_create_slic(unsigned long current); #endif -#include "southbridge/intel/i82801gx/i82801gx_nvs.h" +#include "southbridge/intel/i82801gx/nvs.h" static void acpi_create_gnvs(global_nvs_t *gnvs) { memset((void *)gnvs, 0, sizeof(*gnvs)); diff --git a/src/mainboard/ibase/mb899/mainboard_smi.c b/src/mainboard/ibase/mb899/mainboard_smi.c index 8516bdeba6..3e3bee7e6d 100644 --- a/src/mainboard/ibase/mb899/mainboard_smi.c +++ b/src/mainboard/ibase/mb899/mainboard_smi.c @@ -21,7 +21,7 @@ #include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> -#include "southbridge/intel/i82801gx/i82801gx_nvs.h" +#include "southbridge/intel/i82801gx/nvs.h" /* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler diff --git a/src/mainboard/ibm/e325/romstage.c b/src/mainboard/ibm/e325/romstage.c index 83f04c06b4..590565e4cf 100644 --- a/src/mainboard/ibm/e325/romstage.c +++ b/src/mainboard/ibm/e325/romstage.c @@ -10,7 +10,7 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "southbridge/amd/amd8111/amd8111_early_smbus.c" +#include "southbridge/amd/amd8111/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" @@ -22,7 +22,7 @@ #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include <spd.h> -#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" +#include "southbridge/amd/amd8111/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1) diff --git a/src/mainboard/ibm/e326/romstage.c b/src/mainboard/ibm/e326/romstage.c index 68e6291878..5adc8fb22b 100644 --- a/src/mainboard/ibm/e326/romstage.c +++ b/src/mainboard/ibm/e326/romstage.c @@ -10,7 +10,7 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "southbridge/amd/amd8111/amd8111_early_smbus.c" +#include "southbridge/amd/amd8111/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" @@ -21,7 +21,7 @@ #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" +#include "southbridge/amd/amd8111/early_ctrl.c" #include <spd.h> #define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1) diff --git a/src/mainboard/iei/juki-511p/romstage.c b/src/mainboard/iei/juki-511p/romstage.c index a5019ce095..54ada03b5d 100644 --- a/src/mainboard/iei/juki-511p/romstage.c +++ b/src/mainboard/iei/juki-511p/romstage.c @@ -26,7 +26,7 @@ #include <arch/hlt.h> #include <console/console.h> #include "superio/winbond/w83977f/w83977f_early_serial.c" -#include "southbridge/amd/cs5530/cs5530_enable_rom.c" +#include "southbridge/amd/cs5530/enable_rom.c" #include "cpu/x86/bist.h" #include "pc80/udelay_io.c" #include "northbridge/amd/gx1/raminit.c" diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index 86da8f6c87..0473d5f92b 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -47,8 +47,8 @@ #include "cpu/x86/mtrr/earlymtrr.c" #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" -#include "southbridge/amd/rs780/rs780_early_setup.c" -#include "southbridge/amd/sb700/sb700_early_setup.c" +#include "southbridge/amd/rs780/early_setup.c" +#include "southbridge/amd/sb700/early_setup.c" #include "northbridge/amd/amdfam10/debug.c" #define SERIAL_DEV PNP_DEV(0x2e, F71859_SP1) @@ -70,7 +70,6 @@ static int spd_read_byte(u32 device, u32 address) #include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" -#include "southbridge/amd/sb700/sb700_early_setup.c" #include <spd.h> void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) diff --git a/src/mainboard/iei/nova4899r/romstage.c b/src/mainboard/iei/nova4899r/romstage.c index 1d99197293..50b114e185 100644 --- a/src/mainboard/iei/nova4899r/romstage.c +++ b/src/mainboard/iei/nova4899r/romstage.c @@ -26,7 +26,7 @@ #include <arch/hlt.h> #include <console/console.h> #include "superio/winbond/w83977tf/w83977tf_early_serial.c" -#include "southbridge/amd/cs5530/cs5530_enable_rom.c" +#include "southbridge/amd/cs5530/enable_rom.c" #include "cpu/x86/bist.h" #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) diff --git a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c index 0c06fd2432..d011ed13dc 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c +++ b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c @@ -31,8 +31,8 @@ #include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> -#include "southbridge/amd/cs5536/cs5536_early_smbus.c" -#include "southbridge/amd/cs5536/cs5536_early_setup.c" +#include "southbridge/amd/cs5536/early_smbus.c" +#include "southbridge/amd/cs5536/early_setup.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/intel/d945gclf/acpi_tables.c b/src/mainboard/intel/d945gclf/acpi_tables.c index 9fc2adbc7c..1e8ea292fc 100644 --- a/src/mainboard/intel/d945gclf/acpi_tables.c +++ b/src/mainboard/intel/d945gclf/acpi_tables.c @@ -66,7 +66,7 @@ typedef struct acpi_oemb { } __attribute__((packed)) acpi_oemb_t; #endif -#include "southbridge/intel/i82801gx/i82801gx_nvs.h" +#include "southbridge/intel/i82801gx/nvs.h" #if OLD_ACPI static void acpi_create_oemb(acpi_oemb_t *oemb) diff --git a/src/mainboard/intel/d945gclf/mainboard_smi.c b/src/mainboard/intel/d945gclf/mainboard_smi.c index 8dff64e8fa..dbd1a81a64 100644 --- a/src/mainboard/intel/d945gclf/mainboard_smi.c +++ b/src/mainboard/intel/d945gclf/mainboard_smi.c @@ -21,7 +21,7 @@ #include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> -#include "southbridge/intel/i82801gx/i82801gx_nvs.h" +#include "southbridge/intel/i82801gx/nvs.h" /* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c index 8f8cd0f00f..e91fcd052d 100644 --- a/src/mainboard/intel/eagleheights/romstage.c +++ b/src/mainboard/intel/eagleheights/romstage.c @@ -31,8 +31,8 @@ #include <console/console.h> #include <cpu/x86/bist.h> #include <cpu/intel/acpi.h> -#include "southbridge/intel/i3100/i3100_early_smbus.c" -#include "southbridge/intel/i3100/i3100_early_lpc.c" +#include "southbridge/intel/i3100/early_smbus.c" +#include "southbridge/intel/i3100/early_lpc.c" #include "reset.c" #include "superio/intel/i3100/i3100_early_serial.c" #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" diff --git a/src/mainboard/intel/jarrell/romstage.c b/src/mainboard/intel/jarrell/romstage.c index e3ab67940e..8ce1cd24da 100644 --- a/src/mainboard/intel/jarrell/romstage.c +++ b/src/mainboard/intel/jarrell/romstage.c @@ -6,7 +6,7 @@ #include <cpu/x86/lapic.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" +#include "southbridge/intel/i82801ex/early_smbus.c" #include "northbridge/intel/e7520/raminit.h" #include "superio/nsc/pc87427/pc87427.h" #include "cpu/x86/lapic/boot_cpu.c" diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c index 856c69950d..e397eaefb7 100644 --- a/src/mainboard/intel/mtarvon/romstage.c +++ b/src/mainboard/intel/mtarvon/romstage.c @@ -27,8 +27,8 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "southbridge/intel/i3100/i3100_early_smbus.c" -#include "southbridge/intel/i3100/i3100_early_lpc.c" +#include "southbridge/intel/i3100/early_smbus.c" +#include "southbridge/intel/i3100/early_lpc.c" #include "northbridge/intel/i3100/raminit.h" #include "superio/intel/i3100/i3100.h" #include "cpu/x86/mtrr/earlymtrr.c" diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c index d6ee7c582f..6d29c57c75 100644 --- a/src/mainboard/intel/truxton/romstage.c +++ b/src/mainboard/intel/truxton/romstage.c @@ -28,8 +28,8 @@ #include <pc80/mc146818rtc.h> #include "pc80/udelay_io.c" #include <console/console.h> -#include "southbridge/intel/i3100/i3100_early_smbus.c" -#include "southbridge/intel/i3100/i3100_early_lpc.c" +#include "southbridge/intel/i3100/early_smbus.c" +#include "southbridge/intel/i3100/early_lpc.c" #include "northbridge/intel/i3100/raminit_ep80579.h" #include "superio/intel/i3100/i3100.h" #include "cpu/x86/lapic/boot_cpu.c" diff --git a/src/mainboard/intel/xe7501devkit/romstage.c b/src/mainboard/intel/xe7501devkit/romstage.c index e6fb83f4a6..d594091752 100644 --- a/src/mainboard/intel/xe7501devkit/romstage.c +++ b/src/mainboard/intel/xe7501devkit/romstage.c @@ -8,7 +8,7 @@ #include <stdlib.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "southbridge/intel/i82801cx/i82801cx_early_smbus.c" +#include "southbridge/intel/i82801cx/early_smbus.c" #include "northbridge/intel/e7501/raminit.h" #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/intel/e7501/debug.c" diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c index 582fed392b..3a420c03ff 100644 --- a/src/mainboard/iwill/dk8_htx/romstage.c +++ b/src/mainboard/iwill/dk8_htx/romstage.c @@ -13,7 +13,7 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> -#include "southbridge/amd/amd8111/amd8111_early_smbus.c" +#include "southbridge/amd/amd8111/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "cpu/x86/lapic/boot_cpu.c" @@ -24,7 +24,7 @@ #include "cpu/x86/mtrr/earlymtrr.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" +#include "southbridge/amd/amd8111/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c index 01e747eb94..8181abc200 100644 --- a/src/mainboard/iwill/dk8s2/romstage.c +++ b/src/mainboard/iwill/dk8s2/romstage.c @@ -13,7 +13,7 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> -#include "southbridge/amd/amd8111/amd8111_early_smbus.c" +#include "southbridge/amd/amd8111/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "cpu/x86/lapic/boot_cpu.c" @@ -24,7 +24,7 @@ #include "cpu/x86/mtrr/earlymtrr.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" +#include "southbridge/amd/amd8111/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c index 7b2db33d38..0701234ee5 100644 --- a/src/mainboard/iwill/dk8x/romstage.c +++ b/src/mainboard/iwill/dk8x/romstage.c @@ -13,7 +13,7 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> -#include "southbridge/amd/amd8111/amd8111_early_smbus.c" +#include "southbridge/amd/amd8111/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "cpu/x86/lapic/boot_cpu.c" @@ -24,7 +24,7 @@ #include "cpu/x86/mtrr/earlymtrr.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" +#include "southbridge/amd/amd8111/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/jetway/j7f24/romstage.c b/src/mainboard/jetway/j7f24/romstage.c index b0c14968b9..401fe67617 100644 --- a/src/mainboard/jetway/j7f24/romstage.c +++ b/src/mainboard/jetway/j7f24/romstage.c @@ -31,7 +31,7 @@ #include "cpu/x86/bist.h" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "southbridge/via/vt8237r/vt8237r_early_smbus.c" +#include "southbridge/via/vt8237r/early_smbus.c" #include "superio/fintek/f71805f/f71805f_early_serial.c" #include <lib.h> #include <spd.h> diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 4711aecfdd..b5b9ab3d4b 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -48,8 +48,8 @@ #include "cpu/x86/mtrr/earlymtrr.c" #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" -#include "southbridge/amd/rs780/rs780_early_setup.c" -#include "southbridge/amd/sb700/sb700_early_setup.c" +#include "southbridge/amd/rs780/early_setup.c" +#include "southbridge/amd/sb700/early_setup.c" #include "northbridge/amd/amdfam10/debug.c" #if CONFIG_TTYS0_BASE == 0x2f8 @@ -75,7 +75,6 @@ static int spd_read_byte(u32 device, u32 address) #include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" -#include "southbridge/amd/sb700/sb700_early_setup.c" #include <spd.h> void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) diff --git a/src/mainboard/kontron/986lcd-m/acpi_tables.c b/src/mainboard/kontron/986lcd-m/acpi_tables.c index f8009c3757..0089e2150a 100644 --- a/src/mainboard/kontron/986lcd-m/acpi_tables.c +++ b/src/mainboard/kontron/986lcd-m/acpi_tables.c @@ -35,7 +35,7 @@ extern const unsigned char AmlCode[]; unsigned long acpi_create_slic(unsigned long current); #endif -#include "southbridge/intel/i82801gx/i82801gx_nvs.h" +#include "southbridge/intel/i82801gx/nvs.h" static void acpi_create_gnvs(global_nvs_t *gnvs) { memset((void *)gnvs, 0, sizeof(*gnvs)); diff --git a/src/mainboard/kontron/986lcd-m/mainboard_smi.c b/src/mainboard/kontron/986lcd-m/mainboard_smi.c index 8516bdeba6..3e3bee7e6d 100644 --- a/src/mainboard/kontron/986lcd-m/mainboard_smi.c +++ b/src/mainboard/kontron/986lcd-m/mainboard_smi.c @@ -21,7 +21,7 @@ #include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> -#include "southbridge/intel/i82801gx/i82801gx_nvs.h" +#include "southbridge/intel/i82801gx/nvs.h" /* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c index 16c8b0b455..6c9e3ef345 100644 --- a/src/mainboard/kontron/kt690/romstage.c +++ b/src/mainboard/kontron/kt690/romstage.c @@ -45,8 +45,8 @@ #include <cpu/amd/mtrr.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/amd/rs690/rs690_early_setup.c" -#include "southbridge/amd/sb600/sb600_early_setup.c" +#include "southbridge/amd/rs690/early_setup.c" +#include "southbridge/amd/sb600/early_setup.c" static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } diff --git a/src/mainboard/lanner/em8510/romstage.c b/src/mainboard/lanner/em8510/romstage.c index 5406b7d05f..ba7a2959de 100644 --- a/src/mainboard/lanner/em8510/romstage.c +++ b/src/mainboard/lanner/em8510/romstage.c @@ -33,7 +33,7 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include "southbridge/intel/i82801dx/i82801dx.h" -#include "southbridge/intel/i82801dx/i82801dx_early_smbus.c" +#include "southbridge/intel/i82801dx/early_smbus.c" #include "northbridge/intel/i855/raminit.h" #include "northbridge/intel/i855/debug.c" #include "superio/winbond/w83627thg/w83627thg_early_serial.c" diff --git a/src/mainboard/lippert/frontrunner/romstage.c b/src/mainboard/lippert/frontrunner/romstage.c index 0abdde4372..f96b93bb60 100644 --- a/src/mainboard/lippert/frontrunner/romstage.c +++ b/src/mainboard/lippert/frontrunner/romstage.c @@ -11,8 +11,8 @@ #include <cpu/amd/gx2def.h> #include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5535/cs5535.h" -#include "southbridge/amd/cs5535/cs5535_early_smbus.c" -#include "southbridge/amd/cs5535/cs5535_early_setup.c" +#include "southbridge/amd/cs5535/early_smbus.c" +#include "southbridge/amd/cs5535/early_setup.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/lippert/hurricane-lx/romstage.c b/src/mainboard/lippert/hurricane-lx/romstage.c index 35f8fe5c31..1a56251557 100644 --- a/src/mainboard/lippert/hurricane-lx/romstage.c +++ b/src/mainboard/lippert/hurricane-lx/romstage.c @@ -34,8 +34,8 @@ #include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> -#include "southbridge/amd/cs5536/cs5536_early_smbus.c" -#include "southbridge/amd/cs5536/cs5536_early_setup.c" +#include "southbridge/amd/cs5536/early_smbus.c" +#include "southbridge/amd/cs5536/early_setup.c" #include "superio/ite/it8712f/it8712f_early_serial.c" /* Bit0 enables Spread Spectrum. */ diff --git a/src/mainboard/lippert/literunner-lx/romstage.c b/src/mainboard/lippert/literunner-lx/romstage.c index afe5bd7c09..aa89cac523 100644 --- a/src/mainboard/lippert/literunner-lx/romstage.c +++ b/src/mainboard/lippert/literunner-lx/romstage.c @@ -34,8 +34,8 @@ #include <cpu/amd/lxdef.h> #include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" -#include "southbridge/amd/cs5536/cs5536_early_smbus.c" -#include "southbridge/amd/cs5536/cs5536_early_setup.c" +#include "southbridge/amd/cs5536/early_smbus.c" +#include "southbridge/amd/cs5536/early_setup.c" #include "superio/ite/it8712f/it8712f_early_serial.c" /* Bit0 enables Spread Spectrum, bit1 makes on-board CF slot act as IDE slave. */ diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c index 32f3b3e304..331ba5dfe5 100644 --- a/src/mainboard/lippert/roadrunner-lx/romstage.c +++ b/src/mainboard/lippert/roadrunner-lx/romstage.c @@ -34,8 +34,8 @@ #include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> -#include "southbridge/amd/cs5536/cs5536_early_smbus.c" -#include "southbridge/amd/cs5536/cs5536_early_setup.c" +#include "southbridge/amd/cs5536/early_smbus.c" +#include "southbridge/amd/cs5536/early_setup.c" #include "superio/ite/it8712f/it8712f_early_serial.c" #define ManualConf 1 /* No automatic strapped PLL config */ diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c index 5f940e5661..462a2b5b9a 100644 --- a/src/mainboard/lippert/spacerunner-lx/romstage.c +++ b/src/mainboard/lippert/spacerunner-lx/romstage.c @@ -34,8 +34,8 @@ #include <cpu/amd/lxdef.h> #include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" -#include "southbridge/amd/cs5536/cs5536_early_smbus.c" -#include "southbridge/amd/cs5536/cs5536_early_setup.c" +#include "southbridge/amd/cs5536/early_smbus.c" +#include "southbridge/amd/cs5536/early_setup.c" #include "superio/ite/it8712f/it8712f_early_serial.c" /* Bit0 enables Spread Spectrum, bit1 makes on-board SSD act as IDE slave. */ diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c index c804b6c9fe..53d7e509f5 100644 --- a/src/mainboard/msi/ms7135/romstage.c +++ b/src/mainboard/msi/ms7135/romstage.c @@ -36,7 +36,7 @@ #include <cpu/amd/model_fxx_rev.h> #include <console/console.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "southbridge/nvidia/ck804/ck804_early_smbus.h" +#include "southbridge/nvidia/ck804/early_smbus.h" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" @@ -60,8 +60,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/raminit.c" #include "lib/generic_sdram.c" -#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h" -#include "southbridge/nvidia/ck804/ck804_early_setup_car.c" +#include "southbridge/nvidia/ck804/early_setup_ss.h" +#include "southbridge/nvidia/ck804/early_setup_car.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "northbridge/amd/amdk8/early_ht.c" diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index 4ec8cec9f2..e5b4b47fbe 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -36,7 +36,7 @@ #include <console/console.h> #include <usbdebug.h> #include <cpu/amd/model_fxx_rev.h> -#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" +#include "southbridge/nvidia/mcp55/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" @@ -50,7 +50,7 @@ #include "northbridge/amd/amdk8/debug.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" +#include "southbridge/nvidia/mcp55/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1) @@ -78,8 +78,8 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ -#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" -#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" +#include "southbridge/nvidia/mcp55/early_setup_ss.h" +#include "southbridge/nvidia/mcp55/early_setup_car.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index a27fec0118..ee2847b17e 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -34,7 +34,7 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> -#include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c" +#include "southbridge/broadcom/bcm5785/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" @@ -46,7 +46,7 @@ #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c" +#include "southbridge/broadcom/bcm5785/early_setup.c" #define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1) #define RTC_DEV PNP_DEV(0x2e, PC87417_RTC) diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index f5e9f265f3..599b8b60ca 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -32,7 +32,7 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> -#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" +#include "southbridge/nvidia/mcp55/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" @@ -45,7 +45,7 @@ #include <spd.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include <device/pci_ids.h> -#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" +#include "southbridge/nvidia/mcp55/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) @@ -82,7 +82,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" -#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" +#include "southbridge/nvidia/mcp55/early_setup_ss.h" //set GPIO to input mode #define MCP55_MB_SETUP \ @@ -91,7 +91,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \ -#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" +#include "southbridge/nvidia/mcp55/early_setup_car.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" // Disabled until it's actually used: diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 5c0c9ae31a..9150a832d3 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -35,7 +35,7 @@ #include <lib.h> #include <spd.h> #include <cpu/amd/model_10xxx_rev.h> -#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" +#include "southbridge/nvidia/mcp55/early_smbus.c" #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" #include "cpu/amd/model_fxx/apic_timer.c" @@ -47,7 +47,7 @@ #include "northbridge/amd/amdfam10/debug.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "northbridge/amd/amdfam10/setup_resource_map.c" -#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" +#include "southbridge/nvidia/mcp55/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) @@ -72,8 +72,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ -#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" -#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" +#include "southbridge/nvidia/mcp55/early_setup_ss.h" +#include "southbridge/nvidia/mcp55/early_setup_car.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" diff --git a/src/mainboard/newisys/khepri/romstage.c b/src/mainboard/newisys/khepri/romstage.c index b6ceed1037..1a6cdbc0a5 100644 --- a/src/mainboard/newisys/khepri/romstage.c +++ b/src/mainboard/newisys/khepri/romstage.c @@ -17,7 +17,7 @@ #include <spd.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "southbridge/amd/amd8111/amd8111_early_smbus.c" +#include "southbridge/amd/amd8111/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" @@ -28,7 +28,7 @@ #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" +#include "southbridge/amd/amd8111/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index 8e4067f1f0..508ea83bd0 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -37,7 +37,7 @@ #include <lib.h> #include <spd.h> #include <cpu/amd/model_fxx_rev.h> -#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" +#include "southbridge/nvidia/mcp55/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" @@ -49,7 +49,7 @@ #include "northbridge/amd/amdk8/debug.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" +#include "southbridge/nvidia/mcp55/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) @@ -77,8 +77,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ -#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" -#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" +#include "southbridge/nvidia/mcp55/early_setup_ss.h" +#include "southbridge/nvidia/mcp55/early_setup_car.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c index ed9324ea44..609baf6e5f 100644 --- a/src/mainboard/pcengines/alix1c/romstage.c +++ b/src/mainboard/pcengines/alix1c/romstage.c @@ -38,7 +38,7 @@ /* The ALIX1.C has no SMBus; the setup is hard-wired. */ static void cs5536_enable_smbus(void) { } -#include "southbridge/amd/cs5536/cs5536_early_setup.c" +#include "southbridge/amd/cs5536/early_setup.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" /* The part is a Hynix hy5du121622ctp-d43. diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c index ec77537113..1a0acf2386 100644 --- a/src/mainboard/pcengines/alix2d/romstage.c +++ b/src/mainboard/pcengines/alix2d/romstage.c @@ -38,7 +38,7 @@ /* The ALIX.2D has no SMBus; the setup is hard-wired. */ static void cs5536_enable_smbus(void) { } -#include "southbridge/amd/cs5536/cs5536_early_setup.c" +#include "southbridge/amd/cs5536/early_setup.c" /* The part is a Hynix hy5du121622ctp-d43. * diff --git a/src/mainboard/rca/rm4100/romstage.c b/src/mainboard/rca/rm4100/romstage.c index 1fb1440a1b..6df8d41f38 100644 --- a/src/mainboard/rca/rm4100/romstage.c +++ b/src/mainboard/rca/rm4100/romstage.c @@ -32,12 +32,12 @@ #include "northbridge/intel/i82830/raminit.h" #include "northbridge/intel/i82830/memory_initialized.c" #include "southbridge/intel/i82801dx/i82801dx.h" -#include "southbridge/intel/i82801dx/i82801dx_reset.c" +#include "southbridge/intel/i82801dx/reset.c" #include "cpu/x86/bist.h" #include "spd_table.h" #include "gpio.c" -#include "southbridge/intel/i82801dx/i82801dx_early_smbus.c" -#include "southbridge/intel/i82801dx/i82801dx_tco_timer.c" +#include "southbridge/intel/i82801dx/early_smbus.c" +#include "southbridge/intel/i82801dx/tco_timer.c" #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) diff --git a/src/mainboard/roda/rk886ex/acpi_tables.c b/src/mainboard/roda/rk886ex/acpi_tables.c index 2dd7c5ccf0..d9275b5ac0 100644 --- a/src/mainboard/roda/rk886ex/acpi_tables.c +++ b/src/mainboard/roda/rk886ex/acpi_tables.c @@ -91,7 +91,7 @@ static void acpi_create_gnvs(global_nvs_t *gnvs) } #endif -#include "southbridge/intel/i82801gx/i82801gx_nvs.h" +#include "southbridge/intel/i82801gx/nvs.h" static void acpi_create_gnvs(global_nvs_t *gnvs) { memset((void *)gnvs, 0, sizeof(*gnvs)); diff --git a/src/mainboard/roda/rk886ex/mainboard_smi.c b/src/mainboard/roda/rk886ex/mainboard_smi.c index 17783fe6e6..6736ace09a 100644 --- a/src/mainboard/roda/rk886ex/mainboard_smi.c +++ b/src/mainboard/roda/rk886ex/mainboard_smi.c @@ -23,7 +23,7 @@ #include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> -#include "southbridge/intel/i82801gx/i82801gx_nvs.h" +#include "southbridge/intel/i82801gx/nvs.h" /* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c index ceac91ddfb..21d50469d7 100644 --- a/src/mainboard/sunw/ultra40/romstage.c +++ b/src/mainboard/sunw/ultra40/romstage.c @@ -11,7 +11,7 @@ #include <spd.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "southbridge/nvidia/ck804/ck804_early_smbus.h" +#include "southbridge/nvidia/ck804/early_smbus.h" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" @@ -54,7 +54,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" -#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h" +#include "southbridge/nvidia/ck804/early_setup_ss.h" //set GPIO to input mode #define CK804_MB_SETUP \ @@ -65,7 +65,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ -#include "southbridge/nvidia/ck804/ck804_early_setup_car.c" +#include "southbridge/nvidia/ck804/early_setup_car.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "northbridge/amd/amdk8/early_ht.c" diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index ff7b24f40e..8ba4f2604c 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -33,7 +33,7 @@ #include <lib.h> #include <spd.h> #include <cpu/amd/model_fxx_rev.h> -#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" // for enable the FAN +#include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" @@ -45,7 +45,7 @@ #include "northbridge/amd/amdk8/debug.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" +#include "southbridge/nvidia/mcp55/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define DUMMY_DEV PNP_DEV(0x2e, 0) @@ -127,8 +127,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" -#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" -#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" +#include "southbridge/nvidia/mcp55/early_setup_ss.h" +#include "southbridge/nvidia/mcp55/early_setup_car.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index e7875956b2..65517ec31e 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -36,7 +36,7 @@ #include <lib.h> #include <spd.h> #include <cpu/amd/model_fxx_rev.h> -#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" // for enable the FAN +#include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" @@ -48,7 +48,7 @@ #include "northbridge/amd/amdk8/debug.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" +#include "southbridge/nvidia/mcp55/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define DUMMY_DEV PNP_DEV(0x2e, 0) @@ -68,8 +68,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" -#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" -#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" +#include "southbridge/nvidia/mcp55/early_setup_ss.h" +#include "southbridge/nvidia/mcp55/early_setup_car.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index 966ae3b694..90f0d93a37 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -34,7 +34,7 @@ #include <lib.h> #include <spd.h> #include <cpu/amd/model_10xxx_rev.h> -#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" // for enable the FAN +#include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" #include "cpu/amd/model_10xxx/apic_timer.c" @@ -47,7 +47,7 @@ #include "northbridge/amd/amdfam10/debug.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "northbridge/amd/amdfam10/setup_resource_map.c" -#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" +#include "southbridge/nvidia/mcp55/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define DUMMY_DEV PNP_DEV(0x2e, 0) @@ -64,8 +64,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdfam10/amdfam10_pci.c" #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" -#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" -#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" +#include "southbridge/nvidia/mcp55/early_setup_ss.h" +#include "southbridge/nvidia/mcp55/early_setup_car.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index d60350935d..e6591d90d6 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -34,7 +34,7 @@ #include <lib.h> #include <spd.h> #include <cpu/amd/model_10xxx_rev.h> -#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" // for enable the FAN +#include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" #include "cpu/amd/model_10xxx/apic_timer.c" @@ -47,7 +47,7 @@ #include "northbridge/amd/amdfam10/debug.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "northbridge/amd/amdfam10/setup_resource_map.c" -#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" +#include "southbridge/nvidia/mcp55/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define DUMMY_DEV PNP_DEV(0x2e, 0) @@ -70,8 +70,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdfam10/amdfam10_pci.c" #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" -#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" -#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" +#include "southbridge/nvidia/mcp55/early_setup_ss.h" +#include "southbridge/nvidia/mcp55/early_setup_car.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" diff --git a/src/mainboard/supermicro/x6dai_g/romstage.c b/src/mainboard/supermicro/x6dai_g/romstage.c index 09e52873c1..8815d19f98 100644 --- a/src/mainboard/supermicro/x6dai_g/romstage.c +++ b/src/mainboard/supermicro/x6dai_g/romstage.c @@ -8,7 +8,7 @@ #include <console/console.h> #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "southbridge/intel/esb6300/esb6300_early_smbus.c" +#include "southbridge/intel/esb6300/early_smbus.c" #include "northbridge/intel/e7525/raminit.h" #include "superio/winbond/w83627hf/w83627hf.h" #include "cpu/x86/lapic/boot_cpu.c" diff --git a/src/mainboard/supermicro/x6dhe_g/romstage.c b/src/mainboard/supermicro/x6dhe_g/romstage.c index b6ae4df626..74e1bd8593 100644 --- a/src/mainboard/supermicro/x6dhe_g/romstage.c +++ b/src/mainboard/supermicro/x6dhe_g/romstage.c @@ -8,7 +8,7 @@ #include <console/console.h> #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "southbridge/intel/esb6300/esb6300_early_smbus.c" +#include "southbridge/intel/esb6300/early_smbus.c" #include "northbridge/intel/e7520/raminit.h" #include "superio/winbond/w83627hf/w83627hf.h" #include "cpu/x86/lapic/boot_cpu.c" diff --git a/src/mainboard/supermicro/x6dhe_g2/romstage.c b/src/mainboard/supermicro/x6dhe_g2/romstage.c index bf2762e8c0..72e3b9da5b 100644 --- a/src/mainboard/supermicro/x6dhe_g2/romstage.c +++ b/src/mainboard/supermicro/x6dhe_g2/romstage.c @@ -6,7 +6,7 @@ #include <cpu/x86/lapic.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" +#include "southbridge/intel/i82801ex/early_smbus.c" #include "northbridge/intel/e7520/raminit.h" #include "superio/nsc/pc87427/pc87427.h" #include "cpu/x86/lapic/boot_cpu.c" diff --git a/src/mainboard/supermicro/x6dhr_ig/romstage.c b/src/mainboard/supermicro/x6dhr_ig/romstage.c index 102ef8ead6..f37d565b20 100644 --- a/src/mainboard/supermicro/x6dhr_ig/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig/romstage.c @@ -6,7 +6,7 @@ #include <cpu/x86/lapic.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" +#include "southbridge/intel/i82801ex/early_smbus.c" #include "northbridge/intel/e7520/raminit.h" #include "superio/winbond/w83627hf/w83627hf.h" #include "cpu/x86/lapic/boot_cpu.c" diff --git a/src/mainboard/supermicro/x6dhr_ig2/romstage.c b/src/mainboard/supermicro/x6dhr_ig2/romstage.c index 44b9ae092d..166d56c0f1 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig2/romstage.c @@ -6,7 +6,7 @@ #include <cpu/x86/lapic.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" +#include "southbridge/intel/i82801ex/early_smbus.c" #include "northbridge/intel/e7520/raminit.h" #include "superio/winbond/w83627hf/w83627hf.h" #include "cpu/x86/lapic/boot_cpu.c" diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c index f9f1e70ce1..7f72a32a89 100644 --- a/src/mainboard/technexion/tim5690/romstage.c +++ b/src/mainboard/technexion/tim5690/romstage.c @@ -44,8 +44,8 @@ #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/amd/rs690/rs690_early_setup.c" -#include "southbridge/amd/sb600/sb600_early_setup.c" +#include "southbridge/amd/rs690/early_setup.c" +#include "southbridge/amd/sb600/early_setup.c" static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c index 276ca08682..490eaa5481 100644 --- a/src/mainboard/technexion/tim8690/romstage.c +++ b/src/mainboard/technexion/tim8690/romstage.c @@ -44,8 +44,8 @@ #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/amd/rs690/rs690_early_setup.c" -#include "southbridge/amd/sb600/sb600_early_setup.c" +#include "southbridge/amd/rs690/early_setup.c" +#include "southbridge/amd/sb600/early_setup.c" static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } diff --git a/src/mainboard/televideo/tc7020/romstage.c b/src/mainboard/televideo/tc7020/romstage.c index f5eeab3c29..c79f42d9f0 100644 --- a/src/mainboard/televideo/tc7020/romstage.c +++ b/src/mainboard/televideo/tc7020/romstage.c @@ -28,7 +28,7 @@ #include "northbridge/amd/gx1/raminit.c" #include "superio/nsc/pc97317/pc97317_early_serial.c" #include "cpu/x86/bist.h" -#include "southbridge/amd/cs5530/cs5530_enable_rom.c" +#include "southbridge/amd/cs5530/enable_rom.c" #define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1) diff --git a/src/mainboard/thomson/ip1000/romstage.c b/src/mainboard/thomson/ip1000/romstage.c index c9ec8a80b2..047d704073 100644 --- a/src/mainboard/thomson/ip1000/romstage.c +++ b/src/mainboard/thomson/ip1000/romstage.c @@ -33,12 +33,12 @@ #include "northbridge/intel/i82830/raminit.h" #include "northbridge/intel/i82830/memory_initialized.c" #include "southbridge/intel/i82801dx/i82801dx.h" -#include "southbridge/intel/i82801dx/i82801dx_reset.c" +#include "southbridge/intel/i82801dx/reset.c" #include "cpu/x86/bist.h" #include "spd_table.h" #include "gpio.c" -#include "southbridge/intel/i82801dx/i82801dx_early_smbus.c" -#include "southbridge/intel/i82801dx/i82801dx_tco_timer.c" +#include "southbridge/intel/i82801dx/early_smbus.c" +#include "southbridge/intel/i82801dx/tco_timer.c" #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) diff --git a/src/mainboard/traverse/geos/romstage.c b/src/mainboard/traverse/geos/romstage.c index 3e4ffb5c4c..07962d33fd 100644 --- a/src/mainboard/traverse/geos/romstage.c +++ b/src/mainboard/traverse/geos/romstage.c @@ -32,8 +32,8 @@ #include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> -#include "southbridge/amd/cs5536/cs5536_early_smbus.c" -#include "southbridge/amd/cs5536/cs5536_early_setup.c" +#include "southbridge/amd/cs5536/early_smbus.c" +#include "southbridge/amd/cs5536/early_setup.c" static inline int spd_read_byte(unsigned int device, unsigned int address) { diff --git a/src/mainboard/tyan/s2735/romstage.c b/src/mainboard/tyan/s2735/romstage.c index c7c5eb036a..eaddf9a290 100644 --- a/src/mainboard/tyan/s2735/romstage.c +++ b/src/mainboard/tyan/s2735/romstage.c @@ -9,7 +9,7 @@ #include <console/console.h> #include <lib.h> #include <spd.h> -#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" +#include "southbridge/intel/i82801ex/early_smbus.c" #include "northbridge/intel/e7501/raminit.h" #include "northbridge/intel/e7501/debug.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" diff --git a/src/mainboard/tyan/s2850/romstage.c b/src/mainboard/tyan/s2850/romstage.c index b7f0716796..a45d6dfa1c 100644 --- a/src/mainboard/tyan/s2850/romstage.c +++ b/src/mainboard/tyan/s2850/romstage.c @@ -12,7 +12,7 @@ #include <spd.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "southbridge/amd/amd8111/amd8111_early_smbus.c" +#include "southbridge/amd/amd8111/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" @@ -23,7 +23,7 @@ #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" +#include "southbridge/amd/amd8111/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/tyan/s2875/romstage.c b/src/mainboard/tyan/s2875/romstage.c index db54927e9b..7681e88f31 100644 --- a/src/mainboard/tyan/s2875/romstage.c +++ b/src/mainboard/tyan/s2875/romstage.c @@ -12,7 +12,7 @@ #include <spd.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "southbridge/amd/amd8111/amd8111_early_smbus.c" +#include "southbridge/amd/amd8111/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" @@ -23,7 +23,7 @@ #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" +#include "southbridge/amd/amd8111/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/tyan/s2880/romstage.c b/src/mainboard/tyan/s2880/romstage.c index 2ab663b0d1..a1312659f8 100644 --- a/src/mainboard/tyan/s2880/romstage.c +++ b/src/mainboard/tyan/s2880/romstage.c @@ -12,7 +12,7 @@ #include <spd.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "southbridge/amd/amd8111/amd8111_early_smbus.c" +#include "southbridge/amd/amd8111/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" @@ -23,7 +23,7 @@ #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" +#include "southbridge/amd/amd8111/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/tyan/s2881/romstage.c b/src/mainboard/tyan/s2881/romstage.c index 6645c9de24..22f24bbd18 100644 --- a/src/mainboard/tyan/s2881/romstage.c +++ b/src/mainboard/tyan/s2881/romstage.c @@ -11,7 +11,7 @@ #include <spd.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "southbridge/amd/amd8111/amd8111_early_smbus.c" +#include "southbridge/amd/amd8111/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" @@ -22,7 +22,7 @@ #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" +#include "southbridge/amd/amd8111/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/tyan/s2882/romstage.c b/src/mainboard/tyan/s2882/romstage.c index 2ab663b0d1..a1312659f8 100644 --- a/src/mainboard/tyan/s2882/romstage.c +++ b/src/mainboard/tyan/s2882/romstage.c @@ -12,7 +12,7 @@ #include <spd.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "southbridge/amd/amd8111/amd8111_early_smbus.c" +#include "southbridge/amd/amd8111/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" @@ -23,7 +23,7 @@ #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" +#include "southbridge/amd/amd8111/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/tyan/s2885/romstage.c b/src/mainboard/tyan/s2885/romstage.c index a4b7d076d1..963ba1b7ef 100644 --- a/src/mainboard/tyan/s2885/romstage.c +++ b/src/mainboard/tyan/s2885/romstage.c @@ -11,7 +11,7 @@ #include <spd.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "southbridge/amd/amd8111/amd8111_early_smbus.c" +#include "southbridge/amd/amd8111/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" @@ -22,7 +22,7 @@ #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" +#include "southbridge/amd/amd8111/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/tyan/s2891/romstage.c b/src/mainboard/tyan/s2891/romstage.c index 39bdc65e7e..c059592e8d 100644 --- a/src/mainboard/tyan/s2891/romstage.c +++ b/src/mainboard/tyan/s2891/romstage.c @@ -11,7 +11,7 @@ #include <spd.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "southbridge/nvidia/ck804/ck804_early_smbus.h" +#include "southbridge/nvidia/ck804/early_smbus.h" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" @@ -39,8 +39,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" -#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h" -#include "southbridge/nvidia/ck804/ck804_early_setup.c" +#include "southbridge/nvidia/ck804/early_setup_ss.h" +#include "southbridge/nvidia/ck804/early_setup.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "northbridge/amd/amdk8/early_ht.c" diff --git a/src/mainboard/tyan/s2892/romstage.c b/src/mainboard/tyan/s2892/romstage.c index 2ab6d32090..820e05ff96 100644 --- a/src/mainboard/tyan/s2892/romstage.c +++ b/src/mainboard/tyan/s2892/romstage.c @@ -11,7 +11,7 @@ #include <spd.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "southbridge/nvidia/ck804/ck804_early_smbus.h" +#include "southbridge/nvidia/ck804/early_smbus.h" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" @@ -38,7 +38,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" -#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h" +#include "southbridge/nvidia/ck804/early_setup_ss.h" //set GPIO to input mode #define CK804_MB_SETUP \ @@ -47,7 +47,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \ -#include "southbridge/nvidia/ck804/ck804_early_setup_car.c" +#include "southbridge/nvidia/ck804/early_setup_car.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "northbridge/amd/amdk8/early_ht.c" diff --git a/src/mainboard/tyan/s2895/romstage.c b/src/mainboard/tyan/s2895/romstage.c index 7a6fcbc3a7..db534f021f 100644 --- a/src/mainboard/tyan/s2895/romstage.c +++ b/src/mainboard/tyan/s2895/romstage.c @@ -11,7 +11,7 @@ #include <spd.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "southbridge/nvidia/ck804/ck804_early_smbus.h" +#include "southbridge/nvidia/ck804/early_smbus.h" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" @@ -54,7 +54,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" -#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h" +#include "southbridge/nvidia/ck804/early_setup_ss.h" //set GPIO to input mode #define CK804_MB_SETUP \ @@ -65,7 +65,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ -#include "southbridge/nvidia/ck804/ck804_early_setup_car.c" +#include "southbridge/nvidia/ck804/early_setup_car.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "northbridge/amd/amdk8/early_ht.c" diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c index 0dd7297ea2..aa6107637d 100644 --- a/src/mainboard/tyan/s2912/romstage.c +++ b/src/mainboard/tyan/s2912/romstage.c @@ -37,7 +37,7 @@ #include <spd.h> #include <usbdebug.h> #include <cpu/amd/model_fxx_rev.h> -#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" +#include "southbridge/nvidia/mcp55/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" @@ -49,7 +49,7 @@ #include "northbridge/amd/amdk8/debug.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" +#include "southbridge/nvidia/mcp55/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -77,8 +77,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ -#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" -#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" +#include "southbridge/nvidia/mcp55/early_setup_ss.h" +#include "southbridge/nvidia/mcp55/early_setup_car.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index d5d2c4129b..c9c8561030 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -35,7 +35,7 @@ #include <lib.h> #include <spd.h> #include <cpu/amd/model_10xxx_rev.h> -#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" +#include "southbridge/nvidia/mcp55/early_smbus.c" #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" #include "cpu/amd/model_10xxx/apic_timer.c" @@ -48,7 +48,7 @@ #include "northbridge/amd/amdfam10/debug.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "northbridge/amd/amdfam10/setup_resource_map.c" -#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" +#include "southbridge/nvidia/mcp55/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -73,8 +73,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ -#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" -#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" +#include "southbridge/nvidia/mcp55/early_setup_ss.h" +#include "southbridge/nvidia/mcp55/early_setup_car.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" diff --git a/src/mainboard/tyan/s4880/romstage.c b/src/mainboard/tyan/s4880/romstage.c index cfa061313f..6e480699db 100644 --- a/src/mainboard/tyan/s4880/romstage.c +++ b/src/mainboard/tyan/s4880/romstage.c @@ -11,7 +11,7 @@ #include <lib.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "southbridge/amd/amd8111/amd8111_early_smbus.c" +#include "southbridge/amd/amd8111/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" @@ -22,7 +22,7 @@ #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" +#include "southbridge/amd/amd8111/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/tyan/s4882/romstage.c b/src/mainboard/tyan/s4882/romstage.c index d83c21a893..c21388f545 100644 --- a/src/mainboard/tyan/s4882/romstage.c +++ b/src/mainboard/tyan/s4882/romstage.c @@ -10,7 +10,7 @@ #include <lib.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "southbridge/amd/amd8111/amd8111_early_smbus.c" +#include "southbridge/amd/amd8111/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" @@ -21,7 +21,7 @@ #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" +#include "southbridge/amd/amd8111/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/via/epia-cn/romstage.c b/src/mainboard/via/epia-cn/romstage.c index 20b4c05675..66b607b908 100644 --- a/src/mainboard/via/epia-cn/romstage.c +++ b/src/mainboard/via/epia-cn/romstage.c @@ -32,8 +32,8 @@ #include "cpu/x86/bist.h" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "southbridge/via/vt8237r/vt8237r_early_smbus.c" -#include "southbridge/via/vt8235/vt8235_early_serial.c" +#include "southbridge/via/vt8237r/early_smbus.c" +#include "southbridge/via/vt8235/early_serial.c" #include <spd.h> static inline int spd_read_byte(unsigned device, unsigned address) diff --git a/src/mainboard/via/epia-m/romstage.c b/src/mainboard/via/epia-m/romstage.c index 2d887b3f92..b22719cedc 100644 --- a/src/mainboard/via/epia-m/romstage.c +++ b/src/mainboard/via/epia-m/romstage.c @@ -14,8 +14,8 @@ #include "lib/delay.c" #include "cpu/x86/lapic/boot_cpu.c" #include "lib/debug.c" -#include "southbridge/via/vt8235/vt8235_early_smbus.c" -#include "southbridge/via/vt8235/vt8235_early_serial.c" +#include "southbridge/via/vt8235/early_smbus.c" +#include "southbridge/via/vt8235/early_serial.c" static inline int spd_read_byte(unsigned device, unsigned address) { diff --git a/src/mainboard/via/epia-n/romstage.c b/src/mainboard/via/epia-n/romstage.c index 22e12cb678..aa35858224 100644 --- a/src/mainboard/via/epia-n/romstage.c +++ b/src/mainboard/via/epia-n/romstage.c @@ -33,7 +33,7 @@ #include "pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/lapic/boot_cpu.c" -#include "southbridge/via/vt8237r/vt8237r_early_smbus.c" +#include "southbridge/via/vt8237r/early_smbus.c" #include "superio/winbond/w83697hf/w83697hf_early_serial.c" #include <spd.h> diff --git a/src/mainboard/via/epia/romstage.c b/src/mainboard/via/epia/romstage.c index 870c4e7630..9d9a3f9a9a 100644 --- a/src/mainboard/via/epia/romstage.c +++ b/src/mainboard/via/epia/romstage.c @@ -12,9 +12,9 @@ #include "pc80/udelay_io.c" #include "lib/delay.c" #include "lib/debug.c" -#include "southbridge/via/vt8231/vt8231_early_smbus.c" -#include "southbridge/via/vt8231/vt8231_early_serial.c" -#include "southbridge/via/vt8231/vt8231_enable_rom.c" +#include "southbridge/via/vt8231/early_smbus.c" +#include "southbridge/via/vt8231/early_serial.c" +#include "southbridge/via/vt8231/enable_rom.c" static inline int spd_read_byte(unsigned device, unsigned address) { diff --git a/src/mainboard/via/pc2500e/romstage.c b/src/mainboard/via/pc2500e/romstage.c index 2b653f79d2..0fded96d0c 100644 --- a/src/mainboard/via/pc2500e/romstage.c +++ b/src/mainboard/via/pc2500e/romstage.c @@ -32,7 +32,7 @@ #include "cpu/x86/bist.h" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "southbridge/via/vt8237r/vt8237r_early_smbus.c" +#include "southbridge/via/vt8237r/early_smbus.c" #include "superio/ite/it8716f/it8716f_early_serial.c" #include <spd.h> diff --git a/src/mainboard/winent/pl6064/romstage.c b/src/mainboard/winent/pl6064/romstage.c index cd615efa4b..318b560fba 100644 --- a/src/mainboard/winent/pl6064/romstage.c +++ b/src/mainboard/winent/pl6064/romstage.c @@ -33,8 +33,8 @@ #include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> -#include "southbridge/amd/cs5536/cs5536_early_smbus.c" -#include "southbridge/amd/cs5536/cs5536_early_setup.c" +#include "southbridge/amd/cs5536/early_smbus.c" +#include "southbridge/amd/cs5536/early_setup.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/wyse/s50/romstage.c b/src/mainboard/wyse/s50/romstage.c index f876124336..6865877531 100644 --- a/src/mainboard/wyse/s50/romstage.c +++ b/src/mainboard/wyse/s50/romstage.c @@ -31,8 +31,8 @@ #include <cpu/amd/gx2def.h> #include <cpu/amd/geode_post_code.h> #include <spd.h> -#include "southbridge/amd/cs5536/cs5536_early_smbus.c" -#include "southbridge/amd/cs5536/cs5536_early_setup.c" +#include "southbridge/amd/cs5536/early_smbus.c" +#include "southbridge/amd/cs5536/early_setup.c" static inline int spd_read_byte(unsigned int device, unsigned int address) { |