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-rw-r--r--src/mainboard/intel/kblrvp/Kconfig6
-rw-r--r--src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb (renamed from src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb)118
-rw-r--r--src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb138
-rw-r--r--src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb (renamed from src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb)88
-rw-r--r--src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb (renamed from src/mainboard/intel/kblrvp/variants/rvp8/devicetree.cb)91
5 files changed, 158 insertions, 283 deletions
diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig
index 5fa78176e6..e3852894ed 100644
--- a/src/mainboard/intel/kblrvp/Kconfig
+++ b/src/mainboard/intel/kblrvp/Kconfig
@@ -55,7 +55,11 @@ config GBB_HWID
config DEVICETREE
string
- default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
+ default "variants/baseboard/devicetree.cb"
+
+config OVERRIDE_DEVICETREE
+ string
+ default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
config IFD_BIN_PATH
string
diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
index 1f5d1a7124..be9d1dffe8 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
@@ -9,13 +9,12 @@ chip soc/intel/skylake
# Note that GPE events called out in ASL code rely on this
# route. i.e. If this route changes then the affected GPE
# offset bits also need to be changed.
- register "gpe0_dw0" = "GPP_C"
+ register "gpe0_dw0" = "GPP_B"
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
- register "gen2_dec" = "0x000c0201"
# Enable "Intel Speed Shift Technology"
register "speed_shift_enable" = "1"
@@ -24,9 +23,6 @@ chip soc/intel/skylake
register "dptf_enable" = "1"
# FSP Configuration
- register "EnableAzalia" = "1"
- register "DspEnable" = "1"
- register "IoBufferOwnership" = "0"
register "SmbusEnable" = "1"
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
@@ -34,11 +30,7 @@ chip soc/intel/skylake
register "InternalGfx" = "1"
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
- register "HeciEnabled" = "0"
- register "SaGv" = "3"
- register "PmTimerDisabled" = "1"
- register "Cio2Enable" = "1"
- register "SaImguEnable" = "1"
+ register "SaGv" = "SaGv_Enabled"
register "pirqa_routing" = "PCH_IRQ11"
register "pirqb_routing" = "PCH_IRQ10"
@@ -82,7 +74,7 @@ chip soc/intel/skylake
register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
.vr_config_enable = 1, \
.psi1threshold = 0x50, \
- .psi2threshold = 0x14, \
+ .psi2threshold = 0x10, \
.psi3threshold = 0x4, \
.psi3enable = 1, \
.psi4enable = 1, \
@@ -131,93 +123,12 @@ chip soc/intel/skylake
.voltage_limit = 0x5F0 \
}"
- # Enable Root ports.
- # PCIE Port 1 x4 -> SLOT1
- register "PcieRpEnable[0]" = "1"
- register "PcieRpClkReqSupport[0]" = "1"
- register "PcieRpClkReqNumber[0]" = "2"
- # RP1, uses uses CLK SRC 2
- register "PcieRpClkSrcNumber[0]" = "2"
-
- # PCIE Port 5 x1 -> SLOT2/LAN
- register "PcieRpEnable[4]" = "1"
- register "PcieRpClkReqSupport[4]" = "1"
- register "PcieRpClkReqNumber[4]" = "3"
- # RP5, uses uses CLK SRC 3
- register "PcieRpClkSrcNumber[4]" = "3"
-
- # PCIE Port 6 x1 -> SLOT3
- register "PcieRpEnable[5]" = "1"
- register "PcieRpClkReqSupport[5]" = "1"
- register "PcieRpClkReqNumber[5]" = "1"
- # RP6, uses uses CLK SRC 1
- register "PcieRpClkSrcNumber[5]" = "1"
-
- # PCIE Port 7 Disabled
- # PCIE Port 8 Disabled
- # PCIE Port 9 x1 -> WLAN
- register "PcieRpEnable[8]" = "1"
- register "PcieRpClkReqSupport[8]" = "1"
- register "PcieRpClkReqNumber[8]" = "5"
- # RP9, uses uses CLK SRC 5
- register "PcieRpClkSrcNumber[8]" = "5"
-
- # PCIE Port 10 x1 -> WiGig
- register "PcieRpEnable[9]" = "1"
- register "PcieRpClkReqSupport[9]" = "1"
- register "PcieRpClkReqNumber[9]" = "4"
- # RP10, uses uses CLK SRC 4
- register "PcieRpClkSrcNumber[9]" = "4"
-
- # USB 2.0 Enable all ports
- register "usb2_ports[0]" = "USB2_PORT_MAX(OC0)" # TYPE-A Port
- register "usb2_ports[1]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port
- register "usb2_ports[2]" = "USB2_PORT_MAX(OC_SKIP)" # Bluetooth
- register "usb2_ports[4]" = "USB2_PORT_MAX(OC_SKIP)" # Type-A Port
- register "usb2_ports[5]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port
- register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
- register "usb2_ports[7]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
- register "usb2_ports[8]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
- register "usb2_ports[9]" = "USB2_PORT_MAX(OC1)" # TYPE-A Port
- register "usb2_ports[10]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
- register "usb2_ports[11]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
-
- # USB 3.0 Enable Port 1-4. Port 5 & 6 Disabled
- register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # TYPE-A Port
- register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
- register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
- register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # TYPE-A Port
- register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Disabled
- register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Disabled
-
- register "SsicPortEnable" = "1" # Enable SSIC for WWAN
-
- # Must leave UART0 enabled or SD/eMMC will not work as PCI
- register "SerialIoDevMode" = "{ \
- [PchSerialIoIndexI2C0] = PchSerialIoPci, \
- [PchSerialIoIndexI2C1] = PchSerialIoPci, \
- [PchSerialIoIndexI2C2] = PchSerialIoPci, \
- [PchSerialIoIndexI2C3] = PchSerialIoPci, \
- [PchSerialIoIndexI2C4] = PchSerialIoPci, \
- [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \
- [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \
- [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
- [PchSerialIoIndexUart0] = PchSerialIoPci, \
- [PchSerialIoIndexUart1] = PchSerialIoDisabled, \
- [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \
- }"
-
# Send an extra VR mailbox command for the PS4 exit issue
register "SendVrMbxCmd" = "2"
# Enable/Disable VMX feature
register "VmxEnable" = "0"
- # Lock Down
- register "common_soc_config" = "{
- .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
- }"
-
device cpu_cluster 0 on
device lapic 0 on end
end
@@ -239,14 +150,19 @@ chip soc/intel/skylake
device pci 17.0 off end # SATA
device pci 19.0 on end # UART #2
device pci 19.1 off end # I2C #5
- device pci 19.2 on end
- device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1
- device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN
- device pci 1c.5 on end # PCI Express Port 6 x1 SLOT3
+ device pci 19.2 on end # I2C #4
+ device pci 1c.0 on end # PCI Express Port 1
+ device pci 1c.1 off end # PCI Express Port 2
+ device pci 1c.2 off end # PCI Express Port 3
+ device pci 1c.3 off end # PCI Express Port 4
+ device pci 1c.4 off end # PCI Express Port 5
+ device pci 1c.5 off end # PCI Express Port 6
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 off end # PCI Express Port 8
- device pci 1d.0 on end # PCI Express Port 9 x1 WLAN
- device pci 1d.1 on end # PCI Express Port 10 x1 WIGIG
+ device pci 1d.0 on end # PCI Express Port 9
+ device pci 1d.1 off end # PCI Express Port 10
+ device pci 1d.2 off end # PCI Express Port 11
+ device pci 1d.3 off end # PCI Express Port 12
device pci 1e.0 on end # UART #0
device pci 1e.1 off end # UART #1
device pci 1e.2 off end # GSPI #0
@@ -254,11 +170,7 @@ chip soc/intel/skylake
device pci 1e.4 on end # eMMC
device pci 1e.5 off end # SDIO
device pci 1e.6 on end # SDCard
- device pci 1f.0 on
- chip drivers/pc80/tpm
- device pnp 0c31.0 on end
- end
- end # LPC Interface
+ device pci 1f.0 on end # LPC Interface
device pci 1f.1 on end # P2SB
device pci 1f.2 on end # Power Management Controller
device pci 1f.3 on end # Intel HDA
diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
new file mode 100644
index 0000000000..c413cc6982
--- /dev/null
+++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
@@ -0,0 +1,138 @@
+chip soc/intel/skylake
+
+ # GPE configuration
+ register "gpe0_dw0" = "GPP_C"
+
+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+ register "gen2_dec" = "0x000c0201"
+
+ # FSP Configuration
+ register "EnableAzalia" = "1"
+ register "DspEnable" = "1"
+ register "IoBufferOwnership" = "0"
+ register "HeciEnabled" = "0"
+ register "PmTimerDisabled" = "1"
+ register "Cio2Enable" = "1"
+ register "SaImguEnable" = "1"
+
+ # VR Settings Configuration for 4 Domains
+ #+----------------+-------+-------+-------+-------+
+ #| Domain/Setting | SA | IA | GTUS | GTS |
+ #+----------------+-------+-------+-------+-------+
+ #| Psi1Threshold | 20A | 20A | 20A | 20A |
+ #| Psi2Threshold | 5A | 5A | 5A | 5A |
+ #| Psi3Threshold | 1A | 1A | 1A | 1A |
+ #| Psi3Enable | 1 | 1 | 1 | 1 |
+ #| Psi4Enable | 1 | 1 | 1 | 1 |
+ #| ImonSlope | 0 | 0 | 0 | 0 |
+ #| ImonOffset | 0 | 0 | 0 | 0 |
+ #| IccMax | 7A | 34A | 35A | 35A |
+ #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
+ #+----------------+-------+-------+-------+-------+
+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
+ .vr_config_enable = 1, \
+ .psi1threshold = 0x50, \
+ .psi2threshold = 0x14, \
+ .psi3threshold = 0x4, \
+ .psi3enable = 1, \
+ .psi4enable = 1, \
+ .imon_slope = 0x0, \
+ .imon_offset = 0x0, \
+ .icc_max = 0x1C, \
+ .voltage_limit = 0x5F0 \
+ }"
+
+ # Enable Root ports.
+ # PCIE Port 1 x4 -> SLOT1
+ register "PcieRpEnable[0]" = "1"
+ register "PcieRpClkReqSupport[0]" = "1"
+ register "PcieRpClkReqNumber[0]" = "2"
+ # RP1, uses uses CLK SRC 2
+ register "PcieRpClkSrcNumber[0]" = "2"
+
+ # PCIE Port 5 x1 -> SLOT2/LAN
+ register "PcieRpEnable[4]" = "1"
+ register "PcieRpClkReqSupport[4]" = "1"
+ register "PcieRpClkReqNumber[4]" = "3"
+ # RP5, uses uses CLK SRC 3
+ register "PcieRpClkSrcNumber[4]" = "3"
+
+ # PCIE Port 6 x1 -> SLOT3
+ register "PcieRpEnable[5]" = "1"
+ register "PcieRpClkReqSupport[5]" = "1"
+ register "PcieRpClkReqNumber[5]" = "1"
+ # RP6, uses uses CLK SRC 1
+ register "PcieRpClkSrcNumber[5]" = "1"
+
+ # PCIE Port 7 Disabled
+ # PCIE Port 8 Disabled
+ # PCIE Port 9 x1 -> WLAN
+ register "PcieRpEnable[8]" = "1"
+ register "PcieRpClkReqSupport[8]" = "1"
+ register "PcieRpClkReqNumber[8]" = "5"
+ # RP9, uses uses CLK SRC 5
+ register "PcieRpClkSrcNumber[8]" = "5"
+
+ # PCIE Port 10 x1 -> WiGig
+ register "PcieRpEnable[9]" = "1"
+ register "PcieRpClkReqSupport[9]" = "1"
+ register "PcieRpClkReqNumber[9]" = "4"
+ # RP10, uses uses CLK SRC 4
+ register "PcieRpClkSrcNumber[9]" = "4"
+
+ # USB 2.0 Enable all ports
+ register "usb2_ports[0]" = "USB2_PORT_MAX(OC0)" # TYPE-A Port
+ register "usb2_ports[1]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port
+ register "usb2_ports[2]" = "USB2_PORT_MAX(OC_SKIP)" # Bluetooth
+ register "usb2_ports[4]" = "USB2_PORT_MAX(OC_SKIP)" # Type-A Port
+ register "usb2_ports[5]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port
+ register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
+ register "usb2_ports[7]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
+ register "usb2_ports[8]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
+ register "usb2_ports[9]" = "USB2_PORT_MAX(OC1)" # TYPE-A Port
+ register "usb2_ports[10]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
+ register "usb2_ports[11]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
+
+ # USB 3.0 Enable Port 1-4. Port 5 & 6 Disabled
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # TYPE-A Port
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # TYPE-A Port
+ register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Disabled
+ register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Disabled
+
+ register "SsicPortEnable" = "1" # Enable SSIC for WWAN
+
+ # Must leave UART0 enabled or SD/eMMC will not work as PCI
+ register "SerialIoDevMode" = "{ \
+ [PchSerialIoIndexI2C0] = PchSerialIoPci, \
+ [PchSerialIoIndexI2C1] = PchSerialIoPci, \
+ [PchSerialIoIndexI2C2] = PchSerialIoPci, \
+ [PchSerialIoIndexI2C3] = PchSerialIoPci, \
+ [PchSerialIoIndexI2C4] = PchSerialIoPci, \
+ [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \
+ [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \
+ [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
+ [PchSerialIoIndexUart0] = PchSerialIoPci, \
+ [PchSerialIoIndexUart1] = PchSerialIoDisabled, \
+ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \
+ }"
+
+ # Lock Down
+ register "common_soc_config" = "{
+ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+ }"
+
+ device domain 0 on
+ device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1
+ device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN
+ device pci 1c.5 on end # PCI Express Port 6 x1 SLOT3
+ device pci 1d.0 on end # PCI Express Port 9 x1 WLAN
+ device pci 1d.1 on end # PCI Express Port 10 x1 WIGIG
+ device pci 1f.0 on
+ chip drivers/pc80/tpm
+ device pnp 0c31.0 on end
+ end
+ end # LPC Interface
+ end
+end
diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb
index efcf9be3b8..abd9886d17 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb
@@ -9,63 +9,14 @@ chip soc/intel/skylake
# Enable deep Sx states
register "deep_s5_enable_ac" = "1"
register "deep_s5_enable_dc" = "1"
- register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
-
- # GPE configuration
- # Note that GPE events called out in ASL code rely on this
- # route. i.e. If this route changes then the affected GPE
- # offset bits also need to be changed.
- register "gpe0_dw0" = "GPP_B"
- register "gpe0_dw1" = "GPP_D"
- register "gpe0_dw2" = "GPP_E"
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
- register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"
- # Enable "Intel Speed Shift Technology"
- register "speed_shift_enable" = "1"
-
- # Enable DPTF
- register "dptf_enable" = "1"
-
# FSP Configuration
- register "SmbusEnable" = "1"
- register "ScsEmmcEnabled" = "1"
- register "ScsEmmcHs400Enabled" = "1"
- register "ScsSdCardEnabled" = "2"
- register "InternalGfx" = "1"
- register "SkipExtGfxScan" = "1"
- register "Device4Enable" = "1"
register "HeciEnabled" = "0"
- register "SaGv" = "3"
register "PmTimerDisabled" = "1"
- register "pirqa_routing" = "PCH_IRQ11"
- register "pirqb_routing" = "PCH_IRQ10"
- register "pirqc_routing" = "PCH_IRQ11"
- register "pirqd_routing" = "PCH_IRQ11"
- register "pirqe_routing" = "PCH_IRQ11"
- register "pirqf_routing" = "PCH_IRQ11"
- register "pirqg_routing" = "PCH_IRQ11"
- register "pirqh_routing" = "PCH_IRQ11"
-
- # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
- # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
- register "PmConfigSlpS3MinAssert" = "0x02"
-
- # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s
- register "PmConfigSlpS4MinAssert" = "0x04"
-
- # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s
- register "PmConfigSlpSusMinAssert" = "0x03"
-
- # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s
- register "PmConfigSlpAMinAssert" = "0x03"
-
- # Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled
- register "SerialIrqConfigSirqEnable" = "0x01"
-
# VR Settings Configuration for 4 Domains
#+----------------+-------+-------+-------+-------+
#| Domain/Setting | SA | IA | GTUS | GTS |
@@ -199,11 +150,7 @@ chip soc/intel/skylake
[PchSerialIoIndexUart2] = PchSerialIoSkipInit, \
}"
- # Send an extra VR mailbox command for the PS4 exit issue
- register "SendVrMbxCmd" = "2"
- # Enable/Disable VMX feature
- register "VmxEnable" = "0"
# Use default SD card detect GPIO configuration
register "sdcard_cd_gpio_default" = "GPP_G5"
@@ -217,53 +164,18 @@ chip soc/intel/skylake
device lapic 0 on end
end
device domain 0 on
- device pci 00.0 on end # Host Bridge
- device pci 02.0 on end # Integrated Graphics Device
- device pci 14.0 on end # USB xHCI
- device pci 14.1 off end # USB xDCI (OTG)
- device pci 14.2 on end # Thermal Subsystem
- device pci 15.0 on end # I2C #0
- device pci 15.1 on end # I2C #1
device pci 15.2 off end # I2C #2
device pci 15.3 off end # I2C #3
- device pci 16.0 on end # Management Engine Interface 1
- device pci 16.1 off end # Management Engine Interface 2
- device pci 16.2 off end # Management Engine IDE-R
- device pci 16.3 off end # Management Engine KT Redirection
- device pci 16.4 off end # Management Engine Interface 3
device pci 17.0 on end # SATA
- device pci 19.0 on end # UART #2
device pci 19.1 off end # I2C #5
- device pci 19.2 on end #
- device pci 1c.0 on end # PCI Express Port 1
- device pci 1c.1 off end # PCI Express Port 2
device pci 1c.2 on end # PCI Express Port 3
device pci 1c.3 on end # PCI Express Port 4
device pci 1c.4 on end # PCI Express Port 5
device pci 1c.5 on end # PCI Express Port 6
- device pci 1c.6 off end # PCI Express Port 7
- device pci 1c.7 off end # PCI Express Port 8
- device pci 1d.0 on end # PCI Express Port 9
- device pci 1d.1 off end # PCI Express Port 10
- device pci 1d.2 off end # PCI Express Port 11
- device pci 1d.3 off end # PCI Express Port 12
- device pci 1e.0 on end # UART #0
- device pci 1e.1 off end # UART #1
- device pci 1e.2 off end # GSPI #0
- device pci 1e.3 off end # GSPI #1
- device pci 1e.4 on end # eMMC
- device pci 1e.5 off end # SDIO
- device pci 1e.6 on end # SDCard
device pci 1f.0 on
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
end # LPC Interface
- device pci 1f.1 on end # P2SB
- device pci 1f.2 on end # Power Management Controller
- device pci 1f.3 on end # Intel HDA
- device pci 1f.4 on end # SMBus
- device pci 1f.5 on end # PCH SPI
- device pci 1f.6 off end # GbE
end
end
diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/devicetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
index 0057a288a4..9753c64e26 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp8/devicetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
@@ -3,63 +3,13 @@ chip soc/intel/skylake
# Enable deep Sx states
register "deep_s3_enable_ac" = "0"
register "deep_s3_enable_dc" = "0"
- register "deep_s5_enable_ac" = "0"
- register "deep_s5_enable_dc" = "0"
- register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
-
- # GPE configuration
- # Note that GPE events called out in ASL code rely on this
- # route. i.e. If this route changes then the affected GPE
- # offset bits also need to be changed.
- register "gpe0_dw0" = "GPP_B"
- register "gpe0_dw1" = "GPP_D"
- register "gpe0_dw2" = "GPP_E"
-
- # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
- register "gen1_dec" = "0x00fc0801"
-
- # Enable "Intel Speed Shift Technology"
- register "speed_shift_enable" = "1"
-
- # Enable DPTF
- register "dptf_enable" = "1"
# FSP Configuration
- register "SmbusEnable" = "1"
register "ScsEmmcEnabled" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "ScsSdCardEnabled" = "0"
- register "InternalGfx" = "1"
- register "SkipExtGfxScan" = "1"
- register "Device4Enable" = "1"
register "HeciEnabled" = "0"
- register "SaGv" = "3"
register "PmTimerDisabled" = "0"
-
- register "pirqa_routing" = "PCH_IRQ11"
- register "pirqb_routing" = "PCH_IRQ10"
- register "pirqc_routing" = "PCH_IRQ11"
- register "pirqd_routing" = "PCH_IRQ11"
- register "pirqe_routing" = "PCH_IRQ11"
- register "pirqf_routing" = "PCH_IRQ11"
- register "pirqg_routing" = "PCH_IRQ11"
- register "pirqh_routing" = "PCH_IRQ11"
-
- # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
- # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
- register "PmConfigSlpS3MinAssert" = "0x02"
-
- # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s
- register "PmConfigSlpS4MinAssert" = "0x04"
-
- # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s
- register "PmConfigSlpSusMinAssert" = "0x03"
-
- # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s
- register "PmConfigSlpAMinAssert" = "0x03"
-
- # Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled
- register "SerialIrqConfigSirqEnable" = "0x01"
register "SerialIrqConfigSirqMode" = "0x01"
# VR Settings Configuration for 5 Domains
@@ -205,66 +155,25 @@ chip soc/intel/skylake
# PL2 override 25W
register "tdp_pl2_override" = "25"
- # Send an extra VR mailbox command for the PS4 exit issue
- register "SendVrMbxCmd" = "2"
-
- # Enable/Disable VMX feature
- register "VmxEnable" = "0"
-
# Use default SD card detect GPIO configuration
#register "sdcard_cd_gpio_default" = "GPP_D10"
- device cpu_cluster 0 on
- device lapic 0 on end
- end
device domain 0 on
- device pci 00.0 on end # Host Bridge
- device pci 02.0 on end # Integrated Graphics Device
- device pci 14.0 on end # USB xHCI
- device pci 14.1 off end # USB xDCI (OTG)
- device pci 14.2 on end # Thermal Subsystem
- device pci 15.0 on end # I2C #0
- device pci 15.1 on end # I2C #1
- device pci 15.2 on end # I2C #2
- device pci 15.3 on end # I2C #3
- device pci 16.0 on end # Management Engine Interface 1
- device pci 16.1 off end # Management Engine Interface 2
- device pci 16.2 off end # Management Engine IDE-R
- device pci 16.3 off end # Management Engine KT Redirection
- device pci 16.4 off end # Management Engine Interface 3
device pci 17.0 on end # SATA
- device pci 19.0 on end # UART #2
device pci 19.1 on end # I2C #5
- device pci 19.2 on end # I2C #4
device pci 1c.0 off end # PCI Express Port 1
- device pci 1c.1 off end # PCI Express Port 2
device pci 1c.2 on end # PCI Express Port 3
device pci 1c.3 on end # PCI Express Port 4
device pci 1c.4 on end # PCI Express Port 5
- device pci 1c.5 off end # PCI Express Port 6
- device pci 1c.6 off end # PCI Express Port 7
- device pci 1c.7 off end # PCI Express Port 8
- device pci 1d.0 on end # PCI Express Port 9
- device pci 1d.1 off end # PCI Express Port 10
- device pci 1d.2 off end # PCI Express Port 11
- device pci 1d.3 off end # PCI Express Port 12
- device pci 1e.0 on end # UART #0
device pci 1e.1 on end # UART #1
device pci 1e.2 on end # GSPI #0
device pci 1e.3 on end # GSPI #1
device pci 1e.4 off end # eMMC
- device pci 1e.5 off end # SDIO
- device pci 1e.6 on end # SDCard
device pci 1f.0 on
#chip drivers/pc80/tpm
# device pnp 0c31.0 on end
#end
end # LPC Interface
- device pci 1f.1 on end # P2SB
- device pci 1f.2 on end # Power Management Controller
- device pci 1f.3 on end # Intel HDA
- device pci 1f.4 on end # SMBus
- device pci 1f.5 on end # PCH SPI
device pci 1f.6 on end # GbE
end
end
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-28 09:35:53 +0000