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-rw-r--r--src/mainboard/google/skyrim/variants/crystaldrift/overridetree.cb17
1 files changed, 13 insertions, 4 deletions
diff --git a/src/mainboard/google/skyrim/variants/crystaldrift/overridetree.cb b/src/mainboard/google/skyrim/variants/crystaldrift/overridetree.cb
index 657fdb454b..d42dea7478 100644
--- a/src/mainboard/google/skyrim/variants/crystaldrift/overridetree.cb
+++ b/src/mainboard/google/skyrim/variants/crystaldrift/overridetree.cb
@@ -22,10 +22,6 @@ end
chip soc/amd/mendocino
- # Set Package Power Parameters
- # Remove the sustained_power_limit_mW when STT is enabled
- register "sustained_power_limit_mW" = "15000"
-
device domain 0 on
device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A
device ref xhci_1 on # XHCI1 controller
@@ -131,4 +127,17 @@ chip soc/amd/mendocino
end
end
end # I2C2
+
+ # Enable STT support
+ register "stt_control" = "1"
+ register "stt_pcb_sensor_count" = "2"
+ register "stt_min_limit" = "15000"
+ register "stt_m1" = "0x0555"
+ register "stt_m2" = "0xFDE4"
+ register "stt_c_apu" = "0x021A"
+ register "stt_alpha_apu" = "0x199A"
+ register "stt_skin_temp_apu" = "0x3000"
+ register "stt_error_coeff" = "0xA4"
+ register "stt_error_rate_coefficient" = "0x0E98"
+
end # chip soc/amd/mendocino