3 files changed, 23 insertions, 2 deletions
diff --git a/src/mainboard/google/snow/Kconfig b/src/mainboard/google/snow/Kconfig
index 6face944bb..85b90a5a3a 100644
--- a/src/mainboard/google/snow/Kconfig
+++ b/src/mainboard/google/snow/Kconfig
@@ -1,7 +1,7 @@
 ##
 ## This file is part of the coreboot project.
 ##
-## Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
+## Copyright 2013 Google Inc.
 ##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
@@ -29,6 +29,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select DRIVER_MAXIM_MAX77686
 #	select HAVE_ACPI_TABLES
 #	select MMCONF_SUPPORT
+	select EXYNOS_DISPLAYPORT
 	select CHROMEOS
 
 config MAINBOARD_DIR
diff --git a/src/mainboard/google/snow/devicetree.cb b/src/mainboard/google/snow/devicetree.cb
index 4c88ea8e98..5ad786ef55 100644
--- a/src/mainboard/google/snow/devicetree.cb
+++ b/src/mainboard/google/snow/devicetree.cb
@@ -28,5 +28,19 @@ device domain 0 on
 		device i2c 6 on end # ?
 		device i2c 9 on end # ?
 	end
+	chip cpu/samsung/exynos5-common/displayport
+		register "xres" = "1366"
+		register "yres" = "768"
+		register "bpp" = "16"
+		# complex magic timing!
+		register "clkval_f" = "2"
+		register "upper_margin" = "14"
+		register "lower_margin" = "3"
+		register "vsync" = "5"
+		register "left_margin" = "80"
+		register "right_margin" = "48"
+		register "hsync" = "32"
+		register "lcdbase" = "0x10000000"
+	end
 end
 end
diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c
index 25c0846a07..8de4381d03 100644
--- a/src/mainboard/google/snow/romstage.c
+++ b/src/mainboard/google/snow/romstage.c
@@ -31,7 +31,6 @@
 #include <cpu/samsung/exynos5250/setup.h>
 #include <cpu/samsung/exynos5250/periph.h>
 #include <cpu/samsung/exynos5250/clock_init.h>
-
 #include <console/console.h>
 #include <arch/stages.h>
 
@@ -68,6 +67,11 @@ static void initialize_s5p_mshc(void) {
 	exynos_pinmux_config(PERIPH_ID_SDMMC2, 0);
 }
 
+static void graphics(void)
+{
+
+	exynos_pinmux_config(PERIPH_ID_DPHPD, 0);
+}
 void main(void)
 {
 	struct mem_timings *mem;
@@ -106,6 +110,8 @@ void main(void)
 
 	initialize_s5p_mshc();
 
+	graphics();
+
 	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");
 	printk(BIOS_INFO, "entry is 0x%p, leaving romstage.\n", entry);