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-rw-r--r--src/mainboard/advansus/a785e-i/mainboard.c11
-rw-r--r--src/mainboard/amd/bimini_fam10/mainboard.c14
-rw-r--r--src/mainboard/amd/mahogany_fam10/mainboard.c6
-rw-r--r--src/mainboard/amd/tilapia_fam10/mainboard.c7
-rw-r--r--src/mainboard/asus/m4a78-em/mainboard.c8
-rw-r--r--src/mainboard/asus/m4a785-m/mainboard.c7
-rw-r--r--src/mainboard/asus/m5a88-v/mainboard.c11
-rw-r--r--src/mainboard/avalue/eax-785e/mainboard.c11
-rw-r--r--src/mainboard/gigabyte/ma785gm/mainboard.c7
-rw-r--r--src/mainboard/gigabyte/ma785gmt/mainboard.c7
-rw-r--r--src/mainboard/gigabyte/ma78gm/mainboard.c6
-rw-r--r--src/mainboard/iei/kino-780am2-fam10/mainboard.c11
-rw-r--r--src/mainboard/jetway/pa78vm5/mainboard.c7
13 files changed, 18 insertions, 95 deletions
diff --git a/src/mainboard/advansus/a785e-i/mainboard.c b/src/mainboard/advansus/a785e-i/mainboard.c
index b5a2ea82db..1381dfa352 100644
--- a/src/mainboard/advansus/a785e-i/mainboard.c
+++ b/src/mainboard/advansus/a785e-i/mainboard.c
@@ -23,9 +23,6 @@
#include <device/pci_def.h>
#include "southbridge/amd/rs780/rs780.h"
-void set_pcie_dereset(void);
-void set_pcie_reset(void);
-
/* GPIO6. */
static void enable_int_gfx(void)
{
@@ -45,14 +42,6 @@ static void enable_int_gfx(void)
*(gpio_reg + 170) = 0x0;
}
-void set_pcie_dereset()
-{
-}
-
-void set_pcie_reset(void)
-{
-}
-
int is_dev3_present(void)
{
return 0;
diff --git a/src/mainboard/amd/bimini_fam10/mainboard.c b/src/mainboard/amd/bimini_fam10/mainboard.c
index b6347ebc37..3fa2405739 100644
--- a/src/mainboard/amd/bimini_fam10/mainboard.c
+++ b/src/mainboard/amd/bimini_fam10/mainboard.c
@@ -24,9 +24,6 @@
#include <southbridge/amd/sb800/sb800.h>
#include "southbridge/amd/rs780/rs780.h"
-void set_pcie_dereset(void);
-void set_pcie_reset(void);
-
/* GPIO6. */
static void enable_int_gfx(void)
{
@@ -58,16 +55,9 @@ static void enable_int_gfx(void)
/*
* Bimini uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to
* pull it up before training the slot.
+ *
+ * Old comment says: GPIO 50h to reset PCIe slot.
***/
-void set_pcie_dereset(void)
-{
- /* GPIO 50h reset PCIe slot */
-}
-
-void set_pcie_reset(void)
-{
- /* GPIO 50h reset PCIe slot */
-}
int is_dev3_present(void)
{
diff --git a/src/mainboard/amd/mahogany_fam10/mainboard.c b/src/mainboard/amd/mahogany_fam10/mainboard.c
index 53a8290685..a4a26e026c 100644
--- a/src/mainboard/amd/mahogany_fam10/mainboard.c
+++ b/src/mainboard/amd/mahogany_fam10/mainboard.c
@@ -24,13 +24,11 @@
#include "southbridge/amd/sb700/smbus.h"
#include "southbridge/amd/rs780/rs780.h"
-void set_pcie_dereset(void);
-void set_pcie_reset(void);
/*
* Mahogany uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to
* pull it up before training the slot.
***/
-void set_pcie_dereset()
+void set_pcie_dereset(void)
{
u16 word;
struct device *sm_dev;
@@ -43,7 +41,7 @@ void set_pcie_dereset()
pci_write_config16(sm_dev, 0xA8, word);
}
-void set_pcie_reset()
+void set_pcie_reset(void)
{
u16 word;
struct device *sm_dev;
diff --git a/src/mainboard/amd/tilapia_fam10/mainboard.c b/src/mainboard/amd/tilapia_fam10/mainboard.c
index e8a08a53c1..44c1df69ba 100644
--- a/src/mainboard/amd/tilapia_fam10/mainboard.c
+++ b/src/mainboard/amd/tilapia_fam10/mainboard.c
@@ -34,10 +34,7 @@
#define ADT7461_write_byte(address, val) \
do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
-void set_pcie_dereset(void);
-void set_pcie_reset(void);
-
-void set_pcie_dereset()
+void set_pcie_dereset(void)
{
u8 byte;
u16 word;
@@ -62,7 +59,7 @@ void set_pcie_dereset()
pci_write_config16(sm_dev, 0x7e, word);
}
-void set_pcie_reset()
+void set_pcie_reset(void)
{
u8 byte;
u16 word;
diff --git a/src/mainboard/asus/m4a78-em/mainboard.c b/src/mainboard/asus/m4a78-em/mainboard.c
index e80d39b0e8..87acc5674c 100644
--- a/src/mainboard/asus/m4a78-em/mainboard.c
+++ b/src/mainboard/asus/m4a78-em/mainboard.c
@@ -24,11 +24,7 @@
#include "southbridge/amd/sb700/smbus.h"
#include "southbridge/amd/rs780/rs780.h"
-
-void set_pcie_dereset(void);
-void set_pcie_reset(void);
-
-void set_pcie_dereset()
+void set_pcie_dereset(void)
{
u8 byte;
u16 word;
@@ -53,7 +49,7 @@ void set_pcie_dereset()
pci_write_config16(sm_dev, 0x7e, word);
}
-void set_pcie_reset()
+void set_pcie_reset(void)
{
u8 byte;
u16 word;
diff --git a/src/mainboard/asus/m4a785-m/mainboard.c b/src/mainboard/asus/m4a785-m/mainboard.c
index 42a9f644e3..5acce51969 100644
--- a/src/mainboard/asus/m4a785-m/mainboard.c
+++ b/src/mainboard/asus/m4a785-m/mainboard.c
@@ -34,10 +34,7 @@
#define ADT7461_write_byte(address, val) \
do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
-void set_pcie_dereset(void);
-void set_pcie_reset(void);
-
-void set_pcie_dereset()
+void set_pcie_dereset(void)
{
u8 byte;
u16 word;
@@ -62,7 +59,7 @@ void set_pcie_dereset()
pci_write_config16(sm_dev, 0x7e, word);
}
-void set_pcie_reset()
+void set_pcie_reset(void)
{
u8 byte;
u16 word;
diff --git a/src/mainboard/asus/m5a88-v/mainboard.c b/src/mainboard/asus/m5a88-v/mainboard.c
index 4ec716e96a..75f231e74b 100644
--- a/src/mainboard/asus/m5a88-v/mainboard.c
+++ b/src/mainboard/asus/m5a88-v/mainboard.c
@@ -23,9 +23,6 @@
#include <device/pci_def.h>
#include "southbridge/amd/rs780/rs780.h"
-void set_pcie_dereset(void);
-void set_pcie_reset(void);
-
/* GPIO6. */
static void enable_int_gfx(void)
{
@@ -45,14 +42,6 @@ static void enable_int_gfx(void)
*(gpio_reg + 170) = 0x0;
}
-void set_pcie_dereset()
-{
-}
-
-void set_pcie_reset(void)
-{
-}
-
int is_dev3_present(void)
{
return 0;
diff --git a/src/mainboard/avalue/eax-785e/mainboard.c b/src/mainboard/avalue/eax-785e/mainboard.c
index 4d2f0ff42d..79564a288f 100644
--- a/src/mainboard/avalue/eax-785e/mainboard.c
+++ b/src/mainboard/avalue/eax-785e/mainboard.c
@@ -23,9 +23,6 @@
#include <device/pci_def.h>
#include "southbridge/amd/rs780/rs780.h"
-void set_pcie_dereset(void);
-void set_pcie_reset(void);
-
/* GPIO6. */
static void enable_int_gfx(void)
{
@@ -45,14 +42,6 @@ static void enable_int_gfx(void)
*(gpio_reg + 170) = 0x0;
}
-void set_pcie_dereset()
-{
-}
-
-void set_pcie_reset(void)
-{
-}
-
int is_dev3_present(void)
{
return 1;
diff --git a/src/mainboard/gigabyte/ma785gm/mainboard.c b/src/mainboard/gigabyte/ma785gm/mainboard.c
index 37a3828f94..8fbc591c86 100644
--- a/src/mainboard/gigabyte/ma785gm/mainboard.c
+++ b/src/mainboard/gigabyte/ma785gm/mainboard.c
@@ -24,10 +24,7 @@
#include "southbridge/amd/sb700/smbus.h"
#include "southbridge/amd/rs780/rs780.h"
-void set_pcie_dereset(void);
-void set_pcie_reset(void);
-
-void set_pcie_dereset()
+void set_pcie_dereset(void)
{
u8 byte;
u16 word;
@@ -52,7 +49,7 @@ void set_pcie_dereset()
pci_write_config16(sm_dev, 0x7e, word);
}
-void set_pcie_reset()
+void set_pcie_reset(void)
{
u8 byte;
u16 word;
diff --git a/src/mainboard/gigabyte/ma785gmt/mainboard.c b/src/mainboard/gigabyte/ma785gmt/mainboard.c
index ce186bf587..48545a4535 100644
--- a/src/mainboard/gigabyte/ma785gmt/mainboard.c
+++ b/src/mainboard/gigabyte/ma785gmt/mainboard.c
@@ -34,10 +34,7 @@
#define ADT7461_write_byte(address, val) \
do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
-void set_pcie_dereset(void);
-void set_pcie_reset(void);
-
-void set_pcie_dereset()
+void set_pcie_dereset(void)
{
u8 byte;
u16 word;
@@ -62,7 +59,7 @@ void set_pcie_dereset()
pci_write_config16(sm_dev, 0x7e, word);
}
-void set_pcie_reset()
+void set_pcie_reset(void)
{
u8 byte;
u16 word;
diff --git a/src/mainboard/gigabyte/ma78gm/mainboard.c b/src/mainboard/gigabyte/ma78gm/mainboard.c
index 3e73f229e9..bfd083497e 100644
--- a/src/mainboard/gigabyte/ma78gm/mainboard.c
+++ b/src/mainboard/gigabyte/ma78gm/mainboard.c
@@ -25,13 +25,11 @@
#include "southbridge/amd/sb700/smbus.h"
#include "southbridge/amd/rs780/rs780.h"
-void set_pcie_dereset(void);
-void set_pcie_reset(void);
/*
* ma78gm-us2h uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to
* pull it up before training the slot.
***/
-void set_pcie_dereset()
+void set_pcie_dereset(void)
{
u16 word;
struct device *sm_dev;
@@ -44,7 +42,7 @@ void set_pcie_dereset()
pci_write_config16(sm_dev, 0xA8, word);
}
-void set_pcie_reset()
+void set_pcie_reset(void)
{
u16 word;
struct device *sm_dev;
diff --git a/src/mainboard/iei/kino-780am2-fam10/mainboard.c b/src/mainboard/iei/kino-780am2-fam10/mainboard.c
index f75bec2f9f..b0ffef71f2 100644
--- a/src/mainboard/iei/kino-780am2-fam10/mainboard.c
+++ b/src/mainboard/iei/kino-780am2-fam10/mainboard.c
@@ -24,21 +24,10 @@
#include "southbridge/amd/sb700/smbus.h"
#include "southbridge/amd/rs780/rs780.h"
-void set_pcie_dereset(void);
-void set_pcie_reset(void);
/* TODO - Need to find GPIO for PCIE slot.
* Kino uses GPIO ? as PCIe slot reset, GPIO? as GFX slot reset. We need to
* pull it up before training the slot.
***/
-void set_pcie_dereset()
-{
- /* PCIE slot not yet supported.*/
-}
-
-void set_pcie_reset()
-{
- /* PCIE slot not yet supported.*/
-}
int is_dev3_present(void)
{
diff --git a/src/mainboard/jetway/pa78vm5/mainboard.c b/src/mainboard/jetway/pa78vm5/mainboard.c
index 906b070569..9585832ebe 100644
--- a/src/mainboard/jetway/pa78vm5/mainboard.c
+++ b/src/mainboard/jetway/pa78vm5/mainboard.c
@@ -25,14 +25,11 @@
#include "southbridge/amd/sb700/smbus.h"
#include "southbridge/amd/rs780/rs780.h"
-void set_pcie_dereset(void);
-void set_pcie_reset(void);
-
/*
* the board uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to
* pull it up before training the slot.
***/
-void set_pcie_dereset()
+void set_pcie_dereset(void)
{
u16 word;
struct device *sm_dev;
@@ -45,7 +42,7 @@ void set_pcie_dereset()
pci_write_config16(sm_dev, 0xA8, word);
}
-void set_pcie_reset()
+void set_pcie_reset(void)
{
u16 word;
struct device *sm_dev;
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-24 19:08:01 +0000